mirror of
https://github.com/WangXuan95/FTDI-245fifo-interface.git
synced 2025-01-14 06:42:52 +08:00
123 lines
4.8 KiB
Verilog
123 lines
4.8 KiB
Verilog
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//--------------------------------------------------------------------------------------------------------
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// Module : tb_ftdi_245fifo
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// Type : simulation, top
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// Standard: Verilog 2001 (IEEE1364-2001)
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// Function: top-level testbench for ftdi_245fifo_top
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//--------------------------------------------------------------------------------------------------------
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`timescale 1ps/1ps
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module tb_ftdi_245fifo ();
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// -----------------------------------------------------------------------------------------------------------------------------
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// simulation control
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// -----------------------------------------------------------------------------------------------------------------------------
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initial $dumpvars(0, tb_ftdi_245fifo);
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//initial #(1000 * 1000 * 1000 * 1000) $finish;
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initial #( 100 * 1000 * 1000) $finish;
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// ms us ns ps
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// -----------------------------------------------------------------------------------------------------------------------------
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// FTDI chip signals
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// -----------------------------------------------------------------------------------------------------------------------------
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localparam CHIP_TYPE = "FTx232H"; // can be "FTx232H", "FT600", "FT601"
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localparam CHIP_EW = (CHIP_TYPE=="FT601") ? 2 : (CHIP_TYPE=="FT600") ? 1 : 0;
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wire ftdi_clk;
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wire ftdi_rxf_n;
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wire ftdi_txe_n;
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wire ftdi_oe_n;
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wire ftdi_rd_n;
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wire ftdi_wr_n;
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tri [(8<<CHIP_EW)-1:0] ftdi_data;
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tri [(1<<CHIP_EW)-1:0] ftdi_be;
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// -----------------------------------------------------------------------------------------------------------------------------
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// user signals(loopback)
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// -----------------------------------------------------------------------------------------------------------------------------
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localparam USER_EW = 0;
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wire tready;
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wire tvalid;
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wire [(8<<USER_EW)-1:0] tdata;
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wire [(1<<USER_EW)-1:0] tkeep;
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wire tlast;
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// -----------------------------------------------------------------------------------------------------------------------------
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// user clock
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// -----------------------------------------------------------------------------------------------------------------------------
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reg rstn = 1'b0;
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reg clk = 1'b0;
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always #5000 clk = ~clk; // 100MHz
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initial begin repeat(4) @(posedge clk); rstn<=1'b1; end
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// -----------------------------------------------------------------------------------------------------------------------------
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// generate a simple FT232H behavior
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// -----------------------------------------------------------------------------------------------------------------------------
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tb_ftdi_chip_model # (
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.CHIP_EW ( CHIP_EW )
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) u_tb_ftdi_chip_model (
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.ftdi_clk ( ftdi_clk ),
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.ftdi_rxf_n ( ftdi_rxf_n ),
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.ftdi_txe_n ( ftdi_txe_n ),
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.ftdi_oe_n ( ftdi_oe_n ),
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.ftdi_rd_n ( ftdi_rd_n ),
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.ftdi_wr_n ( ftdi_wr_n ),
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.ftdi_data ( ftdi_data ),
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.ftdi_be ( ftdi_be )
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);
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// -----------------------------------------------------------------------------------------------------------------------------
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// ftdi_245fifo_top module
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// -----------------------------------------------------------------------------------------------------------------------------
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ftdi_245fifo_top #(
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.TX_EW ( USER_EW ),
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.TX_EA ( 10 ),
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.RX_EW ( USER_EW ),
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.RX_EA ( 10 ),
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.CHIP_TYPE ( CHIP_TYPE ),
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.SIMULATION ( 1 )
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) u_ftdi_245fifo_top (
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.rstn_async ( rstn ),
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// user write interface, loopback connect to user read interface
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.tx_clk ( clk ),
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.tx_tready ( tready ),
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.tx_tvalid ( tvalid ),
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.tx_tdata ( tdata ),
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.tx_tkeep ( tkeep ),
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.tx_tlast ( tlast ),
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// user read interface, loopback connect to user write interface
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.rx_clk ( clk ),
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.rx_tready ( tready ),
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.rx_tvalid ( tvalid ),
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.rx_tdata ( tdata ),
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.rx_tkeep ( tkeep ),
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.rx_tlast ( tlast ),
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// FTDI USB interface, must connect to FT232H pins
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.ftdi_clk ( ftdi_clk ),
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.ftdi_rxf_n ( ftdi_rxf_n ),
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.ftdi_txe_n ( ftdi_txe_n ),
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.ftdi_oe_n ( ftdi_oe_n ),
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.ftdi_rd_n ( ftdi_rd_n ),
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.ftdi_wr_n ( ftdi_wr_n ),
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.ftdi_data ( ftdi_data ),
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.ftdi_be ( ftdi_be )
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);
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endmodule
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