mirror of
https://github.com/WangXuan95/FTDI-245fifo-interface.git
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89 lines
4.0 KiB
Python
89 lines
4.0 KiB
Python
#-*- coding:utf-8 -*-
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# Python3
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#
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# This program is a test of FPGA+FTDI USB chips (FT232H, FT600, or FT601)
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# It sends random data block to FTDI chip. The blocks all ends with 0xFF. Except for the last byte, all other bytes are not 0xFF
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# when the FPGA receives the block, it calculates its CRC. When meeting 0xFF, the FPGA send CRC of the block via FTDI chip
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# Finally, the program will verify whether the CRC value is the same as the calculated CRC value.
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#
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# The corresponding FPGA top-level design can be found in fpga_top_ft232h_rx_crc.v (if you are using FT232H or FT2232H chips)
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# Or see fpga_top_ft600_rx_crc.v (if you are using an FT600 chip)
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#
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from USB_FTX232H_FT60X import USB_FTX232H_FT60X_sync245mode # see USB_FTX232H_FT60X.py
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from random import randint
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import time
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def rand_data (minlen, maxlen) :
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minlen = max(1, minlen)
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maxlen = max(minlen, maxlen)
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length = randint(minlen, maxlen)
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array = [randint(0, 0xFE) for i in range(length)]
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return bytes(array)
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def calc_crc (data) :
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TABLE_CRC = (0x00000000, 0x1db71064, 0x3b6e20c8, 0x26d930ac, 0x76dc4190, 0x6b6b51f4, 0x4db26158, 0x5005713c, 0xedb88320, 0xf00f9344, 0xd6d6a3e8, 0xcb61b38c, 0x9b64c2b0, 0x86d3d2d4, 0xa00ae278, 0xbdbdf21c)
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crc = 0xFFFFFFFF
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for byte in data :
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crc ^= byte
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crc = TABLE_CRC[crc & 0xF] ^ (crc >> 4)
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crc = TABLE_CRC[crc & 0xF] ^ (crc >> 4)
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return crc
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data_list = [ # this list will contains several data blocks and their CRC
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[ data, calc_crc(data) ]
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for data in [ # Note that each block of data end with 0xFF, since FPGA start to send CRC when meeting 0xFF (see rx_calc_crc.v)
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b'\xFF' , # block length = 1
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rand_data( 1 , 1 ) + b'\xFF' , # block length = 2
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rand_data( 2 , 2 ) + b'\xFF' , # block length = 3
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rand_data(2000000, 3000000) + b'\xFF' , # block length = 2000001 ~ 3000001
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rand_data(2000000, 3000000) + b'\xFF' , # block length = 2000001 ~ 3000001
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rand_data(2000000, 3000000) + b'\xFF' # block length = 2000001 ~ 3000001
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]
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]
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TEST_COUNT = 50
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if __name__ == '__main__':
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usb = USB_FTX232H_FT60X_sync245mode(device_to_open_list =
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(('FTX232H', 'USB <-> Serial Converter' ), # firstly try to open FTX232H (FT232H or FT2232H) device named 'USB <-> Serial Converter'. Note that 'USB <-> Serial Converter' is the default name of FT232H or FT2232H chip unless the user has modified it. If the chip's name has been modified, you can use FT_Prog software to look up it.
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('FT60X' , 'FTDI SuperSpeed-FIFO Bridge')) # secondly try to open FT60X (FT600 or FT601) device named 'FTDI SuperSpeed-FIFO Bridge'. Note that 'FTDI SuperSpeed-FIFO Bridge' is the default name of FT600 or FT601 chip unless the user has modified it.
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)
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total_tx_len = 0
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time_start = time.time()
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for i in range (TEST_COUNT) :
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txdata, tx_crc = data_list[ randint(0, len(data_list)-1) ] # randomly select one data block, and get its CRC
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usb.send(txdata)
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rxdata = usb.recv(4) # recv 4 bytes
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rx_crc = (rxdata[3]<<24) + (rxdata[2]<<16) + (rxdata[1]<<8) + (rxdata[0]<<0) # regard the 4 bytes as CRC
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total_tx_len += len(txdata)
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time_total = time.time() - time_start
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data_rate = total_tx_len / (time_total + 0.001) / 1e3
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print('[%d/%d] tx_len=%d crc=%08x total_tx_len=%d data_rate=%.0f kB/s' % (i+1, TEST_COUNT, len(txdata), rx_crc, total_tx_len, data_rate) )
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if tx_crc != rx_crc :
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print('*** tx_crc (%08x) and rx_crc (%08x) mismatch' % (tx_crc, rx_crc) )
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break
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usb.close()
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