mirror of
https://github.com/WangXuan95/FTDI-245fifo-interface.git
synced 2025-01-14 06:42:52 +08:00
130 lines
3.9 KiB
Verilog
130 lines
3.9 KiB
Verilog
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//--------------------------------------------------------------------------------------------------------
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// Module : tb_ftdi_245fifo
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// Type : simulation
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// Standard: Verilog 2001 (IEEE1364-2001)
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// Function: simple FT232H / FT600 / FT601 chip model
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//--------------------------------------------------------------------------------------------------------
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`timescale 1ps/1ps
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module tb_ftdi_chip_model #(
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parameter CHIP_EW = 0 // FTDI USB chip data width, 0=8bit, 1=16bit, 2=32bit. for FT232H is 0, for FT600 is 1, for FT601 is 2.
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) (
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output reg ftdi_clk,
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output reg ftdi_rxf_n,
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output reg ftdi_txe_n,
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input wire ftdi_oe_n,
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input wire ftdi_rd_n,
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input wire ftdi_wr_n,
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inout [(8<<CHIP_EW)-1:0] ftdi_data,
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inout [(1<<CHIP_EW)-1:0] ftdi_be
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);
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//---------------------------------------------------------------------------------------------------------------------------------------------------------------
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// function : generate random unsigned integer
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//---------------------------------------------------------------------------------------------------------------------------------------------------------------
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function [31:0] randuint;
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input [31:0] min;
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input [31:0] max;
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begin
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randuint = $random;
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if ( min != 0 || max != 'hFFFFFFFF )
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randuint = (randuint % (1+max-min)) + min;
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end
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endfunction
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wire [(8<<CHIP_EW)-1:0] DATA_HIGHZ = {(8<<CHIP_EW){1'bz}};
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localparam [(8<<CHIP_EW)-1:0] DATA_ZERO = {(8<<CHIP_EW){1'b0}};
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wire [(1<<CHIP_EW)-1:0] BE_HIGHZ = {(1<<CHIP_EW){1'bz}};
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localparam [(1<<CHIP_EW)-1:0] BE_ZERO = {(1<<CHIP_EW){1'b0}};
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localparam [(1<<CHIP_EW)-1:0] BE_ALL_ONE = ~BE_ZERO;
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initial ftdi_clk = 1'b0; // generate FTDI chip clock
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always #8333 ftdi_clk = ~ftdi_clk; // approximately 60MHz.
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reg [(8<<CHIP_EW)-1:0] ftdi_r_data = DATA_ZERO;
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reg [(1<<CHIP_EW)-1:0] ftdi_r_be = BE_ZERO;
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reg [(8<<CHIP_EW)-1:0] tmp_data = DATA_ZERO;
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reg [(8<<CHIP_EW)-1:0] tmp_be = (CHIP_EW==0) ? 1 : BE_ZERO;
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reg [7:0] rxbyte = (CHIP_EW==0) ? 8'h01 : 8'h00;
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integer i;
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always @ (posedge ftdi_clk) // data from FTDI-Chip to FPGA (read from FTDI-Chip)
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if (~ftdi_rd_n & ~ftdi_rxf_n) begin
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tmp_data = ftdi_r_data;
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tmp_be = (CHIP_EW==0) ? BE_ALL_ONE : randuint(0, 'hFFFFFFFF);
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for (i=0; i<(1<<CHIP_EW); i=i+1) begin
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if (tmp_be[i]) begin
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//$write(" %02X", rxbyte);
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tmp_data[8*i +: 8] = rxbyte;
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rxbyte = rxbyte + 1;
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end
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end
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ftdi_r_data <= tmp_data;
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ftdi_r_be <= tmp_be;
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end
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reg [7:0] txbyte = 8'h00;
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always @ (posedge ftdi_clk) // data from FPGA to FTDI-Chip (write to FTDI-Chip)
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if (~ftdi_wr_n & ~ftdi_txe_n) begin
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for (i=0; i<(1<<CHIP_EW); i=i+1) begin
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if (ftdi_be[i]) begin
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$write(" %02X", ftdi_data[8*i +: 8] );
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if (txbyte !== ftdi_data[8*i +: 8]) begin $display("*** error : data incorrect"); $stop; end
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txbyte = txbyte + 1;
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end
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end
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end
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assign ftdi_data = ftdi_oe_n ? DATA_HIGHZ : ftdi_r_data;
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assign ftdi_be = ftdi_oe_n ? BE_HIGHZ : ftdi_r_be;
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initial begin
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ftdi_rxf_n <= 1'b1;
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while (1) begin
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repeat (randuint(1, 100)) @ (posedge ftdi_clk);
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ftdi_rxf_n <= 1'b0;
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repeat (randuint(1, 100)) @ (posedge ftdi_clk);
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ftdi_rxf_n <= 1'b1;
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end
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end
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initial begin
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ftdi_txe_n <= 1'b1;
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while (1) begin
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repeat (randuint(1, 100)) @ (posedge ftdi_clk);
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ftdi_txe_n <= 1'b0;
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repeat (randuint(1, 100)) @ (posedge ftdi_clk);
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ftdi_txe_n <= 1'b1;
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end
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end
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endmodule
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