From 33eb8bb9e93c0a99c4132f63bfd3f9980c27b6b4 Mon Sep 17 00:00:00 2001 From: WangXuan95 <629708558@qq.com> Date: Fri, 9 Jun 2023 20:54:43 +0800 Subject: [PATCH] change to Verilog2001 --- README.md | 726 +++++++++--------- RTL/{adc_ad7928.sv => adc_ad7928.v} | 42 +- .../{cartesian2polar.sv => cartesian2polar.v} | 24 +- RTL/foc/{clark_tr.sv => clark_tr.v} | 10 +- RTL/foc/{foc_top.sv => foc_top.v} | 55 +- RTL/foc/{hold_detect.sv => hold_detect.v} | 6 +- RTL/foc/{park_tr.sv => park_tr.v} | 12 +- RTL/foc/pi_controller.sv | 106 --- RTL/foc/pi_controller.v | 132 ++++ RTL/foc/{sincos.sv => sincos.v} | 31 +- RTL/foc/{svpwm.sv => svpwm.v} | 22 +- RTL/{fpga_top.sv => fpga_top.v} | 26 +- ...c_register_read.sv => i2c_register_read.v} | 22 +- RTL/{uart_monitor.sv => uart_monitor.v} | 68 +- ...tb_clark_park_tr.sv => tb_clark_park_tr.v} | 29 +- SIM/tb_clark_park_tr_run_iverilog.bat | 2 +- SIM/{tb_svpwm.sv => tb_svpwm.v} | 19 +- SIM/tb_svpwm_run_iverilog.bat | 2 +- figures/diagram.png | Bin 42086 -> 29140 bytes figures/sch.png | Bin 63645 -> 40243 bytes figures/tb_clark_park_tr.png | Bin 30129 -> 16010 bytes figures/tb_svpwm.png | Bin 24999 -> 11899 bytes figures/tb_svpwm_2.png | Bin 15125 -> 6741 bytes figures/wave.png | Bin 19175 -> 7419 bytes 24 files changed, 720 insertions(+), 614 deletions(-) rename RTL/{adc_ad7928.sv => adc_ad7928.v} (82%) rename RTL/foc/{cartesian2polar.sv => cartesian2polar.v} (97%) rename RTL/foc/{clark_tr.sv => clark_tr.v} (83%) rename RTL/foc/{foc_top.sv => foc_top.v} (92%) rename RTL/foc/{hold_detect.sv => hold_detect.v} (74%) rename RTL/foc/{park_tr.sv => park_tr.v} (71%) delete mode 100644 RTL/foc/pi_controller.sv create mode 100644 RTL/foc/pi_controller.v rename RTL/foc/{sincos.sv => sincos.v} (93%) rename RTL/foc/{svpwm.sv => svpwm.v} (93%) rename RTL/{fpga_top.sv => fpga_top.v} (80%) rename RTL/{i2c_register_read.sv => i2c_register_read.v} (85%) rename RTL/{uart_monitor.sv => uart_monitor.v} (72%) rename SIM/{tb_clark_park_tr.sv => tb_clark_park_tr.v} (83%) rename SIM/{tb_svpwm.sv => tb_svpwm.v} (88%) diff --git a/README.md b/README.md index 60d18de..fc78db3 100644 --- a/README.md +++ b/README.md @@ -1,329 +1,8 @@ -![语言](https://img.shields.io/badge/语言-systemverilog_(IEEE1800_2005)-CAD09D.svg) ![仿真](https://img.shields.io/badge/仿真-iverilog-green.svg) ![部署](https://img.shields.io/badge/部署-quartus-blue.svg) ![部署](https://img.shields.io/badge/部署-vivado-FF1010.svg) - -中文 | [English](#en) - -FpOC -=========================== - -基于 **FPGA** 的**磁场定向控制 (FOC)**，用于驱动**永磁同步电机 (PMSM)** 或**无刷直流电机 (BLDC)** - -**FOC控制算法**对传感器采样速率和处理器算力提出了一定的要求，使用 **FPGA** 实现的 **FOC** 可以获得更好的**实时性**，并且更方便进行**多路扩展**和**多路反馈协同**。 - -本库实现了基于**角度传感器**（也就是磁编码器）的**有感 FOC**，即一个完整的**电流环**，可以进行**扭矩控制**。借助本库，你可以进一步使用 **纯FPGA** 或 **MCU+FPGA** 的方式实现更复杂的电机应用。 - -| ![diagram](./figures/diagram.png) | -| :---: | -| **图1**：系统框图 | - -本库代码有详细的注释，如果你熟悉 Verilog 但不熟悉 FOC ，可以通过阅读代码来快速地学习 FOC （建议先阅读 FOC 原理 [6~9]）。一些用户在读代码时向本人反馈了一些疑问，我将它们整理在了 [FAQ](#FAQ) 里。 - -### 技术特点 - -* **平台无关** ：纯 RTL 编写，可以在 Altera 和 Xilinx 等各种 FPGA 上运行。 -* 支持 **3路PWM** + **1路EN** ：PWM=1 时上桥臂 MOS 导通，PWM=0 时下桥臂 MOS 导通。 EN=0 时所有的 6 个 MOS 关断。 -* 支持 **12bit 分辨率**的**角度传感器**和**相电流采样ADC**。对于>12bit的传感器，需要进行低位截断。对于<12bit的传感器，需要进行低位填充。 -* 内部使用 **16bit 有符号整数**进行计算，考虑到传感器为 12bit，所以 16bit 计算是够用的。 - -### 目录 - -- [示例程序：让电机转起来](#示例程序：让电机转起来) - - [搭建硬件](#搭建硬件) - - [建立FPGA工程](#建立FPGA工程) - - [调参](#调参) - - [用串口监视电流环](#用串口监视电流环) -- [设计代码详解](#设计代码详解) -- [RTL仿真](#RTL仿真) - - [clark_tr和park_tr子模块的仿真](#clark_tr和park_tr的仿真) - - [cartesian2polar和svpwm子模块的仿真](#cartesian2polar和svpwm的仿真) -- [FAQ](#FAQ) - - - -# 示例程序：让电机转起来 - -**图1** 是示例程序的系统框图，它调用了我实现的 FOC 电流环模块 (foc_top.sv) 来实现一个简单的行为——控制电机的电流（扭矩）按顺时针、逆时针、顺时针、逆时针地交替运行。同时，使用 UART 打印电流的**控制目标值**和**实际值**，以便观察 FOC 电流环控制的质量。 - -该示例的所有代码都在 RTL 目录内。 - - - -## 搭建硬件 - -运行本示例所需要的硬件包括： - -* **FPGA 开发板** ：需有至少 10 个 3.3V 的 IO ，用来接： - * **I2C (2*IO)** ， 用来连接 AS5600 磁编码器。 - * **SPI (4*IO)** ， 用来连接 AD7928 ADC。 - * **PWM (3*IO)** ， 用来输出 3 相 PWM 到电机驱动板。 - * **PWM_EN (1*IO)** ， 用来输出 1 路 EN (使能) 到电机驱动板（PWM_EN=低电平代表所有桥臂关断）。 - * **UART (1*IO)** ，单向(仅发送)的UART，连接计算机的串口，用于监测电流环的跟随曲线，**可不接**。 -* **PMSM** 或 **BLDC 电机**。 -* **电机驱动板**：要支持3相 PWM 输入信号（PWM=0时下桥臂导通，PWM=1时上桥臂导通），并且要内置**低侧电阻采样+放大器**对 3 相电流进行放大。 -* **获取转子角度的磁编码器**：本库直接支持的型号是 AS5600 ，需要安装在电机上。 -* **相电流采样的ADC**：本库直接支持的型号是 AD7928 ，用于采样电机驱动板放大后的 3 相电流 - * 网上似乎找不到现成卖的 AD7928 模块，所以如果你想DIY，就需要自己画 PCB。 - -如果你硬件动手能力很强，可以自己准备以上硬件。 - -不过！建议直接使用我画的一个自带 **AD7928** 的 **电机驱动板**，它的原理图如**图2**，我也提供了制造文件 [gerber_pcb_foc_shield.zip](./gerber_pcb_foc_shield.zip) ，你需要拿制造文件去打样PCB，然后按照**图2**来焊接。 - -> 注意，这个板子包括了**相电流采样的ADC**和**电机驱动板**的功能，但不包括 AS5600 磁编码器，磁编码器是需要安装在电机上的，需要你额外准备。 - -| ![sch](./figures/sch.png) | -| :---------------------------------------------------------: | -| **图2**：电机驱动板原理图，其中 AD7928 ADC 用来采样三相电流 | - -这个板子在立创EDA开源，见 [oshwhub.com/wangxuan/arduino-foc-shield](https://oshwhub.com/wangxuan/arduino-foc-shield) - -这个板子之所以被设计成 Arduino 扩展板的样子，是因为很多 FPGA 开发板也具有 Arduino 扩展板接口（比如 DE10-Nano 开发板），可以直接插上去。如果你的 FPGA 开发板没有 Arduino 扩展板接口也没关系，直接用杜邦线连接即可（建议用短的杜邦线）。 - -这里使用的电机驱动器是 **MP6540** 芯片, 我只试过驱动小功率云台电机，没试过大功率电机。 - - - -## 建立FPGA工程 - -你需要建立 FPGA 工程，把 RTL 目录（包括其子目录）里的所有 .sv 源文件加入工程，请以 fpga_top.sv 作为顶层文件。 - -### 时钟配置 - -fpga_top.sv 中有一处调用了 `altpll` 原语，用来把开发板晶振输入的 50MHz 时钟（clk\_50m 信号）变成 36.864MHz 的主时钟（clk 信号），`altpll` 原语只适用于 Altera Cyclone IV FPGA，如果你用的是其它系列的 FPGA，需要使用它们各自的 IP 核或原语（例如 Xilinx 的 clock wizard）替换它。 - -若你的开发板的晶振不是 50MHz ，你需要修改 PLL 的配置，保证主时钟 clk 信号的频率是 36.864MHz 即可。 - -实际上，主时钟 clk 的频率可以取小于 40MHz 的任意值。clk 是 FOC 系统的驱动时钟，clk 的频率会决定 SVPWM 的频率（SVPWM频率=clk 频率/2048），我选 36.864MHz 是因为可以让 SVPWM 频率 = 36864/2048 = 18kHz，只是为了凑个整数。 - -clk 的频率不能超过 40MHz 的原因是 adc_ad7928.sv 会通过二分频来产生 SPI 时钟（spi\_sck），而 ADC7928 芯片要求 SPI 时钟不能超过 20MHz。 - -### 引脚约束 - -fpga_top.sv 的 IO 连接方法如下： - -* `clk_50m` ： 连接在 FPGA 开发板的晶振上。 -* `i2c_scl`, `i2c_sda` ： 连接 AS5600 (磁编码器) 的 I2C 接口。 -* `spi_ss`, `spi_sck`, `spi_mosi`, `spi_miso` ： 连接 AD7928 (ADC芯片) 的 SPI 接口。 -* `pwm_a`, `pwm_b`, `pwm_c` ： 连接电机驱动板的 3 相 PWM 信号。 -* `pwm_en` : 连接电机驱动板的 EN (使能) 信号。 - * 如果电机驱动板没有 EN 输入，则不接。 - * 如果电机驱动板有 3 路 EN 输入，每路对应 1 相，则应该进行一对三连接。 -* `uart_tx` ： 连接 UART 转 USB 模块，插入计算机的 USB 口，用于监测电流环的跟随曲线，**可不接**。 - - - -## 调参 - -要让电机正常工作，你需要在 fpga_top.sv 中的第103行开始，根据实际情况调整 foc_top 模块的参数（Verilog parameter），包括： - -| 参数名 | 取值范围 | 说明 | -| -------------- | ------------- | ------------------------------------------------------------ | -| `INIT_CYCLES` | 1\~4294967293 | 决定了初始化步骤占多少个时钟(clk)周期。该值不能太小，因为要留足够的时间让转子回归电角度=0。在clk频率为 36.864MHz 的情况下，可以取 `INIT_CYCLES=16777216`，则初始化时间为 `16777216/36864000=0.45` 秒。 | -| `ANGLE_INV` | 0, 1 | 若角度传感器没装反（A相→B相→C相→A相 的旋转方向与角度传感器的读值的增大方向相同），则该参数应取 0。若角度传感器装反了（A相→B相→C相→A相 的旋转方向与 角度传感器的读值的增大方向相反），则该参数应取 1 。 | -| `POLE_PAIR` | 1\~255 | 电机极对数，根据电机型号决定（注意：电角度ψ = 极对数 \* 机械角度φ） | -| `MAX_AMP` | 1\~511 | SVPWM 的最大振幅，该值越小，电机能达到的最大力矩越小；但考虑到使用3相下桥臂电阻采样法来采样电流，该值也不能太大，以保证3个下桥臂有足够的持续导通时间来供ADC进行采样。在本例中，使用默认值 `9'd384` 即可。 | -| `SAMPLE_DELAY` | 0\~511 | 采样延时，考虑到3相的驱动 MOS 管从开始导通到电流稳定需要一定的时间，所以从3个下桥臂都导通，到 ADC 采样时刻之间需要一定的延时。该参数决定了该延时是多少个时钟周期，当延时结束时，该模块在 `sn_adc` 信号上产生一个高电平脉冲，指示外部 ADC “可以采样了”。在本例中，使用默认值 `9'd120` 即可。 | -| `Kp` | 0\~16777215 | PID 的 P 参数。 | -| `Ki` | 0\~16777215 | PID 的 I 参数。 | - -调好参后，综合并烧录到 FPGA 后，应该能看到电机正反交替运行。 - - - -## 用串口监视电流环 - -把 `uart_tx` 信号通过 **UART 转 USB 模块** （例如 CP2102、CH340 模块） 连接到电脑上，就可以用**串口助手**、**Putty**等软件来监测电流环的跟随效果。 - -> 注: UART 的格式是 115200,8,n,1 - -以下是串口打印的部分信息。其中第1~4列分别为：**d轴电流的实际值**，**d轴电流的目标值**，**q轴电流的实际值**，**q轴电流的目标值**。可以看到，即使目标值从+200突变到-200，实际值能跟着目标值走，说明电流环的 PID 控制是有效的。 - - - -5 0 206 200 - -16 0 202 200 - 16 0 192 200 - 15 0 201 200 - 1 0 197 200 - 17 0 -211 -200 - -6 0 -199 -200 - -10 0 -210 -200 - -3 0 -207 -200 - 0 0 -202 -200 - -15 0 -211 -200 - - -另外，你可以借用 **Arduino IDE** 的**串口绘图器**来实时显示电流跟随曲线。前往[Arduino官网](https://www.arduino.cc/en/software)下载 **Arduino IDE**，安装后打开，在“**工具→端口**”中选择正确的COM口，然后点击“**工具→串口绘图器**”，**串口绘图器**会自动接收串口并使用上述4列数据画实时曲线图。 - -**图3** 是我这里绘制出的电流跟随曲线。蓝色曲线是第1列数据（d轴电流的实际值）；红色曲线是第2列数据（d轴电流的目标值）；绿色曲线是第3列数据（q轴电流的实际值）；土黄色曲线是第4列数据（q轴电流的目标值）。可以看到实际值能跟着目标值走。 - -| ![wave](./figures/wave.png) | -| :---: | -| **图3**：电流跟随曲线 | - - - -# 设计代码详解 - -下表罗列了该工程使用的所有 **SystemVerilog** 代码文件，这些文件都在 RTL 目录下。结合**图1**就能看出每个模块的作用。 - -| 文件名 | 功能 | 备注 | -| :-- | :-- | :-- | -| fpga_top.sv | FPGA工程的顶层模块 | | -| uart_monitor.sv | UART 发送器，用于数据监测 | 不需要的话可以移除 | -| i2c_register_read.sv | I2C 读取器，用于读取 AS5600 磁编码器 | | -| adc_ad7928.sv | AD7928 读取器 | | -| foc_top.sv | FOC+SVPWM （即**图1**中的蓝色部分的顶层） | 固定功能，一般不需要改动 | -| clark_tr.sv | Clark 变换 | 固定功能，一般不需要改动 | -| park_tr.sv | Park 变换 | 固定功能，一般不需要改动 | -| sincos.sv | 正弦/余弦计算器，被 park_tr.sv 调用 | 固定功能，一般不需要改动 | -| pi_controller.sv | PI 控制器（PID没有D） | 固定功能，一般不需要改动 | -| cartesian2polar.sv | 直角坐标系转极坐标系 | 固定功能，一般不需要改动 | -| svpwm.sv | SVPWM 调制器 | 固定功能，一般不需要改动 | -| hold_detect.sv | 监测3个下桥臂都导通时，延迟一段时间后触发 sn_adc 信号，指示ADC可以开始采样 | 固定功能，一般不需要改动 | - - -| ![diagram](./figures/diagram.png) | -| :---: | -| **图1**：系统框图 | - -**图1**展示了这些模块的层次，我在设计模块层次时充分考虑了封装的合理性和代码重用 ： - -* **粉色**部分是FPGA内的即传感器控制器，是**硬件相关逻辑**，如果角度传感器和 ADC 型号变了，这部分代码需要重写。 -* **蓝色**部分是FPGA内的 FOC 的固定算法，是**硬件无关逻辑**，一般不需要修改，是本库的核心代码！ -* **黄色**部分是FPGA内的**用户自定逻辑**，用户可以修改 user behavior 来实现各种电机应用。或者修改 uart_monitor 来监测其它变量。 -* **淡橙色**部分是FPGA外部的硬件电路，也就是电机、电机驱动板、角度传感器这些东西。 - -另外，除了 fpga_top.sv 中调用的 `altpll` 原语外，该库的所有代码都使用纯 RTL 编写，可以轻易地移植到其它厂商（Xilinx、Lattice等）的 FPGA 上。 - - - -# RTL仿真 - -因为我并没有电机的 Verilog 模型，没法对整个 FOC 算法进行仿真，所以只对 FOC 中的部分模块进行了仿真。 - -仿真相关的文件都在 SIM 文件夹里，其中包括文件： - -| 文件名 | 功能 | -| --------------------------------- | ------------------------------------------------------------ | -| tb_clark_park_tr.sv | 对 clark_tr.sv （clark变换） 和 park_tr.sv （park变换）的仿真程序 | -| tb_clark_park_tr_run_iverilog.bat | 用 iverilog 运行 tb_clark_park_tr.sv 的命令脚本 | -| tb_svpwm.sv | 对 cartesian2polar.sv 和 svpwm.sv 的仿真程序 | -| tb_svpwm_run_iverilog.bat | 用 iverilog 运行 tb_svpwm.sv 的命令脚本 | - -使用 iverilog 仿真前，需要安装 iverilog ，见：[iverilog_usage](https://github.com/WangXuan95/WangXuan95/blob/main/iverilog_usage/iverilog_usage.md) - -## clark_tr和park_tr的仿真 - -我们先来运行 clark 变换和 park 变换的仿真。 - -双击 tb_clark_park_tr_run_iverilog.bat 可以直接运行仿真，运行完后会生成波形文件 dump.vcd 。请用 gtkwave 打开 dump.vcd ，导入**图4**中的这些信号，可以看到如**图4**的波形（需要你把这些信号改成模拟信号显示的形式，才能看得到**图4**这种效果：第一步，对于 Verilog 代码中声明为 signed 的信号（有符号数），需要右键该信号→Data Format→Signed Decimal。第二步，右键该信号→Data Format→Analog→Step ，即可把它变成如图的模拟信号的样子）。 - -对该**图4**波形的解读： - -- theta 是一个不断递增的角度（0→2π→0→2π→...） -- ia, ib, ic 是用 theta 生成的正弦波，相位各自相差 (2/3)*π （也就是说 ia, ib, ic）构成了三相正弦波。 -- 使用 clark 变换把 ia, ib, ic 变换成 ialpha, ibeta ，得到一对正交的正弦波（相位相差 π/2 ）。 -- 使用 park 变换把 ialpha, ibeta 变换到定子坐标系，得到定值 id 和 iq （因为实际的计算误差，所以得到的是近似的定值，而不是严格的定值）。 - -| ![tb_clark_park_tr](./figures/tb_clark_park_tr.png) | -| :-------------------------------------------------: | -| **图4**：对 clark_tr 与 park_tr 仿真的波形。 | - -## cartesian2polar和svpwm的仿真 - -现在来运行 cartesian2polar （直角坐标转极坐标系）和 svpwm 的仿真。 - -双击 tb_svpwm_run_iverilog.bat 可以直接运行仿真，运行完后会生成波形文件 dump.vcd 。请用 gtkwave 打开 dump.vcd ，可以看到如**图5**的波形。 - -注意： pwma_duty、pwmb_duty、pwmc_duty 这三个信号不在顶层，你要在 svpwm 这个模块内才能找到这三个信号。 - -对**图5**波形的解读： - -- theta 是一个不断递增的角度（0→2π→0→2π→...） -- x 和 y 是用 theta 生成的正交的正弦波（或者说，y是正弦波，x是余弦波） -- 把 (x,y) 视作直角坐标值，然后 cartesian2polar 把它转换成极坐标系 (ρ, φ) ，也即 (rho, phi) -- 把 (rho, phi) 输给 svpwm ，产生了 pwma_duty、pwmb_duty、pwmc_duty 这三个马鞍波。如果你熟悉七段式 SVPWM 的原理，就应该知道为什么是马鞍波，这里不做赘述。 -- pwma_duty、pwmb_duty、pwmc_duty 分别决定了 pwm_a, pwm_b, pwm_c 的占空比（duty这个单词就是占空比的意思）。 - -| ![tb_svpwm](./figures/tb_svpwm.png) | -| :-----------------------------------------------: | -| **图5**：对 cartesian2polar 与 svpwm 仿真的波形。 | - -放大波形，可以看到确实是 duty 值越大，对应的 pwm 信号的占空比就越大，如**图6**。 - -| ![tb_svpwm_2](./figures/tb_svpwm_2.png) | -| :-------------------------------------: | -| **图6**：图5的放大。 | - - - -# FAQ - -一些用户在读代码时向本人反馈了一些疑问，我将它们整理如下。 - -### 关于 PCB 设计 - -* **问**： **相电流低压侧3电阻采样需要运放放大电流信号才能作为AD输入，但你[开源的PCB]((https://oshwhub.com/wangxuan/arduino-foc-shield))似乎找不到运放放大？** -* **答**： 我[开源的PCB](https://oshwhub.com/wangxuan/arduino-foc-shield)使用了一体化的三相无刷电机驱动芯片MP6540（U1），3相电流采样电阻和放大器是集成在里面的。请注意MP6540的 SOA, SOB, SOC 三个引脚，它们就是三相电流放大后的电压输出。 - - -### 关于 FOC 中的数学计算 - -* **问**： **三电阻采样后的电流重构的那部分代码如何理解？为什么 ia = ADCb + ADCc - 2*ADCa ？** -* **答**： 我们知道电机的相电流 ia, ib, ic 是双极性的（即有正有负的，分别代表流出电机和流入电机），但我们常用的ADC往往都是单极性的（即只能采样正电压）。那么，相电流采样-放大电路就必须考虑双极性到单极性的转换问题，工程上用的方法往往都是反向放大加偏置（包括MP6540内置采样-放大电路也是这种方案），它输出给ADC的电压遵循公式： - ADCa = -R × ia + Voff - ADCb = -R × ib + Voff - ADCc = -R × ic + Voff - 其中 R 是放大系数（R>0，也叫跨阻放大系数，因为 R 的量纲和电阻一样），因为反向放大所以加了负号。Voff 是偏置电压，以此保证 ADCa, ADCb, ADCc 是单极性的。另外又有基尔霍夫电流定律（KCL）： - ia + ib + ic = 0 - 联立以上公式，推出： - 3 * Voff = ADCa + ADCb + ADCc - 令 R = 1/(3*k) ，于是： - ia = (Voff - ADCa) / R - = k × (3 * Voff - 3 × ADCa) - = k × (ADCa + ADCb + ADCc - 3 × ADCa) - = k × (ADCb + ADCc - 2×ADCa) - 于是就有了你问的 ia = ADCb + ADCc - 2×ADCa 。 你肯定会疑惑，系数 k 哪儿去了？这个并不在乎，因为整个FOC都是线性系统，通过调整PID参数，能跑就行，系数只在理论分析时有用。 - -* **问** : **你的程序里是不是都没有在乎系数K，包括clark变换中得到的Iα和Iβ和ia、ib、ic也并没有满足严格的公式关系，程序中得到的Iα和Iβ是理论值的2倍。这是不是也可以用调整PID参数的思想来解释？** -* **答**： 是的，我很多地方的代码也与理论公式的系数不同，比如 clark 变换公式本来是： - Iα = Ia - Ib/2 - Ic/2 - Iβ = √3/2 * (Ib - Ic) - 我多乘了个2： - Iα = 2 * Ia - Ib - Ic - Iβ = √3 * (Ib - Ic) - 这是出于避免整数计算的截断导致的数据位丢失，比如 Ib/2 就会让 Ib 的最低 bit 丢失。不过实际上这种小误差基本不会影响控制质量。这种系数问题可以通过 PID 调参来消除。 - -* **问**: **你的代码中的 cartesian2polar.sv 是把电压矢量从转子直角坐标系 (Vd, Vq) 变换到转子极坐标系 (Vrρ, Vrθ)，目的是什么？** -* **答**： 书上一般会说 SVPWM 模块输入的是定子直角坐标系下的电压，但我实现的 SVPWM 输入的是定子极坐标系下的电压，两种方法在数学上是等价的。而且 SVPWM 在 FPGA 里用查找表(ROM)实现，因此两种方法对电路复杂度影响不大。另外，输入极坐标系的 SVPWM 还带来 2 个好处和 1 个代价，好处 1 是更方便在开发过程中让电机开环地转起来（只需要让角度递增即可）。好处 2 是极坐标系下的 park 变换更简单，只需要用电压在转子坐标系中的角度减去电角度就能得到电压在定子坐标系中的角度。 代价是需要在 PID 的后面、park 变换的前面实现一个直角坐标系转极坐标系的运算，即 cartesian2polar.sv - -### 关于 ADC 采样时机 - -* **问**： **AD7928只有一个T/H(采样保持器)，也就意味着这个AD一次只能保持一个通道的数据，也就是说当通道1 打开的时候采集A相的电流，然后采集完再打开通道2采集B相的电流，那么这并不是一个同步采集的过程，如何实现AD采样三相电流的同步输出？** -* **答**： 在电流采样问题上，我们与大多数 FOC 方案相同，因为 MP6540 里的采样电阻在下桥臂，所以规定 SVPWM 在每个控制周期（约 55us，对应频率18kHz）内至少有一段时间里 3 相都是下通上闭，称为采样窗口。FOC的基础振幅（也就是 foc_top.sv 里的 MAX_AMP 参数）越大，采样窗口越短。当 MAX_AMP=9'd511 (最大值) 时，采样窗口长度就是 0 了。而默认的 MAX_AMP=9'd384 大概会让采样窗口长度为十几us。 -AD7928 只有一个T/H，所以采样窗口内要做 3 次采样，这个过程是 hold_detect.sv 和 adc_ad7928.sv 共同控制的，hold_detect.sv负责在采样窗口开始时延迟一段时间（来让电流趋于稳定）后发出 sn_adc 信号脉冲，来告诉 adc_ad7928.sv 可以开始工作了（可以通过 foc_top.sv 里的 SAMPLE_DELAY 来调整该延迟）。然后 adc_ad7928.sv 内部就会自动串行地完成 3 个通道的采样，最后再同步提交3个采样结果（提交的同时产生 o_en_adc 信号脉冲）。注意adc_ad7928.sv是一个通用的 AD7928 控制器，每收到一个 i_sn_adc 信号脉冲，就进行一系列串行采样。其中采样多少次，每次采样哪一个通道，都可以通过 adc_ad7928.sv 里的 parameter 来配置。所有通道采样结束后，产生o_en_adc信号脉冲，同时同步提交所有通道的结果。 -我把 foc_top.sv 用来连接 ADC控制器的接口（也就是sn_adc, en_adc, adc_a, adc_b, adc_c 这几个信号）设计成同步读入3通道数据，是出于通用性、简约性和可移植性的原则考虑，因为这样的同步读入接口是 ADC 的一种高度抽象，最容易让人理解其时序（即，sn_adc脉冲命令ADC控制器开始工作。en_adc指示ADC读取器结束工作，同时 adc_a, adc_b, adc_c 上产生结果）。如果用户用了其它 ADC 型号，只需按照这个时序的抽象来具象地编写 ADC 控制器即可，而 foc_top.sv 并不关心拟用的是1个串行的ADC还是3个并行的ADC，反正你都要给我同步提交。当然，用户必须自己算好 hold_detect.sv 的延时 + ADC 采样三个通道（也即 sn_adc 脉冲和 en_adc 脉冲的时间差） 是小于采样窗口的长度的。 - - -* **问**： **进行串行采样的时候不会出现这样的问题：第一个时钟周期采到的是A相的电流，第2个时钟周期采的是B相，第3个时钟周期采到的是C相，而我们知道相电流是正弦变化的，这三个时钟周期采的A B C 三相电流并不是同一时刻的相电流，因此这将产生误差，而时钟周期是很短的，是不是产生的误差几乎可以忽略不计呢？** -* **答**： 首先指正一个不准确的地方， AD7928 的接口是 SPI （一种串行接口），其采样是多个时钟周期（而不是一个时钟周期）内完成的。因此三相的采样间隔是几十个时钟周期（具体数字我忘了，你可以仿真确定一下）。 -虽然不同步，但3相的采样毕竟都是在同一个控制周期的采样窗口（几微秒）内。而相电流的变化通常以控制周期（即几十微秒）为尺度变化，例如 3000r/min（50r/s）的转子，若极对数=7，其相电流是350Hz（周期28ms）的正弦波，其变化在几微秒内是可以忽略的。 - - - -# 参考资料 - -* [1] [Sensorless FOC for PMSM](https://www.microchip.com/stellent/groups/SiteComm_sg/documents/Training_Tutorials/en532365.pdf), MicroChip. -* [2] [Current sensing in BLDC motor application](https://www.st.com/resource/en/application_note/dm00666970-current-sensing-in-bldc-motor-application-stmicroelectronics.pdf), ST. -* [3] [Center-Aligned SVPWM Realization](https://www.ti.com/lit/an/sprabs6/sprabs6.pdf), TI -* [4] [MP6540, 3-phase, brushless DC motor drivers](https://www.monolithicpower.com/en/mp6540-mp6540a.html), MPS. -* [5] [AD7928, 8-Channel, 1 MSPS, 12-Bit ADC](https://www.analog.com/en/products/ad7928.html), Analog Devices. -* [6] [深入浅出讲解FOC算法与SVPWM技术](https://zhuanlan.zhihu.com/p/147659820), 稚晖 - 知乎 -* [7] [如何从零开始写一套自己的FOC矢量控制程序](https://zhuanlan.zhihu.com/p/103758450?utm_source=qzone), 上官致远 - 知乎 -* [8] [STM32电动机控制应用系列讲座](https://www.bilibili.com/video/BV1vT4y1j7kc) -* [9] [BLDC电机基础](https://www.bilibili.com/video/BV1TW411d7k6) - - +![语言](https://img.shields.io/badge/语言-verilog_(IEEE1364_2001)-9A90FD.svg) ![仿真](https://img.shields.io/badge/仿真-iverilog-green.svg) ![部署](https://img.shields.io/badge/部署-quartus-blue.svg) ![部署](https://img.shields.io/badge/部署-vivado-FF1010.svg) +[English](#en) | [中文](#cn) +　 FpOC =========================== @@ -342,7 +21,7 @@ The code in this repository has detailed comments (in Chinese). If you are famil ### Technical features -* Platform independent：Written in pure SystemVerilog, able to run on various FPGAs such as Altera and Xilinx. +* Platform independent：Written in pure Verilog, able to run on various FPGAs such as Altera and Xilinx. * Support **3 channels of PWM** + **1 channel of EN**: when PWM=1, the upper MOSFET turns on, and when PWM=0, the lower MOSFET turns on. When EN=0, all 6 MOSFET are turned off. * Supports **angle sensor** and **phase current sampling ADC** with **12bit resolution**. For sensors >12bit, low-order truncation is required. For sensors <12bit, low-bit stuffing is required. @@ -360,7 +39,7 @@ The code in this repository has detailed comments (in Chinese). If you are famil - [simulate clark_tr and park_tr](#simulate clark_tr and park_tr) - [simulate cartesian2polar and svpwm](#simulate cartesian2polar and svpwm) - +　 # Demo project: let your motor spin @@ -402,21 +81,21 @@ The motor driver used here is the **MP6540** chip, I have only tried to drive th ## Create FPGA project -You need to create an FPGA project and add all the .sv source files in the [RTL](./RTL) folder (including its subdirectories) to the project. Please use fpga_top.sv as the top-level file. +You need to create an FPGA project and add all the .v source files in the [RTL](./RTL) folder (including its subdirectories) to the project. Please use fpga_top.v as the top-level file. ### clock config -There is a call to the `altpll` primitive in fpga_top.sv, which convert the 50MHz clock (clk\_50m signal) input by the crystal oscillator into a 36.864MHz main clock (clk signal). The `altpll` primitive is only applicable in Altera Cyclone IV FPGA, if you are using other series of FPGAs, you need to replace it with their IP cores or primitives (e.g. Xilinx's clock wizard). +There is a call to the `altpll` primitive in fpga_top.v, which convert the 50MHz clock (clk\_50m signal) input by the crystal oscillator into a 36.864MHz main clock (clk signal). The `altpll` primitive is only applicable in Altera Cyclone IV FPGA, if you are using other series of FPGAs, you need to replace it with their IP cores or primitives (e.g. Xilinx's clock wizard). If the crystal oscillator of your development board is not 50MHz, you need to modify the PLL's configuration to ensure that the frequency of the main clock is 36.864MHz. In fact, the frequency of the main clock can take any value less than 40MHz. main clock is to drive the FOC system, its frequency will determine the frequency of SVPWM (SVPWM frequency = clk frequency/2048), I choose 36.864MHz because it can make SVPWM frequency = 36864/2048 = 18kHz. -The reason why the frequency of main clock cannot exceed 40MHz is that adc_ad7928.sv will generate the SPI clock (spi\_sck signal) by dividing the frequency by two, and the ADC7928 chip requires that the SPI clock cannot exceed 20MHz. +The reason why the frequency of main clock cannot exceed 40MHz is that adc_ad7928.v will generate the SPI clock (spi\_sck signal) by dividing the frequency by two, and the ADC7928 chip requires that the SPI clock cannot exceed 20MHz. ### pin constraints -The IO connection of fpga_top.sv is as follows: +The IO connection of fpga_top.v is as follows: * `clk_50m` : connect to the crystal oscillator on FPGA board. * `i2c_scl`, `i2c_sda` : connect to AS5600's I2C. @@ -429,7 +108,7 @@ The IO connection of fpga_top.sv is as follows: ## parameter tuning -To make the motor work normally, you need to tune the Verilog parameters of foc_top module which starts from 103 line in fpga_top.sv, including: +To make the motor work normally, you need to tune the Verilog parameters of foc_top module which starts from 103 line in fpga_top.v, including: | Parameter | Value Range | Illustration | | -------------- | ------------- | ------------------------------------------------------------ | @@ -438,8 +117,14 @@ To make the motor work normally, you need to tune the Verilog parameters of foc_ | `POLE_PAIR` | 1\~255 | The number of pole pairs of the motor, which is determined according to the motor model (note: electrical angle ψ = number of pole pairs \* mechanical angle φ). | | `MAX_AMP` | 1\~511 | The maximum duty of SVPWM, the smaller the value, the smaller torque the motor can achieve. But considering that we use the lower arm resistance sampling method, the value should not be too large to ensure that the lower arms have sufficient time for ADC sampling. In this example, the default value of `9'd384` is sufficient. | | `SAMPLE_DELAY` | 0\~511 | Sampling delay, considering that the 3-phase drive MOSFET needs a certain time from the start of conduction to the current stabilization, so a certain delay is required from the conduction of the three lower arms to the ADC sampling time. This parameter determines how many clock cycles this delay is, and when the delay is over, the module generates a high-level pulse on the `sn_adc` signal, indicating that the external ADC is "ready to sample". In this example, the default value of `9'd120` is sufficient. | -| `Kp` | 0\~16777215 | Kp for PID. | -| `Ki` | 0\~16777215 | Ki for PID. | + +In addition, foc_top module has two input ports `Kp` and `Ki` , they are parameters for PID controller. They will affect the quality of control. They can be adjusted at runtime, but you can also input fixed constants for them. + +```verilog +// ports of foc_top.v +input wire [30:0] Kp, +input wire [30:0] Ki, +``` After tuning the parameters, you can compile and program to the FPGA. You should be able to see the motor spining clockwize and anticlockwize alternately. @@ -473,24 +158,26 @@ In addition, you can use the **serial plotter** of **Arduino IDE** to display th | :----------------------------------------------------------: | | **Figure3** : current following curve printed by the "Serial Port Plotter" in Arduino IDE. | +　 + # Design code -The following table lists all the **SystemVerilog** code files in this project, which are in the [RTL](./RTL) folder. Combined with **Figure1**, you can see the role of each module. +The following table lists all the **Verilog** code files in this project, which are in the [RTL](./RTL) folder. Combined with **Figure1**, you can see the role of each module. | File Name | Function | 备注 | | :------------------- | :----------------------------------------------------------- | :-------------------------------------------------- | -| fpga_top.sv | FPGA project's top module | | -| uart_monitor.sv | UART sender. | Can be removed if not used. | -| i2c_register_read.sv | Read AS5600 magnetic encoder. | | -| adc_ad7928.sv | Read AD7928 ADC. | | -| foc_top.sv | FOC+SVPWM, that is, the blue part in **Figure1**. | Fixed function, generally do not need to be changed | -| clark_tr.sv | Clark transform. | Fixed function, generally do not need to be changed | -| park_tr.sv | Park transform. | Fixed function, generally do not need to be changed | -| sincos.sv | Sine/Cosine calculator, called by park_tr.sv | Fixed function, generally do not need to be changed | -| pi_controller.sv | PI controller (PID without D). | Fixed function, generally do not need to be changed | -| cartesian2polar.sv | Cartesian coordinate system to polar coordinate system. | Fixed function, generally do not need to be changed | -| svpwm.sv | SVPWM 调制器 | Fixed function, generally do not need to be changed | -| hold_detect.sv | When three lower bridge arms are all turned on, pulse the sn_adc signal after a delay, indicating that the ADC can start sampling. | Fixed function, generally do not need to be changed | +| fpga_top.v | FPGA project's top module | | +| uart_monitor.v | UART sender. | Can be removed if not used. | +| i2c_register_read.v | Read AS5600 magnetic encoder. | | +| adc_ad7928.v | Read AD7928 ADC. | | +| foc_top.v | FOC+SVPWM, that is, the blue part in **Figure1**. | Fixed function, generally do not need to be changed | +| clark_tr.v | Clark transform. | Fixed function, generally do not need to be changed | +| park_tr.v | Park transform. | Fixed function, generally do not need to be changed | +| sincos.v | Sine/Cosine calculator, called by park_tr.v | Fixed function, generally do not need to be changed | +| pi_controller.v | PI controller (PID without D). | Fixed function, generally do not need to be changed | +| cartesian2polar.v | Cartesian coordinate system to polar coordinate system. | Fixed function, generally do not need to be changed | +| svpwm.v | SVPWM 调制器 | Fixed function, generally do not need to be changed | +| hold_detect.v | When three lower bridge arms are all turned on, pulse the sn_adc signal after a delay, indicating that the ADC can start sampling. | Fixed function, generally do not need to be changed | | ![diagram](./figures/diagram.png) | @@ -504,7 +191,9 @@ The following table lists all the **SystemVerilog** code files in this project, * The **yellow** part is the **user-defined logic** in the FPGA, the user can modify the user behavior to realize various motor applications. Or modify `uart_monitor` to monitor other variables. * The **orange** part is the hardware circuit outside the FPGA, that is, the motor, the motor driver board, and the angle sensor. -In addition, except for the `altpll` primitives in fpga_top.sv, all code in this library is written in pure RTL and can be easily ported to FPGAs from other vendors (Xilinx, Lattice, etc.). +In addition, except for the `altpll` primitives in fpga_top.v, all code in this library is written in pure RTL and can be easily ported to FPGAs from other vendors (Xilinx, Lattice, etc.). + +　 # RTL simulation @@ -514,10 +203,10 @@ The simulation related files are all in the [SIM](./SIM) folder, including the f | File Name | Function | | --------------------------------- | ------------------------------------------------------------ | -| tb_clark_park_tr.sv | Testbench for clark_tr.sv (clark transform) and park_tr.sv (park transform). | -| tb_clark_park_tr_run_iverilog.bat | Command script to run tb_clark_park_tr.sv with iverilog. | -| tb_svpwm.sv | Testbench for cartesian2polar.sv and svpwm.sv. | -| tb_svpwm_run_iverilog.bat | Command script to run tb_svpwm.sv with iverilog. | +| tb_clark_park_tr.v | Testbench for clark_tr.v (clark transform) and park_tr.v (park transform). | +| tb_clark_park_tr_run_iverilog.bat | Command script to run tb_clark_park_tr.v with iverilog. | +| tb_svpwm.v | Testbench for cartesian2polar.v and svpwm.v. | +| tb_svpwm_run_iverilog.bat | Command script to run tb_svpwm.v with iverilog. | Before using iverilog simulation, you need to install iverilog , see: [iverilog_usage](https://github.com/WangXuan95/WangXuan95/blob/main/iverilog_usage/iverilog_usage.md) @@ -565,3 +254,338 @@ Interpretation of **Figure5** waveform: | :-------------------------------------: | | **Figure6** : Zoom in Figure5. | +　 + +　 + +　 + +　 + +　 + +FpOC +=========================== + +基于 **FPGA** 的**磁场定向控制 (FOC)**，用于驱动**永磁同步电机 (PMSM)** 或**无刷直流电机 (BLDC)** + +**FOC控制算法**对传感器采样速率和处理器算力提出了一定的要求，使用 **FPGA** 实现的 **FOC** 可以获得更好的**实时性**，并且更方便进行**多路扩展**和**多路反馈协同**。 + +本库实现了基于**角度传感器**（也就是磁编码器）的**有感 FOC**，即一个完整的**电流环**，可以进行**扭矩控制**。借助本库，你可以进一步使用 **纯FPGA** 或 **MCU+FPGA** 的方式实现更复杂的电机应用。 + +| ![diagram](./figures/diagram.png) | +| :---: | +| **图1**：系统框图 | + +本库代码有详细的注释，如果你熟悉 Verilog 但不熟悉 FOC ，可以通过阅读代码来快速地学习 FOC （建议先阅读 FOC 原理 [6~9]）。一些用户在读代码时向本人反馈了一些疑问，我将它们整理在了 [FAQ](#FAQ) 里。 + +### 技术特点 + +* **平台无关** ：纯 RTL 编写，可以在 Altera 和 Xilinx 等各种 FPGA 上运行。 +* 支持 **3路PWM** + **1路EN** ：PWM=1 时上桥臂 MOS 导通，PWM=0 时下桥臂 MOS 导通。 EN=0 时所有的 6 个 MOS 关断。 +* 支持 **12bit 分辨率**的**角度传感器**和**相电流采样ADC**。对于>12bit的传感器，需要进行低位截断。对于<12bit的传感器，需要进行低位填充。 +* 内部使用 **16bit 有符号整数**进行计算，考虑到传感器为 12bit，所以 16bit 计算是够用的。 + +### 目录 + +- [示例程序：让电机转起来](#示例程序：让电机转起来) + - [搭建硬件](#搭建硬件) + - [建立FPGA工程](#建立FPGA工程) + - [调参](#调参) + - [用串口监视电流环](#用串口监视电流环) +- [设计代码详解](#设计代码详解) +- [RTL仿真](#RTL仿真) + - [clark_tr和park_tr子模块的仿真](#clark_tr和park_tr的仿真) + - [cartesian2polar和svpwm子模块的仿真](#cartesian2polar和svpwm的仿真) +- [FAQ](#FAQ) + +　 + +# 示例程序：让电机转起来 + +**图1** 是示例程序的系统框图，它调用了我实现的 FOC 电流环模块 (foc_top.v) 来实现一个简单的行为——控制电机的电流（扭矩）按顺时针、逆时针、顺时针、逆时针地交替运行。同时，使用 UART 打印电流的**控制目标值**和**实际值**，以便观察 FOC 电流环控制的质量。 + +该示例的所有代码都在 RTL 目录内。 + + + +## 搭建硬件 + +运行本示例所需要的硬件包括： + +* **FPGA 开发板** ：需有至少 10 个 3.3V 的 IO ，用来接： + * **I2C (2*IO)** ， 用来连接 AS5600 磁编码器。 + * **SPI (4*IO)** ， 用来连接 AD7928 ADC。 + * **PWM (3*IO)** ， 用来输出 3 相 PWM 到电机驱动板。 + * **PWM_EN (1*IO)** ， 用来输出 1 路 EN (使能) 到电机驱动板（PWM_EN=低电平代表所有桥臂关断）。 + * **UART (1*IO)** ，单向(仅发送)的UART，连接计算机的串口，用于监测电流环的跟随曲线，**可不接**。 +* **PMSM** 或 **BLDC 电机**。 +* **电机驱动板**：要支持3相 PWM 输入信号（PWM=0时下桥臂导通，PWM=1时上桥臂导通），并且要内置**低侧电阻采样+放大器**对 3 相电流进行放大。 +* **获取转子角度的磁编码器**：本库直接支持的型号是 AS5600 ，需要安装在电机上。 +* **相电流采样的ADC**：本库直接支持的型号是 AD7928 ，用于采样电机驱动板放大后的 3 相电流 + * 网上似乎找不到现成卖的 AD7928 模块，所以如果你想DIY，就需要自己画 PCB。 + +如果你硬件动手能力很强，可以自己准备以上硬件。 + +不过！建议直接使用我画的一个自带 **AD7928** 的 **电机驱动板**，它的原理图如**图2**，我也提供了制造文件 [gerber_pcb_foc_shield.zip](./gerber_pcb_foc_shield.zip) ，你需要拿制造文件去打样PCB，然后按照**图2**来焊接。 + +> 注意，这个板子包括了**相电流采样的ADC**和**电机驱动板**的功能，但不包括 AS5600 磁编码器，磁编码器是需要安装在电机上的，需要你额外准备。 + +| ![sch](./figures/sch.png) | +| :---------------------------------------------------------: | +| **图2**：电机驱动板原理图，其中 AD7928 ADC 用来采样三相电流 | + +这个板子在立创EDA开源，见 [oshwhub.com/wangxuan/arduino-foc-shield](https://oshwhub.com/wangxuan/arduino-foc-shield) + +这个板子之所以被设计成 Arduino 扩展板的样子，是因为很多 FPGA 开发板也具有 Arduino 扩展板接口（比如 DE10-Nano 开发板），可以直接插上去。如果你的 FPGA 开发板没有 Arduino 扩展板接口也没关系，直接用杜邦线连接即可（建议用短的杜邦线）。 + +这里使用的电机驱动器是 **MP6540** 芯片, 我只试过驱动小功率云台电机，没试过大功率电机。 + + + +## 建立FPGA工程 + +你需要建立 FPGA 工程，把 RTL 目录（包括其子目录）里的所有 .v 源文件加入工程，请以 fpga_top.v 作为顶层文件。 + +### 时钟配置 + +fpga_top.v 中有一处调用了 `altpll` 原语，用来把开发板晶振输入的 50MHz 时钟（clk\_50m 信号）变成 36.864MHz 的主时钟（clk 信号），`altpll` 原语只适用于 Altera Cyclone IV FPGA，如果你用的是其它系列的 FPGA，需要使用它们各自的 IP 核或原语（例如 Xilinx 的 clock wizard）替换它。 + +若你的开发板的晶振不是 50MHz ，你需要修改 PLL 的配置，保证主时钟 clk 信号的频率是 36.864MHz 即可。 + +实际上，主时钟 clk 的频率可以取小于 40MHz 的任意值。clk 是 FOC 系统的驱动时钟，clk 的频率会决定 SVPWM 的频率（SVPWM频率=clk 频率/2048），我选 36.864MHz 是因为可以让 SVPWM 频率 = 36864/2048 = 18kHz，只是为了凑个整数。 + +clk 的频率不能超过 40MHz 的原因是 adc_ad7928.v 会通过二分频来产生 SPI 时钟（spi\_sck），而 ADC7928 芯片要求 SPI 时钟不能超过 20MHz。 + +### 引脚约束 + +fpga_top.v 的 IO 连接方法如下： + +* `clk_50m` ： 连接在 FPGA 开发板的晶振上。 +* `i2c_scl`, `i2c_sda` ： 连接 AS5600 (磁编码器) 的 I2C 接口。 +* `spi_ss`, `spi_sck`, `spi_mosi`, `spi_miso` ： 连接 AD7928 (ADC芯片) 的 SPI 接口。 +* `pwm_a`, `pwm_b`, `pwm_c` ： 连接电机驱动板的 3 相 PWM 信号。 +* `pwm_en` : 连接电机驱动板的 EN (使能) 信号。 + * 如果电机驱动板没有 EN 输入，则不接。 + * 如果电机驱动板有 3 路 EN 输入，每路对应 1 相，则应该进行一对三连接。 +* `uart_tx` ： 连接 UART 转 USB 模块，插入计算机的 USB 口，用于监测电流环的跟随曲线，**可不接**。 + + + +## 调参 + +要让电机正常工作，你需要在 fpga_top.v 中的第103行开始，根据实际情况调整 foc_top 模块的参数（Verilog parameter），包括： + +| 参数名 | 取值范围 | 说明 | +| -------------- | ------------- | ------------------------------------------------------------ | +| `INIT_CYCLES` | 1\~4294967293 | 决定了初始化步骤占多少个时钟(clk)周期。该值不能太小，因为要留足够的时间让转子回归电角度=0。在clk频率为 36.864MHz 的情况下，可以取 `INIT_CYCLES=16777216`，则初始化时间为 `16777216/36864000=0.45` 秒。 | +| `ANGLE_INV` | 0, 1 | 若角度传感器没装反（A相→B相→C相→A相 的旋转方向与角度传感器的读值的增大方向相同），则该参数应取 0。若角度传感器装反了（A相→B相→C相→A相 的旋转方向与 角度传感器的读值的增大方向相反），则该参数应取 1 。 | +| `POLE_PAIR` | 1\~255 | 电机极对数，根据电机型号决定（注意：电角度ψ = 极对数 \* 机械角度φ） | +| `MAX_AMP` | 1\~511 | SVPWM 的最大振幅，该值越小，电机能达到的最大力矩越小；但考虑到使用3相下桥臂电阻采样法来采样电流，该值也不能太大，以保证3个下桥臂有足够的持续导通时间来供ADC进行采样。在本例中，使用默认值 `9'd384` 即可。 | +| `SAMPLE_DELAY` | 0\~511 | 采样延时，考虑到3相的驱动 MOS 管从开始导通到电流稳定需要一定的时间，所以从3个下桥臂都导通，到 ADC 采样时刻之间需要一定的延时。该参数决定了该延时是多少个时钟周期，当延时结束时，该模块在 `sn_adc` 信号上产生一个高电平脉冲，指示外部 ADC “可以采样了”。在本例中，使用默认值 `9'd120` 即可。 | + +另外，foc_top 模块具有输入端口 `Kp` 和 `Ki` ，它们是 PID 控制器的参数，会影响控制的质量。它们可以在运行时调整，不过你也可以给他们输入固定的常数。 + +```verilog +// ports of foc_top.v +input wire [30:0] Kp, +input wire [30:0] Ki, +``` + +调好参后，综合并烧录到 FPGA 后，应该能看到电机正反交替运行。 + +## 用串口监视电流环 + +把 `uart_tx` 信号通过 **UART 转 USB 模块** （例如 CP2102、CH340 模块） 连接到电脑上，就可以用**串口助手**、**Putty**等软件来监测电流环的跟随效果。 + +> 注: UART 的格式是 115200,8,n,1 + +以下是串口打印的部分信息。其中第1~4列分别为：**d轴电流的实际值**，**d轴电流的目标值**，**q轴电流的实际值**，**q轴电流的目标值**。可以看到，即使目标值从+200突变到-200，实际值能跟着目标值走，说明电流环的 PID 控制是有效的。 + + + -5 0 206 200 + -16 0 202 200 + 16 0 192 200 + 15 0 201 200 + 1 0 197 200 + 17 0 -211 -200 + -6 0 -199 -200 + -10 0 -210 -200 + -3 0 -207 -200 + 0 0 -202 -200 + -15 0 -211 -200 + + +另外，你可以借用 **Arduino IDE** 的**串口绘图器**来实时显示电流跟随曲线。前往[Arduino官网](https://www.arduino.cc/en/software)下载 **Arduino IDE**，安装后打开，在“**工具→端口**”中选择正确的COM口，然后点击“**工具→串口绘图器**”，**串口绘图器**会自动接收串口并使用上述4列数据画实时曲线图。 + +**图3** 是我这里绘制出的电流跟随曲线。蓝色曲线是第1列数据（d轴电流的实际值）；红色曲线是第2列数据（d轴电流的目标值）；绿色曲线是第3列数据（q轴电流的实际值）；土黄色曲线是第4列数据（q轴电流的目标值）。可以看到实际值能跟着目标值走。 + +| ![wave](./figures/wave.png) | +| :---: | +| **图3**：电流跟随曲线 | + +　 + +# 设计代码详解 + +下表罗列了该工程使用的所有 **Verilog** 代码文件，这些文件都在 RTL 目录下。结合**图1**就能看出每个模块的作用。 + +| 文件名 | 功能 | 备注 | +| :-- | :-- | :-- | +| fpga_top.v | FPGA工程的顶层模块 | | +| uart_monitor.v | UART 发送器，用于数据监测 | 不需要的话可以移除 | +| i2c_register_read.v | I2C 读取器，用于读取 AS5600 磁编码器 | | +| adc_ad7928.v | AD7928 读取器 | | +| foc_top.v | FOC+SVPWM （即**图1**中的蓝色部分的顶层） | 固定功能，一般不需要改动 | +| clark_tr.v | Clark 变换 | 固定功能，一般不需要改动 | +| park_tr.v | Park 变换 | 固定功能，一般不需要改动 | +| sincos.v | 正弦/余弦计算器，被 park_tr.v 调用 | 固定功能，一般不需要改动 | +| pi_controller.v | PI 控制器（PID没有D） | 固定功能，一般不需要改动 | +| cartesian2polar.v | 直角坐标系转极坐标系 | 固定功能，一般不需要改动 | +| svpwm.v | SVPWM 调制器 | 固定功能，一般不需要改动 | +| hold_detect.v | 监测3个下桥臂都导通时，延迟一段时间后触发 sn_adc 信号，指示ADC可以开始采样 | 固定功能，一般不需要改动 | + + +| ![diagram](./figures/diagram.png) | +| :---: | +| **图1**：系统框图 | + +**图1**展示了这些模块的层次，我在设计模块层次时充分考虑了封装的合理性和代码重用 ： + +* **粉色**部分是FPGA内的即传感器控制器，是**硬件相关逻辑**，如果角度传感器和 ADC 型号变了，这部分代码需要重写。 +* **蓝色**部分是FPGA内的 FOC 的固定算法，是**硬件无关逻辑**，一般不需要修改，是本库的核心代码！ +* **黄色**部分是FPGA内的**用户自定逻辑**，用户可以修改 user behavior 来实现各种电机应用。或者修改 uart_monitor 来监测其它变量。 +* **淡橙色**部分是FPGA外部的硬件电路，也就是电机、电机驱动板、角度传感器这些东西。 + +另外，除了 fpga_top.v 中调用的 `altpll` 原语外，该库的所有代码都使用纯 RTL 编写，可以轻易地移植到其它厂商（Xilinx、Lattice等）的 FPGA 上。 + +　 + +# RTL仿真 + +因为我并没有电机的 Verilog 模型，没法对整个 FOC 算法进行仿真，所以只对 FOC 中的部分模块进行了仿真。 + +仿真相关的文件都在 SIM 文件夹里，其中包括文件： + +| 文件名 | 功能 | +| --------------------------------- | ------------------------------------------------------------ | +| tb_clark_park_tr.v | 对 clark_tr.v （clark变换） 和 park_tr.v （park变换）的仿真程序 | +| tb_clark_park_tr_run_iverilog.bat | 用 iverilog 运行 tb_clark_park_tr.v 的命令脚本 | +| tb_svpwm.v | 对 cartesian2polar.v 和 svpwm.v 的仿真程序 | +| tb_svpwm_run_iverilog.bat | 用 iverilog 运行 tb_svpwm.v 的命令脚本 | + +使用 iverilog 仿真前，需要安装 iverilog ，见：[iverilog_usage](https://github.com/WangXuan95/WangXuan95/blob/main/iverilog_usage/iverilog_usage.md) + +## clark_tr和park_tr的仿真 + +我们先来运行 clark 变换和 park 变换的仿真。 + +双击 tb_clark_park_tr_run_iverilog.bat 可以直接运行仿真，运行完后会生成波形文件 dump.vcd 。请用 gtkwave 打开 dump.vcd ，导入**图4**中的这些信号，可以看到如**图4**的波形（需要你把这些信号改成模拟信号显示的形式，才能看得到**图4**这种效果：第一步，对于 Verilog 代码中声明为 signed 的信号（有符号数），需要右键该信号→Data Format→Signed Decimal。第二步，右键该信号→Data Format→Analog→Step ，即可把它变成如图的模拟信号的样子）。 + +对该**图4**波形的解读： + +- theta 是一个不断递增的角度（0→2π→0→2π→...） +- ia, ib, ic 是用 theta 生成的正弦波，相位各自相差 (2/3)*π （也就是说 ia, ib, ic）构成了三相正弦波。 +- 使用 clark 变换把 ia, ib, ic 变换成 ialpha, ibeta ，得到一对正交的正弦波（相位相差 π/2 ）。 +- 使用 park 变换把 ialpha, ibeta 变换到定子坐标系，得到定值 id 和 iq （因为实际的计算误差，所以得到的是近似的定值，而不是严格的定值）。 + +| ![tb_clark_park_tr](./figures/tb_clark_park_tr.png) | +| :-------------------------------------------------: | +| **图4**：对 clark_tr 与 park_tr 仿真的波形。 | + +## cartesian2polar和svpwm的仿真 + +现在来运行 cartesian2polar （直角坐标转极坐标系）和 svpwm 的仿真。 + +双击 tb_svpwm_run_iverilog.bat 可以直接运行仿真，运行完后会生成波形文件 dump.vcd 。请用 gtkwave 打开 dump.vcd ，可以看到如**图5**的波形。 + +注意： pwma_duty、pwmb_duty、pwmc_duty 这三个信号不在顶层，你要在 svpwm 这个模块内才能找到这三个信号。 + +对**图5**波形的解读： + +- theta 是一个不断递增的角度（0→2π→0→2π→...） +- x 和 y 是用 theta 生成的正交的正弦波（或者说，y是正弦波，x是余弦波） +- 把 (x,y) 视作直角坐标值，然后 cartesian2polar 把它转换成极坐标系 (ρ, φ) ，也即 (rho, phi) +- 把 (rho, phi) 输给 svpwm ，产生了 pwma_duty、pwmb_duty、pwmc_duty 这三个马鞍波。如果你熟悉七段式 SVPWM 的原理，就应该知道为什么是马鞍波，这里不做赘述。 +- pwma_duty、pwmb_duty、pwmc_duty 分别决定了 pwm_a, pwm_b, pwm_c 的占空比（duty这个单词就是占空比的意思）。 + +| ![tb_svpwm](./figures/tb_svpwm.png) | +| :-----------------------------------------------: | +| **图5**：对 cartesian2polar 与 svpwm 仿真的波形。 | + +放大波形，可以看到确实是 duty 值越大，对应的 pwm 信号的占空比就越大，如**图6**。 + +| ![tb_svpwm_2](./figures/tb_svpwm_2.png) | +| :-------------------------------------: | +| **图6**：图5的放大。 | + +　 + +# FAQ + +一些用户在读代码时向本人反馈了一些疑问，我将它们整理如下。 + +### 关于 PCB 设计 + +* **问**： **相电流低压侧3电阻采样需要运放放大电流信号才能作为AD输入，但你[开源的PCB]((https://oshwhub.com/wangxuan/arduino-foc-shield))似乎找不到运放放大？** +* **答**： 我[开源的PCB](https://oshwhub.com/wangxuan/arduino-foc-shield)使用了一体化的三相无刷电机驱动芯片MP6540（U1），3相电流采样电阻和放大器是集成在里面的。请注意MP6540的 SOA, SOB, SOC 三个引脚，它们就是三相电流放大后的电压输出。 + + +### 关于 FOC 中的数学计算 + +* **问**： **三电阻采样后的电流重构的那部分代码如何理解？为什么 ia = ADCb + ADCc - 2*ADCa ？** +* **答**： 我们知道电机的相电流 ia, ib, ic 是双极性的（即有正有负的，分别代表流出电机和流入电机），但我们常用的ADC往往都是单极性的（即只能采样正电压）。那么，相电流采样-放大电路就必须考虑双极性到单极性的转换问题，工程上用的方法往往都是反向放大加偏置（包括MP6540内置采样-放大电路也是这种方案），它输出给ADC的电压遵循公式： + ADCa = -R × ia + Voff + ADCb = -R × ib + Voff + ADCc = -R × ic + Voff + 其中 R 是放大系数（R>0，也叫跨阻放大系数，因为 R 的量纲和电阻一样），因为反向放大所以加了负号。Voff 是偏置电压，以此保证 ADCa, ADCb, ADCc 是单极性的。另外又有基尔霍夫电流定律（KCL）： + ia + ib + ic = 0 + 联立以上公式，推出： + 3 * Voff = ADCa + ADCb + ADCc + 令 R = 1/(3*k) ，于是： + ia = (Voff - ADCa) / R + = k × (3 * Voff - 3 × ADCa) + = k × (ADCa + ADCb + ADCc - 3 × ADCa) + = k × (ADCb + ADCc - 2×ADCa) + 于是就有了你问的 ia = ADCb + ADCc - 2×ADCa 。 你肯定会疑惑，系数 k 哪儿去了？这个并不在乎，因为整个FOC都是线性系统，通过调整PID参数，能跑就行，系数只在理论分析时有用。 + +* **问** : **你的程序里是不是都没有在乎系数K，包括clark变换中得到的Iα和Iβ和ia、ib、ic也并没有满足严格的公式关系，程序中得到的Iα和Iβ是理论值的2倍。这是不是也可以用调整PID参数的思想来解释？** +* **答**： 是的，我很多地方的代码也与理论公式的系数不同，比如 clark 变换公式本来是： + Iα = Ia - Ib/2 - Ic/2 + Iβ = √3/2 * (Ib - Ic) + 我多乘了个2： + Iα = 2 * Ia - Ib - Ic + Iβ = √3 * (Ib - Ic) + 这是出于避免整数计算的截断导致的数据位丢失，比如 Ib/2 就会让 Ib 的最低 bit 丢失。不过实际上这种小误差基本不会影响控制质量。这种系数问题可以通过 PID 调参来消除。 + +* **问**: **你的代码中的 cartesian2polar.v 是把电压矢量从转子直角坐标系 (Vd, Vq) 变换到转子极坐标系 (Vrρ, Vrθ)，目的是什么？** +* **答**： 书上一般会说 SVPWM 模块输入的是定子直角坐标系下的电压，但我实现的 SVPWM 输入的是定子极坐标系下的电压，两种方法在数学上是等价的。而且 SVPWM 在 FPGA 里用查找表(ROM)实现，因此两种方法对电路复杂度影响不大。另外，输入极坐标系的 SVPWM 还带来 2 个好处和 1 个代价，好处 1 是更方便在开发过程中让电机开环地转起来（只需要让角度递增即可）。好处 2 是极坐标系下的 park 变换更简单，只需要用电压在转子坐标系中的角度减去电角度就能得到电压在定子坐标系中的角度。 代价是需要在 PID 的后面、park 变换的前面实现一个直角坐标系转极坐标系的运算，即 cartesian2polar.v + +### 关于 ADC 采样时机 + +* **问**： **AD7928只有一个T/H(采样保持器)，也就意味着这个AD一次只能保持一个通道的数据，也就是说当通道1 打开的时候采集A相的电流，然后采集完再打开通道2采集B相的电流，那么这并不是一个同步采集的过程，如何实现AD采样三相电流的同步输出？** +* **答**： 在电流采样问题上，我们与大多数 FOC 方案相同，因为 MP6540 里的采样电阻在下桥臂，所以规定 SVPWM 在每个控制周期（约 55us，对应频率18kHz）内至少有一段时间里 3 相都是下通上闭，称为采样窗口。FOC的基础振幅（也就是 foc_top.v 里的 MAX_AMP 参数）越大，采样窗口越短。当 MAX_AMP=9'd511 (最大值) 时，采样窗口长度就是 0 了。而默认的 MAX_AMP=9'd384 大概会让采样窗口长度为十几us。 +AD7928 只有一个T/H，所以采样窗口内要做 3 次采样，这个过程是 hold_detect.v 和 adc_ad7928.v 共同控制的，hold_detect.v负责在采样窗口开始时延迟一段时间（来让电流趋于稳定）后发出 sn_adc 信号脉冲，来告诉 adc_ad7928.v 可以开始工作了（可以通过 foc_top.v 里的 SAMPLE_DELAY 来调整该延迟）。然后 adc_ad7928.v 内部就会自动串行地完成 3 个通道的采样，最后再同步提交3个采样结果（提交的同时产生 o_en_adc 信号脉冲）。注意adc_ad7928.v是一个通用的 AD7928 控制器，每收到一个 i_sn_adc 信号脉冲，就进行一系列串行采样。其中采样多少次，每次采样哪一个通道，都可以通过 adc_ad7928.v 里的 parameter 来配置。所有通道采样结束后，产生o_en_adc信号脉冲，同时同步提交所有通道的结果。 +我把 foc_top.v 用来连接 ADC控制器的接口（也就是sn_adc, en_adc, adc_a, adc_b, adc_c 这几个信号）设计成同步读入3通道数据，是出于通用性、简约性和可移植性的原则考虑，因为这样的同步读入接口是 ADC 的一种高度抽象，最容易让人理解其时序（即，sn_adc脉冲命令ADC控制器开始工作。en_adc指示ADC读取器结束工作，同时 adc_a, adc_b, adc_c 上产生结果）。如果用户用了其它 ADC 型号，只需按照这个时序的抽象来具象地编写 ADC 控制器即可，而 foc_top.v 并不关心拟用的是1个串行的ADC还是3个并行的ADC，反正你都要给我同步提交。当然，用户必须自己算好 hold_detect.v 的延时 + ADC 采样三个通道（也即 sn_adc 脉冲和 en_adc 脉冲的时间差） 是小于采样窗口的长度的。 + + +* **问**： **进行串行采样的时候不会出现这样的问题：第一个时钟周期采到的是A相的电流，第2个时钟周期采的是B相，第3个时钟周期采到的是C相，而我们知道相电流是正弦变化的，这三个时钟周期采的A B C 三相电流并不是同一时刻的相电流，因此这将产生误差，而时钟周期是很短的，是不是产生的误差几乎可以忽略不计呢？** +* **答**： 首先指正一个不准确的地方， AD7928 的接口是 SPI （一种串行接口），其采样是多个时钟周期（而不是一个时钟周期）内完成的。因此三相的采样间隔是几十个时钟周期（具体数字我忘了，你可以仿真确定一下）。 +虽然不同步，但3相的采样毕竟都是在同一个控制周期的采样窗口（几微秒）内。而相电流的变化通常以控制周期（即几十微秒）为尺度变化，例如 3000r/min（50r/s）的转子，若极对数=7，其相电流是350Hz（周期28ms）的正弦波，其变化在几微秒内是可以忽略的。 + +　 + +# 参考资料 + +* [1] [Sensorless FOC for PMSM](https://www.microchip.com/stellent/groups/SiteComm_sg/documents/Training_Tutorials/en532365.pdf), MicroChip. +* [2] [Current sensing in BLDC motor application](https://www.st.com/resource/en/application_note/dm00666970-current-sensing-in-bldc-motor-application-stmicroelectronics.pdf), ST. +* [3] [Center-Aligned SVPWM Realization](https://www.ti.com/lit/an/sprabs6/sprabs6.pdf), TI +* [4] [MP6540, 3-phase, brushless DC motor drivers](https://www.monolithicpower.com/en/mp6540-mp6540a.html), MPS. +* [5] [AD7928, 8-Channel, 1 MSPS, 12-Bit ADC](https://www.analog.com/en/products/ad7928.html), Analog Devices. +* [6] [深入浅出讲解FOC算法与SVPWM技术](https://zhuanlan.zhihu.com/p/147659820), 稚晖 - 知乎 +* [7] [如何从零开始写一套自己的FOC矢量控制程序](https://zhuanlan.zhihu.com/p/103758450?utm_source=qzone), 上官致远 - 知乎 +* [8] [STM32电动机控制应用系列讲座](https://www.bilibili.com/video/BV1vT4y1j7kc) +* [9] [BLDC电机基础](https://www.bilibili.com/video/BV1TW411d7k6) + + + diff --git a/RTL/adc_ad7928.sv b/RTL/adc_ad7928.v similarity index 82% rename from RTL/adc_ad7928.sv rename to RTL/adc_ad7928.v index 5563abe..800111c 100644 --- a/RTL/adc_ad7928.sv +++ b/RTL/adc_ad7928.v @@ -1,10 +1,12 @@ +//-------------------------------------------------------------------------------------------------------- // 模块: adc_ad7928 // Type : synthesizable -// Standard: SystemVerilog 2005 (IEEE1800-2005) +// Standard: Verilog 2001 (IEEE1364-2001) // 功能：通过 SPI 接口从 ADC7928 (ADC芯片) 中读出 ADC 值。 // 参数：详见下方注释，该模块可以使用参数完全自由地配置单次转换要用多少个通道以及用哪些通道 // 输入输出：详见下方注释 +//-------------------------------------------------------------------------------------------------------- module adc_ad7928 #( parameter [2:0] CH_CNT = 3'd7, // 单次 ADC 转换使用的通道数为 CH_CNT+1，例如若 CH_CNT=0，则只使用 CH0 。若 CH_CNT=2，则使用 CH0,CH1,CH2。 若 CH_CNT=7，则使用 CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7。用的通道越多，ADC转换时延越长（即从 sn_adc 到 en_adc 之间的时间差越长） @@ -39,7 +41,7 @@ module adc_ad7928 #( localparam WAIT_CNT = 8'd6; -wire [2:0] channels [8]; +wire [2:0] channels [0:7]; assign channels[0] = CH0; assign channels[1] = CH1; assign channels[2] = CH2; @@ -56,7 +58,7 @@ reg [11:0] wshift; reg nfirst; reg [11:0] data_in_latch; reg sck_pre; -reg [11:0] ch_value [8]; +reg [11:0] ch_value [0:7]; assign o_adc_value0 = ch_value[0]; assign o_adc_value1 = ch_value[1]; @@ -75,15 +77,15 @@ always @ (posedge clk or negedge rstn) always @ (posedge clk or negedge rstn) if(~rstn) begin - cnt <= '0; + cnt <= 0; idx <= 3'd7; addr <= 3'd0; - wshift <= '1; - {spi_ss, sck_pre, spi_mosi} <= '1; + wshift <= 12'hFFF; + {spi_ss, sck_pre, spi_mosi} <= 3'b111; end else begin if(cnt==8'd0) begin - {spi_ss, sck_pre, spi_mosi} <= '1; - if(idx!='0) begin + {spi_ss, sck_pre, spi_mosi} <= 3'b111; + if(idx != 3'd0) begin cnt <= 8'd1; idx <= idx - 3'd1; end else if(i_sn_adc) begin @@ -91,15 +93,15 @@ always @ (posedge clk or negedge rstn) idx <= CH_CNT; end end else if(cnt==8'd1) begin - {spi_ss, sck_pre, spi_mosi} <= '1; - addr <= (idx=='0) ? CH_CNT : idx - 3'd1; + {spi_ss, sck_pre, spi_mosi} <= 3'b111; + addr <= (idx == 3'd0) ? CH_CNT : idx - 3'd1; cnt <= cnt + 8'd1; end else if(cnt==8'd2) begin - {spi_ss, sck_pre, spi_mosi} <= '1; + {spi_ss, sck_pre, spi_mosi} <= 3'b111; wshift <= {1'b1, 1'b0, 1'b0, channels[addr], 2'b11, 1'b0, 1'b0, 2'b11}; cnt <= cnt + 8'd1; end else if(cnt=WAIT_CNT+8'd2 && cnt> ATTENUAION; always @ (posedge clk or negedge rstn) if(~rstn) begin - cnt <= '0; - {signx, signy, signxy, absx, absy, smtb, smta, accb, acca} <= '0; - {a, theta, amp} <= '0; - {o_en, o_rho, o_theta} <= '0; + cnt <= 0; + {signx, signy, signxy, absx, absy, smtb, smta, accb, acca} <= 0; + {a, theta, amp} <= 0; + {o_en, o_rho, o_theta} <= 0; end else begin o_en <= 1'b0; if(cnt==5'd0) begin - accb <= '0; - acca <= '0; - signx <= i_x<$signed(16'd0); - signy <= i_y<$signed(16'd0); - absx <= i_x<$signed(16'd0) ? -i_x : i_x; - absy <= i_y<$signed(16'd0) ? -i_y : i_y; + accb <= 0; + acca <= 0; + signx <= (i_x < $signed(16'd0)); + signy <= (i_y < $signed(16'd0)); + absx <= (i_x < $signed(16'd0)) ? -i_x : i_x; + absy <= (i_y < $signed(16'd0)) ? -i_y : i_y; if(i_en) cnt <= 5'd30; end else begin diff --git a/RTL/foc/clark_tr.sv b/RTL/foc/clark_tr.v similarity index 83% rename from RTL/foc/clark_tr.sv rename to RTL/foc/clark_tr.v index d99c426..f404a5f 100644 --- a/RTL/foc/clark_tr.sv +++ b/RTL/foc/clark_tr.v @@ -1,8 +1,10 @@ -// clark_tr +//-------------------------------------------------------------------------------------------------------- +// 模块： clark_tr // Type : synthesizable -// Standard: SystemVerilog 2005 (IEEE1800-2005) +// Standard: Verilog 2001 (IEEE1364-2001) // 功能： clark 变换 +//-------------------------------------------------------------------------------------------------------- module clark_tr( input wire rstn, @@ -24,7 +26,7 @@ reg signed [15:0] ialpha_s2, i_beta1_s2, i_beta2_s2, i_beta3_s2; // pipeline stage 1 always @ (posedge clk or negedge rstn) if(~rstn) begin - {en_s1, ax2_s1, bmc_s1, bpc_s1} <= '0; + {en_s1, ax2_s1, bmc_s1, bpc_s1} <= 0; end else begin en_s1 <= i_en; ax2_s1 <= i_ia << 1; @@ -35,7 +37,7 @@ always @ (posedge clk or negedge rstn) // pipeline stage 2 always @ (posedge clk or negedge rstn) if(~rstn) begin - {en_s2, ialpha_s2, i_beta1_s2, i_beta2_s2, i_beta3_s2} <= '0; + {en_s2, ialpha_s2, i_beta1_s2, i_beta2_s2, i_beta3_s2} <= 0; end else begin en_s2 <= en_s1; ialpha_s2 <= ax2_s1 - bpc_s1; diff --git a/RTL/foc/foc_top.sv b/RTL/foc/foc_top.v similarity index 92% rename from RTL/foc/foc_top.sv rename to RTL/foc/foc_top.v index adc7aef..3b590be 100644 --- a/RTL/foc/foc_top.sv +++ b/RTL/foc/foc_top.v @@ -1,24 +1,27 @@ +//-------------------------------------------------------------------------------------------------------- // 模块: foc_top // Type : synthesizable, IP's top -// Standard: SystemVerilog 2005 (IEEE1800-2005) +// Standard: Verilog 2001 (IEEE1364-2001) // 功能：FOC 算法（仅包含电流环） + SVPWM // 参数：详见下方注释 // 输入输出：详见下方注释 +//-------------------------------------------------------------------------------------------------------- module foc_top #( // ----------------------------------------------- 模块参数 --------------------------------------------------------------------------------------------------------------------------------------------------- - parameter INIT_CYCLES = 16777216, // 决定了初始化步骤占多少个时钟(clk)周期，取值范围为1~4294967294。该值不能太短，因为要留足够的时间让转子回归电角度=0。例如若时钟(clk)频率为 36.864MHz，INIT_CYCLES=16777216，则初始化时间为 16777216/36864000=0.45 秒 - parameter logic ANGLE_INV = 1'b0, // 若角度传感器没装反（A->B->C->A 的旋转方向与 φ 增大的方向相同），则该参数应设为 0。若角度传感器装反了（A->B->C->A 的旋转方向与 φ 增大的方向相反），则该参数应设为 1。 - parameter logic [ 7:0] POLE_PAIR = 8'd7, // 电机极对数 (简记为N)，取值范围1~255，根据电机型号决定。（电角度ψ = 极对数N * 机械角度φ） - parameter logic [ 8:0] MAX_AMP = 9'd384, // SVPWM 的最大振幅，取值范围为1~511，该值越小，电机能达到的最大力矩越小；但考虑到使用3相下桥臂电阻采样法来采样电流，该值也不能太大，以保证3个下桥臂有足够的持续导通时间来供ADC进行采样。 - parameter logic [ 8:0] SAMPLE_DELAY = 9'd120, // 采样延时，取值范围0~511，考虑到3相的驱动 MOS 管从开始导通到电流稳定需要一定的时间，所以从3个下桥臂都导通，到 ADC 采样时刻之间需要一定的延时。该参数决定了该延时是多少个时钟周期，当延时结束时，该模块在 sn_adc 信号上产生一个高电平脉冲，指示外部 ADC “可以采样了” - parameter logic [23:0] Kp = 24'd32768,// 电流环 PID 控制算法的 P 参数 - parameter logic [23:0] Ki = 24'd2 // 电流环 PID 控制算法的 I 参数 + parameter INIT_CYCLES = 16777216, // 决定了初始化步骤占多少个时钟(clk)周期，取值范围为1~4294967294。该值不能太短，因为要留足够的时间让转子回归电角度=0。例如若时钟(clk)频率为 36.864MHz，INIT_CYCLES=16777216，则初始化时间为 16777216/36864000=0.45 秒 + parameter ANGLE_INV = 0, // 若角度传感器没装反（A->B->C->A 的旋转方向与 φ 增大的方向相同），则该参数应设为 0。若角度传感器装反了（A->B->C->A 的旋转方向与 φ 增大的方向相反），则该参数应设为 1。 + parameter [ 7:0] POLE_PAIR = 8'd7, // 电机极对数 (简记为N)，取值范围1~255，根据电机型号决定。（电角度ψ = 极对数N * 机械角度φ） + parameter [ 8:0] MAX_AMP = 9'd384, // SVPWM 的最大振幅，取值范围为1~511，该值越小，电机能达到的最大力矩越小；但考虑到使用3相下桥臂电阻采样法来采样电流，该值也不能太大，以保证3个下桥臂有足够的持续导通时间来供ADC进行采样。 + parameter [ 8:0] SAMPLE_DELAY = 9'd120 // 采样延时，取值范围0~511，考虑到3相的驱动 MOS 管从开始导通到电流稳定需要一定的时间，所以从3个下桥臂都导通，到 ADC 采样时刻之间需要一定的延时。该参数决定了该延时是多少个时钟周期，当延时结束时，该模块在 sn_adc 信号上产生一个高电平脉冲，指示外部 ADC “可以采样了” ) ( // ----------------------------------------------- 驱动时钟和复位 --------------------------------------------------------------------------------------------------------------------------------------------- input wire rstn, // 复位信号，应该先拉低来对模块进行复位，然后一直保持高电平来让模块正常工作。 input wire clk, // 时钟信号，频率可取几十MHz。控制频率 = 时钟频率 / 2048。比如若时钟频率为 36.864MHz ，那么控制频率为 36.864MHz/2048=18kHz。（控制频率 = 3相电流采样的采样率 = PID算法的控制频率 = SVPWM占空比的更新频率） + // ----------------------------------------------- PI 参数 ---------------------------------------------------------------------------------------------------------------------------------------------------- + input wire [30:0] Kp, + input wire [30:0] Ki, // ----------------------------------------------- 角度传感器输入信号 ----------------------------------------------------------------------------------------------------------------------------------------- input wire [11:0] phi, // 角度传感器输入（机械角度，简记为φ），取值范围0~4095。0对应0°；1024对应90°；2048对应180°；3072对应270°。 // ----------------------------------------------- 3相电流 ADC 采样时刻控制信号 和采样结果输入信号 ------------------------------------------------------------------------------------------------------------ @@ -73,13 +76,13 @@ reg [11:0] vs_theta; // 定子极坐标系上的电压矢量的角 generate if(ANGLE_INV) begin // 如果角度传感器装反了 always @ (posedge clk or negedge init_done) if(~init_done) - psi <= '0; + psi <= 0; else psi <= {4'h0, POLE_PAIR} * (init_phi - phi); // ψ = -N * (φ - Φ) end else begin // 如果角度传感器没装反 always @ (posedge clk or negedge init_done) if(~init_done) - psi <= '0; + psi <= 0; else psi <= {4'h0, POLE_PAIR} * (phi - init_phi); // ψ = N * (φ - Φ) end endgenerate @@ -95,7 +98,7 @@ end endgenerate // 输出更新：ADC 每采样完成一次（即en_adc每产生一次高电平脉冲）后更新一次，即更新频率 = 控制周期，更新后 en_iabc 产生一个时钟周期的高电平脉冲 always @ (posedge clk or negedge init_done) if(~init_done) begin - {en_iabc, ia, ib, ic} <= '0; + {en_iabc, ia, ib, ic} <= 0; end else begin en_iabc <= en_adc; if(en_adc) begin @@ -113,7 +116,7 @@ always @ (posedge clk or negedge init_done) // 计算公式：Iα = 2 * Ia - Ib - Ic // Iβ = √3 * (Ib - Ic) // 输出更新：en_iabc 每产生一个高电平脉冲后的若干周期后 Iα, Iβ 更新，同时 en_ialphabeta 产生一个时钟周期的高电平脉冲，即更新频率 = 控制周期 -clark_tr clark_tr_i( +clark_tr u_clark_tr ( .rstn ( init_done ), .clk ( clk ), .i_en ( en_iabc ), @@ -134,7 +137,7 @@ clark_tr clark_tr_i( // 计算公式：Id = Iα * cosψ + Iβ * sinψ; // Iq = Iβ * cosψ - Iα * sinψ; // 输出更新：en_ialphabeta 每产生一个高电平脉冲后的若干周期后 Id, Iq 更新，同时 en_idq 产生一个时钟周期的高电平脉冲，即更新频率 = 控制周期 -park_tr park_tr_i ( +park_tr u_park_tr ( .rstn ( init_done ), .clk ( clk ), .psi ( psi ), // input : ψ @@ -154,13 +157,12 @@ park_tr park_tr_i ( // 输出 ：电压矢量在d轴上的分量（vd） // 原理 ：PID 控制（实际上没有D，只有P和I） // 输出更新：en_idq 每产生一个高电平脉冲后的若干周期后 Vd 更新，即更新频率 = 控制周期 -pi_controller #( - .Kp ( Kp ), - .Ki ( Ki ) -) pi_id_i ( +pi_controller u_id_pi ( .rstn ( init_done ), .clk ( clk ), .i_en ( en_idq ), + .i_Kp ( Kp ), + .i_Ki ( Ki ), .i_aim ( id_aim ), // input : Idaim .i_real ( id ), // input : Id .o_en ( ), @@ -175,13 +177,12 @@ pi_controller #( // 输出 ：电压矢量在q轴上的分量（vq） // 原理 ：PID 控制（实际上没有D，只有P和I） // 输出更新：en_idq 每产生一个高电平脉冲后的若干周期后 Vq 更新，即更新频率 = 控制周期 -pi_controller #( - .Kp ( Kp ), - .Ki ( Ki ) -) pi_iq_i ( +pi_controller u_iq_pi ( .rstn ( init_done ), .clk ( clk ), .i_en ( en_idq ), + .i_Kp ( Kp ), + .i_Ki ( Ki ), .i_aim ( iq_aim ), // input : Iqaim .i_real ( iq ), // input : Iq .o_en ( ), @@ -196,7 +197,7 @@ pi_controller #( // 输出 ：电压矢量在转子极坐标系上的幅值（Vrρ） // 原理 ：电压矢量在转子极坐标系上的角度（Vrθ） // 输出更新：Vd, Vq 每产生变化的若干周期后 Vrρ 和 Vrθ 更新，更新频率 = 控制周期 -cartesian2polar cartesian2polar_i ( +cartesian2polar u_cartesian2polar ( .rstn ( init_done ), .clk ( clk ), .i_en ( 1'b1 ), @@ -216,9 +217,9 @@ cartesian2polar cartesian2polar_i ( // 输出 ：Φ，Vsρ, Vsθ，init_done always @ (posedge clk or negedge rstn) if(~rstn) begin - {vs_rho, vs_theta} <= '0; - init_cnt <= '0; - init_phi <= '0; + {vs_rho, vs_theta} <= 0; + init_cnt <= 0; + init_phi <= 0; init_done <= 1'b0; end else begin if(init_cnt<=INIT_CYCLES) begin // 若 init_cnt 计数变量 <= INIT_CYCLES ，则初始化未完成 @@ -242,7 +243,7 @@ always @ (posedge clk or negedge rstn) // 输出 ：PWM使能信号 pwm_en // 3相PWM信号 pwm_a, pwm_b, pwm_c // 说明 ：该模块产生的 PWM 的频率是 clk 频率 / 2048。例如 clk 为 36.864MHz ，则 PWM 的频率为 36.864MHz / 2048 = 18kHz -svpwm svpwm_i ( +svpwm u_svpwm ( .rstn ( rstn ), .clk ( clk ), .v_amp ( MAX_AMP ), @@ -262,7 +263,7 @@ svpwm svpwm_i ( // 原理 ：该模块检测 pwm_a, pwm_b, pwm_c 均为低电平的时刻，并延迟 SAMPLE_DELAY 的时钟周期，在 sn_adc 信号上产生一个时钟周期的高电平。 hold_detect #( .SAMPLE_DELAY ( SAMPLE_DELAY ) -) adc_sn_ctrl_i ( +) u_adc_sn_ctrl ( .rstn ( init_done ), .clk ( clk ), .in ( ~pwm_a & ~pwm_b & ~pwm_c ), // input : 当 pwm_a, pwm_b, pwm_c 均为低电平时=1，否则=0 diff --git a/RTL/foc/hold_detect.sv b/RTL/foc/hold_detect.v similarity index 74% rename from RTL/foc/hold_detect.sv rename to RTL/foc/hold_detect.v index ba4a732..fdc0b9d 100644 --- a/RTL/foc/hold_detect.sv +++ b/RTL/foc/hold_detect.v @@ -1,8 +1,10 @@ +//-------------------------------------------------------------------------------------------------------- // 模块： hold_detect // Type : synthesizable -// Standard: SystemVerilog 2005 (IEEE1800-2005) +// Standard: Verilog 2001 (IEEE1364-2001) // 功能： 检测 in 从高电平变为低电平并保持 SAMPLE_DELAY 个时钟周期，在 sn_adc 信号上产生一个时钟周期的高电平。 +//-------------------------------------------------------------------------------------------------------- module hold_detect #( parameter [15:0] SAMPLE_DELAY = 16'd100 @@ -18,7 +20,7 @@ reg [15:0] cnt; always @ (posedge clk or negedge rstn) if(~rstn) - {latch1, latch2} <= '1; + {latch1, latch2} <= 2'b11; else {latch1, latch2} <= {in, latch1}; diff --git a/RTL/foc/park_tr.sv b/RTL/foc/park_tr.v similarity index 71% rename from RTL/foc/park_tr.sv rename to RTL/foc/park_tr.v index d0b738c..2dc5ba3 100644 --- a/RTL/foc/park_tr.sv +++ b/RTL/foc/park_tr.v @@ -1,8 +1,10 @@ +//-------------------------------------------------------------------------------------------------------- // 模块： park_tr // Type : synthesizable -// Standard: SystemVerilog 2005 (IEEE1800-2005) +// Standard: Verilog 2001 (IEEE1364-2001) // 功能： park 变换器 +//-------------------------------------------------------------------------------------------------------- module park_tr( input wire rstn, @@ -14,7 +16,7 @@ module park_tr( output reg signed [15:0] o_id, o_iq ); -reg signed [15:0] sin_psi, cos_psi; // -1~+1 is mapped to -16384~+16384 +wire signed [15:0] sin_psi, cos_psi; // -1~+1 is mapped to -16384~+16384 reg en_s1; reg signed [31:0] alpha_cos, alpha_sin, beta_cos, beta_sin; @@ -22,7 +24,7 @@ reg signed [31:0] alpha_cos, alpha_sin, beta_cos, beta_sin; wire signed[31:0] ide = alpha_cos + beta_sin; wire signed[31:0] iqe = beta_cos - alpha_sin; -sincos sincos_i( +sincos u_sincos ( .rstn ( rstn ), .clk ( clk ), .i_en ( 1'b1 ), @@ -34,7 +36,7 @@ sincos sincos_i( always @ (posedge clk or negedge rstn) if(~rstn) begin - {en_s1, alpha_cos, alpha_sin, beta_cos, beta_sin} <= '0; + {en_s1, alpha_cos, alpha_sin, beta_cos, beta_sin} <= 0; end else begin en_s1 <= i_en; alpha_cos <= i_ialpha * cos_psi; @@ -45,7 +47,7 @@ always @ (posedge clk or negedge rstn) always @ (posedge clk or negedge rstn) if(~rstn) begin - {o_en, o_id, o_iq} <= '0; + {o_en, o_id, o_iq} <= 0; end else begin o_en <= en_s1; if(en_s1) begin diff --git a/RTL/foc/pi_controller.sv b/RTL/foc/pi_controller.sv deleted file mode 100644 index f5806a4..0000000 --- a/RTL/foc/pi_controller.sv +++ /dev/null @@ -1,106 +0,0 @@ - -// 模块： pi_controller -// Type : synthesizable -// Standard: SystemVerilog 2005 (IEEE1800-2005) -// 功能： PI 控制器 - -module pi_controller #( - parameter logic [23:0] Kp = 24'd32768, - parameter logic [23:0] Ki = 24'd2 -) ( - input wire rstn, - input wire clk, - input wire i_en, - input wire signed [15:0] i_aim, - input wire signed [15:0] i_real, - output reg o_en, - output wire signed [15:0] o_value -); - -reg en1, en2, en3, en4; -reg signed [31:0] pdelta, idelta, kpdelta1, kpdelta, kidelta, kpidelta, value; - -assign o_value = value[31:16]; - -function automatic logic signed [31:0] protect_add(input logic signed [31:0] a, input logic signed [31:0] b); - automatic logic signed [32:0] y; - y = $signed({a[31],a}) + $signed({b[31],b}); - if( y > $signed(33'h7fffffff) ) - return $signed(32'h7fffffff); - else if(y < -$signed(33'h7fffffff) ) - return -$signed(32'h7fffffff); - else - return $signed(y[31:0]); -endfunction - -function automatic logic signed [31:0] protect_mul(input logic signed [31:0] a, input logic signed [24:0] b); - automatic logic signed [56:0] y; - y = a * b; - if( y > $signed(57'h7fffffff) ) - return $signed(32'h7fffffff); - else if(y < -$signed(57'h7fffffff) ) - return -$signed(32'h7fffffff); - else - return $signed(y[31:0]); -endfunction - -always @ (posedge clk or negedge rstn) - if(~rstn) begin - en1 <= 1'b0; - pdelta <= 0; - end else begin - en1 <= i_en; - if(i_en) begin - pdelta <= $signed({{16{i_aim[15]}},i_aim}) - $signed({{16{i_real[15]}},i_real}); - end - end - -always @ (posedge clk or negedge rstn) - if(~rstn) begin - en2 <= 1'b0; - kpdelta1 <= 0; - idelta <= 0; - end else begin - en2 <= en1; - if(en1) begin - kpdelta1 <= protect_mul(pdelta, $signed({1'b0,Kp}) ); - idelta <= protect_add(idelta, pdelta); - end - end - -always @ (posedge clk or negedge rstn) - if(~rstn) begin - en3 <= 1'b0; - kpdelta <= 0; - kidelta <= 0; - end else begin - en3 <= en2; - if(en2) begin - kpdelta <= kpdelta1; - kidelta <= protect_mul(idelta, $signed({1'b0,Ki}) ); - end - end - -always @ (posedge clk or negedge rstn) - if(~rstn) begin - en4 <= 1'b0; - kpidelta <= 0; - end else begin - en4 <= en3; - if(en3) begin - kpidelta <= protect_add(kpdelta, kidelta); - end - end - -always @ (posedge clk or negedge rstn) - if(~rstn) begin - o_en <= 1'b0; - value <= 0; - end else begin - o_en <= en4; - if(en4) begin - value <= protect_add(value, kpidelta); - end - end - -endmodule diff --git a/RTL/foc/pi_controller.v b/RTL/foc/pi_controller.v new file mode 100644 index 0000000..a1c6eff --- /dev/null +++ b/RTL/foc/pi_controller.v @@ -0,0 +1,132 @@ + +//-------------------------------------------------------------------------------------------------------- +// 模块： pi_controller +// Type : synthesizable +// Standard: Verilog 2001 (IEEE1364-2001) +// 功能： PI 控制器 +//-------------------------------------------------------------------------------------------------------- + +module pi_controller ( + input wire rstn, + input wire clk, + input wire i_en, + input wire [30:0] i_Kp, + input wire [30:0] i_Ki, + input wire signed [15:0] i_aim, + input wire signed [15:0] i_real, + output reg o_en, + output wire signed [15:0] o_value +); + +reg en1, en2, en3, en4; +reg signed [31:0] pdelta, idelta, kpdelta1, kpdelta, kidelta, kpidelta, value; +reg [30:0] Kp0=0, Ki0=0, Ki1=0; + +assign o_value = value[31:16]; + + +function signed [31:0] protect_add; + input signed [31:0] a, b; + reg signed [32:0] y; +//function automatic logic signed [31:0] protect_add(input logic signed [31:0] a, input logic signed [31:0] b); +// automatic logic signed [32:0] y; +begin + y = $signed({a[31],a}) + $signed({b[31],b}); + if( y > $signed(33'h7fffffff) ) + protect_add = $signed(32'h7fffffff); + else if(y < -$signed(33'h7fffffff) ) + protect_add = -$signed(32'h7fffffff); + else + protect_add = $signed(y[31:0]); +end +endfunction + + +function signed [31:0] protect_mul; + input signed [31:0] a, b; + reg signed [56:0] y; +//function automatic logic signed [31:0] protect_mul(input logic signed [31:0] a, input logic signed [24:0] b); +// automatic logic signed [56:0] y; +begin + y = a * b; + if( y > $signed(57'h7fffffff) ) + protect_mul = $signed(32'h7fffffff); + else if(y < -$signed(57'h7fffffff) ) + protect_mul = -$signed(32'h7fffffff); + else + protect_mul = $signed(y[31:0]); +end +endfunction + + +always @ (posedge clk or negedge rstn) + if(~rstn) begin + en1 <= 1'b0; + en2 <= 1'b0; + en3 <= 1'b0; + en4 <= 1'b0; + o_en <= 1'b0; + end else begin + en1 <= i_en; + en2 <= en1; + en3 <= en2; + en4 <= en3; + o_en <= en4; + end + + +always @ (posedge clk or negedge rstn) + if(~rstn) begin + Kp0 <= 0; + Ki0 <= 0; + pdelta <= 0; + end else begin + if(i_en) begin + Kp0 <= i_Kp; + Ki0 <= i_Ki; + pdelta <= $signed({{16{i_aim[15]}},i_aim}) - $signed({{16{i_real[15]}},i_real}); // pdelta = i_aim - i_real + end + end + +always @ (posedge clk or negedge rstn) + if(~rstn) begin + Ki1 <= 0; + kpdelta1 <= 0; + idelta <= 0; + end else begin + if (en1) begin + Ki1 <= Ki0; + kpdelta1 <= protect_mul(pdelta, $signed({1'h0, Kp0}) ); // kpdelta1 = Kp * pdelta + idelta <= protect_add(idelta, pdelta); // idelta += (i_aim - i_real) that is: idelta = Σ pdelta + end + end + +always @ (posedge clk or negedge rstn) + if(~rstn) begin + kpdelta <= 0; + kidelta <= 0; + end else begin + if (en2) begin + kpdelta <= kpdelta1; // kpdelta = Kp * pdelta + kidelta <= protect_mul(idelta, $signed({1'h0, Ki1}) ); // kidelta = Ki * Σ pdelta + end + end + +always @ (posedge clk or negedge rstn) + if(~rstn) begin + kpidelta <= 0; + end else begin + if (en3) + kpidelta <= protect_add(kpdelta, kidelta); // kpidelta = Kp * pdelta + Ki * Σ pdelta + end + +always @ (posedge clk or negedge rstn) + if(~rstn) begin + value <= 0; + end else begin + if (en4) + value <= kpidelta; // modified at 20230609, now it is a stardard PID + // value <= protect_add(value, kpidelta); // + end + +endmodule diff --git a/RTL/foc/sincos.sv b/RTL/foc/sincos.v similarity index 93% rename from RTL/foc/sincos.sv rename to RTL/foc/sincos.v index d528806..79377f6 100644 --- a/RTL/foc/sincos.sv +++ b/RTL/foc/sincos.v @@ -1,10 +1,12 @@ +//-------------------------------------------------------------------------------------------------------- // 模块：sincos // Type : synthesizable -// Standard: SystemVerilog 2005 (IEEE1800-2005) +// Standard: Verilog 2001 (IEEE1364-2001) // 功能： 计算 sin 和 cos // 在 i_theta 上给出角度（0~π被映射为0~4095）， // 在 o_sin 和 o_cos 上产生 sinθ 和 cosθ （-1~+1 被映射为 -16384~+16384） +//-------------------------------------------------------------------------------------------------------- module sincos( input wire rstn, @@ -15,7 +17,15 @@ module sincos( output reg signed [15:0] o_sin, o_cos // -1~+1 is mapped to -16384~+16384 ); -enum logic [2:0] {IDLE, S1, S2, S3, S4, S5} stat; + +localparam [2:0] IDLE = 3'd0, + S1 = 3'd1, + S2 = 3'd2, + S3 = 3'd3, + S4 = 3'd4, + S5 = 3'd5; + +reg [ 2:0] stat; reg [11:0] theta_a, theta_b; reg cos_z, cos_s, sin_z, sin_s; @@ -26,11 +36,11 @@ reg signed [15:0] cos_tmp; always @ (posedge clk or negedge rstn) if(~rstn) begin stat <= IDLE; - {theta_a, theta_b} <= '0; - {cos_z, cos_s, sin_z, sin_s} <= '0; - rom_x <= '0; - cos_tmp <= '0; - {o_en, o_sin, o_cos} <= '0; + {theta_a, theta_b} <= 0; + {cos_z, cos_s, sin_z, sin_s} <= 0; + rom_x <= 0; + cos_tmp <= 0; + {o_en, o_sin, o_cos} <= 0; end else begin o_en <= 1'b0; case(stat) @@ -73,7 +83,7 @@ always @ (posedge clk or negedge rstn) S3: begin stat <= S4; if(cos_z) - cos_tmp <= '0; + cos_tmp <= 0; else if(cos_s) cos_tmp <= -$signed({1'b0,rom_y}); else @@ -84,13 +94,14 @@ always @ (posedge clk or negedge rstn) o_en <= 1'b1; o_cos <= cos_tmp; if(sin_z) - o_sin <= '0; + o_sin <= 0; else if(sin_s) o_sin <= -$signed({1'b0,rom_y}); else o_sin <= $signed({1'b0,rom_y}); end - S5: stat <= IDLE; + default: // S5: + stat <= IDLE; endcase end diff --git a/RTL/foc/svpwm.sv b/RTL/foc/svpwm.v similarity index 93% rename from RTL/foc/svpwm.sv rename to RTL/foc/svpwm.v index 9f8eba2..09cee5c 100644 --- a/RTL/foc/svpwm.sv +++ b/RTL/foc/svpwm.v @@ -1,12 +1,14 @@ +//-------------------------------------------------------------------------------------------------------- // 模块：svpwm // Type : synthesizable -// Standard: SystemVerilog 2005 (IEEE1800-2005) +// Standard: Verilog 2001 (IEEE1364-2001) // 功能：7 段式 SVPWM 生成器（调制器） // 输入：定子极坐标系下的电压矢量 Vsρ, Vsθ // 输出：PWM使能信号 pwm_en // 3相PWM信号 pwm_a, pwm_b, pwm_c // 说明：该模块产生的 PWM 的频率是 clk 频率 / 2048。例如 clk 为 36.864MHz ，则 PWM 的频率为 36.864MHz / 2048 = 18kHz +//-------------------------------------------------------------------------------------------------------- module svpwm ( input wire rstn, @@ -35,25 +37,25 @@ reg pwm_act; always @ (posedge clk or negedge rstn) if(~rstn) - mul_o <= '0; + mul_o <= 12'd0; else mul_o <= mul_y[20:9]; always @ (posedge clk or negedge rstn) if(~rstn) - cnt <= '0; + cnt <= 11'd0; else cnt <= cnt + 11'd1; always @ (posedge clk or negedge rstn) if(~rstn) begin - rom_x <= '0; - mul_i1 <= '0; - mul_i2 <= '0; - {sya, syb, syc} <= '0; - {ya, yb} <= '0; - {pwma_duty, pwmb_duty, pwmc_duty} <= '0; - {pwma_lb, pwma_ub, pwmb_lb, pwmb_ub, pwmc_lb, pwmc_ub} <= '0; + rom_x <= 0; + mul_i1 <= 0; + mul_i2 <= 0; + {sya, syb, syc} <= 0; + {ya, yb} <= 0; + {pwma_duty, pwmb_duty, pwmc_duty} <= 0; + {pwma_lb, pwma_ub, pwmb_lb, pwmb_ub, pwmc_lb, pwmc_ub} <= 0; pwm_act <= 1'b0; end else begin if(cnt==11'd2041-ROM_LATENCY) begin diff --git a/RTL/fpga_top.sv b/RTL/fpga_top.v similarity index 80% rename from RTL/fpga_top.sv rename to RTL/fpga_top.v index f807c06..12b59af 100644 --- a/RTL/fpga_top.sv +++ b/RTL/fpga_top.v @@ -1,10 +1,12 @@ +//-------------------------------------------------------------------------------------------------------- // fpga_top // Type : synthesizable, FPGA's top -// Standard: SystemVerilog 2005 (IEEE1800-2005) +// Standard: Verilog 2001 (IEEE1364-2001) // 功能：FOC 使用示例，是FPGA工程的顶层模块，控制电机的切向力矩一会顺时针一会逆时针，同时可以通过 UART 监测电流环控制的跟随曲线 // 参数：无 // 输入输出：详见下方注释 +//-------------------------------------------------------------------------------------------------------- module fpga_top ( input wire clk_50m, // 连接 50MHz 晶振 @@ -25,6 +27,7 @@ module fpga_top ( output wire uart_tx ); + wire rstn; // 复位信号，初始为0，当PLL锁相成功后置1。 wire clk; // 时钟信号，频率可取几十MHz。控制频率 = 时钟频率 / 2048。比如本例取时钟频率为 36.864MHz ，那么控制频率为 36.864MHz/2048=18kHz。（控制频率 = 3相电流采样的采样率 = PID算法的控制频率 = SVPWM占空比的更新频率） @@ -47,9 +50,9 @@ reg signed [15:0] iq_aim; // 转子 q 轴（交轴）的目标电流值， // PLL，用 50MHz 时钟（clk_50m）产生 36.864 MHz 时钟（clk） // 注：该模块仅适用于 Altera Cyclone IV FPGA ，对于其他厂家或系列的FPGA，请使用各自相同效果的IP核/原语（例如Xilinx的clock wizard）代替该模块。 wire [3:0] subwire0; -altpll altpll_i ( .inclk ( {1'b0, clk_50m} ), .clk ( {subwire0, clk} ), .locked ( rstn ), .activeclock (), .areset (1'b0), .clkbad (), .clkena ({6{1'b1}}), .clkloss (), .clkswitch (1'b0), .configupdate (1'b0), .enable0 (), .enable1 (), .extclk (), .extclkena ({4{1'b1}}), .fbin (1'b1), .fbmimicbidir (), .fbout (), .fref (), .icdrclk (), .pfdena (1'b1), .phasecounterselect ({4{1'b1}}), .phasedone (), .phasestep (1'b1), .phaseupdown (1'b1), .pllena (1'b1), .scanaclr (1'b0), .scanclk (1'b0), .scanclkena (1'b1), .scandata (1'b0), .scandataout (), .scandone (), .scanread (1'b0), .scanwrite (1'b0), .sclkout0 (), .sclkout1 (), .vcooverrange (), .vcounderrange ()); -defparam altpll_i.bandwidth_type = "AUTO", altpll_i.clk0_divide_by = 99, altpll_i.clk0_duty_cycle = 50, altpll_i.clk0_multiply_by = 73, altpll_i.clk0_phase_shift = "0", altpll_i.compensate_clock = "CLK0", altpll_i.inclk0_input_frequency = 20000, altpll_i.intended_device_family = "Cyclone IV E", altpll_i.lpm_hint = "CBX_MODULE_PREFIX=pll", altpll_i.lpm_type = "altpll", altpll_i.operation_mode = "NORMAL", altpll_i.pll_type = "AUTO", altpll_i.port_activeclock = "PORT_UNUSED", altpll_i.port_areset = "PORT_UNUSED", altpll_i.port_clkbad0 = "PORT_UNUSED", altpll_i.port_clkbad1 = "PORT_UNUSED", altpll_i.port_clkloss = "PORT_UNUSED", altpll_i.port_clkswitch = "PORT_UNUSED", altpll_i.port_configupdate = "PORT_UNUSED", altpll_i.port_fbin = "PORT_UNUSED", altpll_i.port_inclk0 = "PORT_USED", altpll_i.port_inclk1 = "PORT_UNUSED", altpll_i.port_locked = "PORT_USED", altpll_i.port_pfdena = "PORT_UNUSED", altpll_i.port_phasecounterselect = "PORT_UNUSED", altpll_i.port_phasedone = "PORT_UNUSED", altpll_i.port_phasestep = "PORT_UNUSED", altpll_i.port_phaseupdown = "PORT_UNUSED", altpll_i.port_pllena = "PORT_UNUSED", altpll_i.port_scanaclr = "PORT_UNUSED", altpll_i.port_scanclk = "PORT_UNUSED", altpll_i.port_scanclkena = "PORT_UNUSED", altpll_i.port_scandata = "PORT_UNUSED", altpll_i.port_scandataout = "PORT_UNUSED", altpll_i.port_scandone = "PORT_UNUSED", altpll_i.port_scanread = "PORT_UNUSED", altpll_i.port_scanwrite = "PORT_UNUSED", altpll_i.port_clk0 = "PORT_USED", altpll_i.port_clk1 = "PORT_UNUSED", altpll_i.port_clk2 = "PORT_UNUSED", altpll_i.port_clk3 = "PORT_UNUSED", altpll_i.port_clk4 = "PORT_UNUSED", altpll_i.port_clk5 = "PORT_UNUSED", altpll_i.port_clkena0 = "PORT_UNUSED", altpll_i.port_clkena1 = "PORT_UNUSED", altpll_i.port_clkena2 = "PORT_UNUSED", altpll_i.port_clkena3 = "PORT_UNUSED", altpll_i.port_clkena4 = "PORT_UNUSED", altpll_i.port_clkena5 = "PORT_UNUSED", altpll_i.port_extclk0 = "PORT_UNUSED", altpll_i.port_extclk1 = "PORT_UNUSED", altpll_i.port_extclk2 = "PORT_UNUSED", altpll_i.port_extclk3 = "PORT_UNUSED", altpll_i.self_reset_on_loss_lock = "OFF", altpll_i.width_clock = 5; - +altpll u_altpll ( .inclk ( {1'b0, clk_50m} ), .clk ( {subwire0, clk} ), .locked ( rstn ), .activeclock (), .areset (1'b0), .clkbad (), .clkena ({6{1'b1}}), .clkloss (), .clkswitch (1'b0), .configupdate (1'b0), .enable0 (), .enable1 (), .extclk (), .extclkena ({4{1'b1}}), .fbin (1'b1), .fbmimicbidir (), .fbout (), .fref (), .icdrclk (), .pfdena (1'b1), .phasecounterselect ({4{1'b1}}), .phasedone (), .phasestep (1'b1), .phaseupdown (1'b1), .pllena (1'b1), .scanaclr (1'b0), .scanclk (1'b0), .scanclkena (1'b1), .scandata (1'b0), .scandataout (), .scandone (), .scanread (1'b0), .scanwrite (1'b0), .sclkout0 (), .sclkout1 (), .vcooverrange (), .vcounderrange ()); +defparam u_altpll.bandwidth_type = "AUTO", u_altpll.clk0_divide_by = 99, u_altpll.clk0_duty_cycle = 50, u_altpll.clk0_multiply_by = 73, u_altpll.clk0_phase_shift = "0", u_altpll.compensate_clock = "CLK0", u_altpll.inclk0_input_frequency = 20000, u_altpll.intended_device_family = "Cyclone IV E", u_altpll.lpm_hint = "CBX_MODULE_PREFIX=pll", u_altpll.lpm_type = "altpll", u_altpll.operation_mode = "NORMAL", u_altpll.pll_type = "AUTO", u_altpll.port_activeclock = "PORT_UNUSED", u_altpll.port_areset = "PORT_UNUSED", u_altpll.port_clkbad0 = "PORT_UNUSED", u_altpll.port_clkbad1 = "PORT_UNUSED", u_altpll.port_clkloss = "PORT_UNUSED", u_altpll.port_clkswitch = "PORT_UNUSED", u_altpll.port_configupdate = "PORT_UNUSED", u_altpll.port_fbin = "PORT_UNUSED", u_altpll.port_inclk0 = "PORT_USED", u_altpll.port_inclk1 = "PORT_UNUSED", u_altpll.port_locked = "PORT_USED", u_altpll.port_pfdena = "PORT_UNUSED", u_altpll.port_phasecounterselect = "PORT_UNUSED", u_altpll.port_phasedone = "PORT_UNUSED", u_altpll.port_phasestep = "PORT_UNUSED", u_altpll.port_phaseupdown = "PORT_UNUSED", u_altpll.port_pllena = "PORT_UNUSED", u_altpll.port_scanaclr = "PORT_UNUSED", u_altpll.port_scanclk = "PORT_UNUSED", u_altpll.port_scanclkena = "PORT_UNUSED", u_altpll.port_scandata = "PORT_UNUSED", u_altpll.port_scandataout = "PORT_UNUSED", u_altpll.port_scandone = "PORT_UNUSED", u_altpll.port_scanread = "PORT_UNUSED", u_altpll.port_scanwrite = "PORT_UNUSED", u_altpll.port_clk0 = "PORT_USED", u_altpll.port_clk1 = "PORT_UNUSED", u_altpll.port_clk2 = "PORT_UNUSED", u_altpll.port_clk3 = "PORT_UNUSED", u_altpll.port_clk4 = "PORT_UNUSED", u_altpll.port_clk5 = "PORT_UNUSED", u_altpll.port_clkena0 = "PORT_UNUSED", u_altpll.port_clkena1 = "PORT_UNUSED", u_altpll.port_clkena2 = "PORT_UNUSED", u_altpll.port_clkena3 = "PORT_UNUSED", u_altpll.port_clkena4 = "PORT_UNUSED", u_altpll.port_clkena5 = "PORT_UNUSED", u_altpll.port_extclk0 = "PORT_UNUSED", u_altpll.port_extclk1 = "PORT_UNUSED", u_altpll.port_extclk2 = "PORT_UNUSED", u_altpll.port_extclk3 = "PORT_UNUSED", u_altpll.self_reset_on_loss_lock = "OFF", u_altpll.width_clock = 5; +//assign rstn=1'b1; assign clk=clk_50m; // 简易 I2C 读取控制器，实现 AS5600 磁编码器读取，读出当前转子机械角度 φ @@ -58,7 +61,7 @@ i2c_register_read #( .CLK_DIV ( 16'd10 ), // i2c_scl 时钟信号分频系数，scl频率 = clk频率 / (4*CLK_DIV) ，例如在本例中 clk 为 36.864MHz，CLK_DIV=10，则 SCL 频率为 36864/(4*10) = 922kHz 。注，AS5600 芯片要求 SCL 频率不超过 1MHz .SLAVE_ADDR ( 7'h36 ), // AS5600's I2C slave address .REGISTER_ADDR( 8'h0E ) // the register address to read -) as5600_read_i ( +) u_as5600_read ( .rstn ( rstn ), .clk ( clk ), .scl ( i2c_scl ), // I2C 接口： SCL @@ -77,7 +80,7 @@ adc_ad7928 #( .CH0 ( 3'd1 ), // 指示 CH0 对应 AD7928 的 通道1。（硬件上 A 相电流连接到 AD7928 的 通道1） .CH1 ( 3'd2 ), // 指示 CH1 对应 AD7928 的 通道2。（硬件上 B 相电流连接到 AD7928 的 通道2） .CH2 ( 3'd3 ) // 指示 CH2 对应 AD7928 的 通道3。（硬件上 C 相电流连接到 AD7928 的 通道3） -) adc_ad7928_i ( +) u_adc_ad7928 ( .rstn ( rstn ), .clk ( clk ), .spi_ss ( spi_ss ), // SPI 接口：SS @@ -104,12 +107,12 @@ foc_top #( .ANGLE_INV ( 1'b0 ), // 本例中，角度传感器没装反（A->B->C->A 的旋转方向与 φ 增大的方向相同），则该参数应设为 0 .POLE_PAIR ( 8'd7 ), // 本例使用的电机的极对数为 7 .MAX_AMP ( 9'd384 ), // 384 / 512 = 0.75。说明 SVPWM 的最大振幅 占 最大振幅极限的 75% - .SAMPLE_DELAY ( 9'd120 ), // 采样延时，取值范围0~511，考虑到3相的驱动 MOS 管从开始导通到电流稳定需要一定的时间，所以从3个下桥臂都导通，到 ADC 采样时刻之间需要一定的延时。该参数决定了该延时是多少个时钟周期，当延时结束时，该模块在 sn_adc 信号上产生一个高电平脉冲，指示外部 ADC “可以采样了” - .Kp ( 24'd32768 ), // 电流环 PID 控制算法的 P 参数 - .Ki ( 24'd2 ) // 电流环 PID 控制算法的 I 参数 -) foc_top_i ( + .SAMPLE_DELAY ( 9'd120 ) // 采样延时，取值范围0~511，考虑到3相的驱动 MOS 管从开始导通到电流稳定需要一定的时间，所以从3个下桥臂都导通，到 ADC 采样时刻之间需要一定的延时。该参数决定了该延时是多少个时钟周期，当延时结束时，该模块在 sn_adc 信号上产生一个高电平脉冲，指示外部 ADC “可以采样了” +) u_foc_top ( .rstn ( rstn ), .clk ( clk ), + .Kp ( 31'd300000 ), // 电流环 PID 控制算法的 P 参数 + .Ki ( 31'd30000 ), // 电流环 PID 控制算法的 I 参数 .phi ( phi ), // input : 角度传感器输入（机械角度，简记为φ），取值范围0~4095。0对应0°；1024对应90°；2048对应180°；3072对应270°。 .sn_adc ( sn_adc ), // output: 3相电流 ADC 采样时刻控制信号，当需要进行一次采样时，sn_adc 信号上产生一个时钟周期的高电平脉冲，指示ADC应该进行采样了。 .en_adc ( en_adc ), // input : 3相电流 ADC 采样结果有效信号，sn_adc 产生高电平脉冲后，外部ADC开始采样3相电流，在转换结束后，应在 en_adc 信号上产生一个周期的高电平脉冲，同时把ADC转换结果产生在 adc_a, adc_b, adc_c 信号上 @@ -155,7 +158,7 @@ always @ (posedge clk or negedge rstn) // 该 always 块令 iq_aim 交替地 // UART 发送器(监视器)，格式为：115200,8,n,1 uart_monitor #( .CLK_DIV ( 16'd320 ) // UART分频倍率，在本例中取320。因为时钟频率为 36.864MHz, 36.864MHz/320=115200 -) uart_monitor_i ( +) u_uart_monitor ( .rstn ( rstn ), .clk ( clk ), .i_en ( en_idq ), // input: 当 en_idq 上出现高电平脉冲时，启动 UART 发送 @@ -166,4 +169,5 @@ uart_monitor #( .o_uart_tx ( uart_tx ) // output: UART 发送信号 ); + endmodule diff --git a/RTL/i2c_register_read.sv b/RTL/i2c_register_read.v similarity index 85% rename from RTL/i2c_register_read.sv rename to RTL/i2c_register_read.v index d3242ae..66bfb72 100644 --- a/RTL/i2c_register_read.sv +++ b/RTL/i2c_register_read.v @@ -1,8 +1,10 @@ +//-------------------------------------------------------------------------------------------------------- // 模块: i2c_register_read // Type : synthesizable -// Standard: SystemVerilog 2005 (IEEE1800-2005) +// Standard: Verilog 2001 (IEEE1364-2001) // 功能 : I2C 读控制器 +//-------------------------------------------------------------------------------------------------------- module i2c_register_read #( parameter [15:0] CLK_DIV = 16'd16, @@ -34,30 +36,30 @@ reg [15:0] recv_shift; always @ (posedge clk or negedge rstn) if(~rstn) begin epoch <= 1'b0; - clkcnt <= '0; + clkcnt <= 0; end else begin if(clkcnt==CLK_DIV_PARSED) begin epoch <= 1'b1; - clkcnt <= '0; + clkcnt <= 0; end else begin epoch <= 1'b0; clkcnt <= clkcnt + 16'd1; end end -assign ready = (cnt=='0); +assign ready = (cnt == 8'd0); always @ (posedge clk or negedge rstn) if(~rstn) begin - {scl, sda_e, sda_o} <= '1; - cnt <= '0; - send_shift <= '0; - recv_shift <= '0; - regout <= '0; + {scl, sda_e, sda_o} <= 3'b111; + cnt <= 0; + send_shift <= 0; + recv_shift <= 0; + regout <= 0; done <= 1'b0; end else begin if(ready) begin - {scl, sda_e, sda_o} <= '1; + {scl, sda_e, sda_o} <= 3'b111; if(start) begin cnt <= 8'd1; end diff --git a/RTL/uart_monitor.sv b/RTL/uart_monitor.v similarity index 72% rename from RTL/uart_monitor.sv rename to RTL/uart_monitor.v index d2245d2..cba6807 100644 --- a/RTL/uart_monitor.sv +++ b/RTL/uart_monitor.v @@ -1,8 +1,10 @@ +//-------------------------------------------------------------------------------------------------------- // 模块：uart_monitor // Type : synthesizable -// Standard: SystemVerilog 2005 (IEEE1800-2005) -// 功能：UART发送器，格式为：115200,8,n,1，可以把 i_val0, i_val1, i_val2, i_val3 变成10进制格式，放在一行里，通过 UART 发送出去， +// Standard: Verilog 2001 (IEEE1364-2001) +// 功能：UART发送器，格式为：115200,8,n,1，可以把 i_val0, i_val1, i_val2, i_val3 变成10进制格式，放在一行里，通过 UART 发送出去 +//-------------------------------------------------------------------------------------------------------- module uart_monitor #( parameter [15:0] CLK_DIV = 217 // UART分频倍率，例如若时钟频率为 36.864MHz, CLK_DIV=320，则 UART 波特率为 36.864MHz/320=115200 @@ -19,7 +21,12 @@ module uart_monitor #( initial o_uart_tx = 1'b1; -enum logic [2:0] {IDLE, SELECT, WAIT, PARSING, SENDING} stat; +localparam [2:0] IDLE = 3'd0, + SELECT = 3'd1, + WAIT = 3'd2, + PARSING = 3'd3, + SENDING = 3'd4; +reg [2:0] stat; wire tx_rdy; reg tx_en; @@ -28,13 +35,13 @@ reg [7:0] tx_data; reg itoa_en; reg signed [15:0] itoa_val; reg itoa_oen; -reg [ 7:0] itoa_str [6]; +reg [ 7:0] itoa_str [0:5]; reg [ 2:0] vcnt; reg [ 2:0] cnt; reg [ 7:0] eov; -wire [ 7:0] s_str[8]; +wire [ 7:0] s_str[0:7]; assign s_str[0] = itoa_str[0]; assign s_str[1] = itoa_str[1]; @@ -45,9 +52,9 @@ assign s_str[5] = itoa_str[5]; assign s_str[6] = 8'h20; assign s_str[7] = eov; -always_comb begin +always @ (*) begin tx_en = 1'b0; - tx_data = '0; + tx_data = 0; if(stat==SENDING) begin tx_en = 1'b1; tx_data = s_str[cnt]; @@ -58,9 +65,9 @@ always @ (posedge clk or negedge rstn) if(~rstn) begin stat <= IDLE; itoa_en <= 1'b0; - itoa_val <= '0; - vcnt <= '0; - cnt <= '0; + itoa_val <= 0; + vcnt <= 0; + cnt <= 0; eov <= 8'h20; end else begin itoa_en <= 1'b0; @@ -102,11 +109,12 @@ always @ (posedge clk or negedge rstn) stat <= PARSING; PARSING: if(itoa_oen) stat <= SENDING; - SENDING: if(tx_rdy) begin - cnt <= cnt + 3'd1; - if(cnt==3'd7) - stat <= SELECT; - end + default: //SENDING: + if(tx_rdy) begin + cnt <= cnt + 3'd1; + if(cnt==3'd7) + stat <= SELECT; + end endcase end @@ -115,26 +123,32 @@ reg [ 2:0] itoa_cnt; reg itoa_sign; reg itoa_zero; reg [15:0] itoa_abs; +wire[15:0] itoa_rem_w = (itoa_abs % 16'd10); reg [ 3:0] itoa_rem; always @ (posedge clk or negedge rstn) if(~rstn) begin itoa_cnt <= 3'd0; - {itoa_sign, itoa_abs, itoa_zero, itoa_rem} <= '0; + {itoa_sign, itoa_abs, itoa_zero, itoa_rem} <= 0; itoa_oen <= 1'b0; - itoa_str <= '{6{'0}}; + itoa_str[0] <= 0; + itoa_str[1] <= 0; + itoa_str[2] <= 0; + itoa_str[3] <= 0; + itoa_str[4] <= 0; + itoa_str[5] <= 0; end else begin if(itoa_cnt==3'd0) begin if(itoa_en) itoa_cnt <= 3'd1; itoa_sign <= itoa_val[15]; - itoa_abs <= itoa_val[15] ? $unsigned(-itoa_val) : $unsigned(itoa_val); + itoa_abs <= itoa_val[15] ? $unsigned(-itoa_val) : $unsigned(itoa_val); end else begin - itoa_cnt <= itoa_cnt + 3'd1; - itoa_abs <= itoa_abs / 16'd10; - itoa_rem <= (4)'(itoa_abs % 16'd10); - itoa_zero <= itoa_abs==16'd0; + itoa_cnt <= (itoa_cnt + 3'd1); + itoa_abs <= (itoa_abs / 16'd10); + itoa_rem <= itoa_rem_w[3:0]; + itoa_zero <= (itoa_abs == 16'd0); if(itoa_cnt>3'd1) begin itoa_str[5] <= itoa_str[4]; itoa_str[4] <= itoa_str[3]; @@ -162,13 +176,13 @@ assign tx_rdy = (tx_cnt==4'd0); always @ (posedge clk or negedge rstn) if(~rstn) begin o_uart_tx <= 1'b1; - ccnt <= '0; - tx_cnt <= '0; - tx_shift <= '1; + ccnt <= 0; + tx_cnt <= 0; + tx_shift <= 12'hFFF; end else begin if(tx_cnt==4'd0) begin o_uart_tx <= 1'b1; - ccnt <= '0; + ccnt <= 0; if(tx_en) begin tx_cnt <= 4'd12; tx_shift <= {2'b10, tx_data[0], tx_data[1], tx_data[2], tx_data[3], tx_data[4], tx_data[5], tx_data[6], tx_data[7], 2'b11}; @@ -178,7 +192,7 @@ always @ (posedge clk or negedge rstn) if( ccnt + 16'd1 < CLK_DIV ) begin ccnt <= ccnt + 16'd1; end else begin - ccnt <= '0; + ccnt <= 0; tx_cnt <= tx_cnt - 4'd1; end end diff --git a/SIM/tb_clark_park_tr.sv b/SIM/tb_clark_park_tr.v similarity index 83% rename from SIM/tb_clark_park_tr.sv rename to SIM/tb_clark_park_tr.v index ca80f04..5e1355e 100644 --- a/SIM/tb_clark_park_tr.sv +++ b/SIM/tb_clark_park_tr.v @@ -2,12 +2,10 @@ //-------------------------------------------------------------------------------------------------------- // Module : tb_clark_park_tr // Type : simulation, top -// Standard: SystemVerilog 2005 (IEEE1800-2005) +// Standard: Verilog 2001 (IEEE1364-2001) // Function: testbench for sincos.sv , clark_tr.sv , park_tr.sv //-------------------------------------------------------------------------------------------------------- -`timescale 1ps/1ps - module tb_clark_park_tr(); @@ -19,8 +17,11 @@ reg clk = 1'b1; always #(13563) clk = ~clk; // 36.864MHz initial begin repeat(4) @(posedge clk); rstn<=1'b1; end -reg en_theta = '0; -reg [11:0] theta = '0; // 当前电角度（简记为 ψ）。取值范围0~4095。0对应0°；1024对应90°；2048对应180°；3072对应270°。 +reg en_theta = 0; +reg [11:0] theta = 0; // 当前电角度（简记为 ψ）。取值范围0~4095。0对应0°；1024对应90°；2048对应180°；3072对应270°。 + +localparam [11:0] PI_M2_D3 = (2*4096/3); // (2/3)*π +localparam [11:0] PI_D3 = ( 4096/3); // (1/3)*π wire en_iabc; wire signed [15:0] ia, ib, ic; @@ -33,27 +34,27 @@ wire signed [15:0] id; wire signed [15:0] iq; // 这里只是刚好借助了 sincos 模块来生成正弦波给 clark_tr ，只是为了仿真。在 FOC 设计中 sincos 模块并不是用来给 clark_tr 提供输入数据的，而是被 park_tr 调用。 -sincos sincos_i1 ( +sincos u1_sincos ( .rstn ( rstn ), .clk ( clk ), .i_en ( en_theta ), - .i_theta ( theta + (12)'(2*4096/3) ), // input : θ + (2/3)*π + .i_theta ( theta + PI_M2_D3 ), // input : θ + (2/3)*π .o_en ( en_iabc ), .o_sin ( ia ), // output: Ia, 振幅为±16384，初相位为 (4/3)*π 的正弦波 .o_cos ( ) ); -sincos sincos_i2 ( +sincos u2_sincos ( .rstn ( rstn ), .clk ( clk ), .i_en ( en_theta ), - .i_theta ( theta + (12)'( 4096/3) ), // input : θ + (1/3)*π + .i_theta ( theta + PI_D3 ), // input : θ + (1/3)*π .o_en ( ), .o_sin ( ib ), // output: Ib, 振幅为±16384，初相位为 (2/3)*π 的正弦波 .o_cos ( ) ); -sincos sincos_i3 ( +sincos u3_sincos ( .rstn ( rstn ), .clk ( clk ), .i_en ( en_theta ), @@ -64,7 +65,7 @@ sincos sincos_i3 ( ); // clark 变换 -clark_tr clark_tr_i( +clark_tr u_clark_tr ( .rstn ( rstn ), .clk ( clk ), .i_en ( en_iabc ), @@ -77,7 +78,7 @@ clark_tr clark_tr_i( ); // park 变换 -park_tr park_tr_i ( +park_tr u_park_tr ( .rstn ( rstn ), .clk ( clk ), .psi ( theta + 12'd512 ), // input : θ + (1/4)*π @@ -90,9 +91,11 @@ park_tr park_tr_i ( ); +integer i; + initial begin while(~rstn) @ (posedge clk); - for(int i=0; i<1000; i++) @ (posedge clk) begin + for (i=0; i<1000; i=i+1) @ (posedge clk) begin en_theta <= 1'b1; theta <= theta + 12'd10; @ (posedge clk); diff --git a/SIM/tb_clark_park_tr_run_iverilog.bat b/SIM/tb_clark_park_tr_run_iverilog.bat index 19145a7..6a16651 100644 --- a/SIM/tb_clark_park_tr_run_iverilog.bat +++ b/SIM/tb_clark_park_tr_run_iverilog.bat @@ -1,5 +1,5 @@ del sim.out dump.vcd -iverilog -g2005-sv -o sim.out tb_clark_park_tr.sv ../RTL/foc/sincos.sv ../RTL/foc/clark_tr.sv ../RTL/foc/park_tr.sv +iverilog -g2001 -o sim.out tb_clark_park_tr.v ../RTL/foc/sincos.v ../RTL/foc/clark_tr.v ../RTL/foc/park_tr.v vvp -n sim.out del sim.out pause \ No newline at end of file diff --git a/SIM/tb_svpwm.sv b/SIM/tb_svpwm.v similarity index 88% rename from SIM/tb_svpwm.sv rename to SIM/tb_svpwm.v index 2d87d38..9d56498 100644 --- a/SIM/tb_svpwm.sv +++ b/SIM/tb_svpwm.v @@ -2,17 +2,15 @@ //-------------------------------------------------------------------------------------------------------- // Module : tb_swpwm // Type : simulation, top -// Standard: SystemVerilog 2005 (IEEE1800-2005) +// Standard: Verilog 2001 (IEEE1364-2001) // Function: testbench for cartesian2polar.sv and swpwm.sv //-------------------------------------------------------------------------------------------------------- -`timescale 1ps/1ps - module tb_swpwm(); initial $dumpvars(1, tb_swpwm); -initial $dumpvars(1, svpwm_i); +initial $dumpvars(1, u_svpwm); reg rstn = 1'b0; @@ -21,7 +19,7 @@ always #(13563) clk = ~clk; // 36.864MHz initial begin repeat(4) @(posedge clk); rstn<=1'b1; end -reg [11:0] theta = '0; +reg [11:0] theta = 0; wire signed [15:0] x, y; @@ -30,8 +28,9 @@ wire [11:0] phi; wire pwm_en, pwm_a, pwm_b, pwm_c; + // 这里只是刚好借助了 sincos 模块来生成正弦波给 cartesian2polar ，只是为了仿真。在 FOC 设计中 sincos 模块并不是用来给 cartesian2polar 提供输入数据的，而是被 park_tr 调用。 -sincos sincos_i ( +sincos u_sincos ( .rstn ( rstn ), .clk ( clk ), .i_en ( 1'b1 ), @@ -41,7 +40,7 @@ sincos sincos_i ( .o_cos ( x ) // output : x, 振幅为 ±16384 的余弦波 ); -cartesian2polar cartesian2polar_i ( +cartesian2polar u_cartesian2polar ( .rstn ( rstn ), .clk ( clk ), .i_en ( 1'b1 ), @@ -52,7 +51,7 @@ cartesian2polar cartesian2polar_i ( .o_theta ( phi ) // output: φ, 应该是一个接近 θ 的角度值 ); -svpwm svpwm_i ( +svpwm u_svpwm ( .rstn ( rstn ), .clk ( clk ), .v_amp ( 9'd384 ), @@ -65,9 +64,11 @@ svpwm svpwm_i ( ); +integer i; + initial begin while(~rstn) @ (posedge clk); - for(int i=0; i<200; i++) begin + for(i=0; i<200; i=i+1) begin theta <= 25 * i; // 让 θ 递增 repeat(2048) @ (posedge clk); $display("%d/200", i); diff --git a/SIM/tb_svpwm_run_iverilog.bat b/SIM/tb_svpwm_run_iverilog.bat index 11e311e..b24f7be 100644 --- a/SIM/tb_svpwm_run_iverilog.bat +++ b/SIM/tb_svpwm_run_iverilog.bat @@ -1,5 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