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fix adc_ad7928.sv, make MISO sampled at SCK's falling edge

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WangXuan95 2021-09-07 16:41:40 +08:00
parent 8d1eba9415
commit 84188c6653
1 changed files with 1 additions and 1 deletions
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RTL/sensors/adc_ad7928.sv
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@ -121,7 +121,7 @@ always @ (posedge clk or negedge rstn)
end else begin
o_en_adc <= 1'b0;
if(cnt>=WAIT_CNT+8'd2 && cnt<WAIT_CNT+8'd32) begin
if(~spi_sck)
if(spi_sck)
data_in_latch <= {data_in_latch[10:0], spi_miso};
end else if(cnt==WAIT_CNT+8'd32) begin
if(idx=='0) begin