FPGA/FpOC
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WangXuan95 2022-04-01 17:10:25 +08:00
parent fca7ab3fba
commit 88f4b72b85
3 changed files with 3 additions and 51 deletions
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4
FPGA/foc.qsf
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@ -73,8 +73,9 @@ set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
set_global_assignment -name SYSTEMVERILOG_FILE ../RTL/top.sv
set_global_assignment -name SYSTEMVERILOG_FILE ../RTL/uart/uart_monitor.sv
set_global_assignment -name SYSTEMVERILOG_FILE ../RTL/uart_monitor.sv
set_global_assignment -name SYSTEMVERILOG_FILE ../RTL/sensors/as5600_read.sv
set_global_assignment -name SYSTEMVERILOG_FILE ../RTL/sensors/i2c_register_read.sv
set_global_assignment -name SYSTEMVERILOG_FILE ../RTL/sensors/adc_ad7928.sv
@ -86,4 +87,5 @@ set_global_assignment -name SYSTEMVERILOG_FILE ../RTL/foc/pi_controller.sv
set_global_assignment -name SYSTEMVERILOG_FILE ../RTL/foc/cartesian2polar.sv
set_global_assignment -name SYSTEMVERILOG_FILE ../RTL/foc/svpwm.sv
set_global_assignment -name SYSTEMVERILOG_FILE ../RTL/foc/hold_detect.sv
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

50
RTL/uart/uart_tx.sv
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@ -1,50 +0,0 @@
// 模块： uart_tx
// Type : synthesizable
// Standard: SystemVerilog 2005 (IEEE1800-2005)
module uart_tx #(
parameter [15:0] CLK_DIV = 217 // 25MHz / 217 = 115207 ~= 115200
)(
input wire rstn, // active-low reset
input wire clk,
input wire i_e,
output wire i_r,
input wire [ 7:0] i_d,
output reg tx
);
reg [15:0] ccnt;
reg [ 3:0] cnt;
reg [12:1] tx_shift;
assign i_r = (cnt==4'd0);
always @ (posedge clk or negedge rstn)
if(~rstn) begin
tx <= 1'b1;
ccnt <= '0;
cnt <= '0;
tx_shift <= '1;
end else begin
if(cnt==4'd0) begin
tx <= 1'b1;
ccnt <= '0;
if(i_e) begin
cnt <= 4'd12;
tx_shift <= {2'b10, i_d[0], i_d[1], i_d[2], i_d[3], i_d[4], i_d[5], i_d[6], i_d[7], 2'b11};
end
end else begin
tx <= tx_shift[cnt];
if( ccnt + 16'd1 < CLK_DIV ) begin
ccnt <= ccnt + 16'd1;
end else begin
ccnt <= '0;
cnt <= cnt - 4'd1;
end
end
end
endmodule

0
RTL/uart/uart_monitor.sv → RTL/uart_monitor.sv
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