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WangXuan95 2022-04-01 05:23:15 +08:00
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commit fca7ab3fba
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SIM/tb_svpwm.sv
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@ -3,7 +3,7 @@
// Module : tb_swpwm
// Type : simulation, top
// Standard: SystemVerilog 2005 (IEEE1800-2005)
// Function: testbench for swpwm.sv
// Function: testbench for cartesian2polar.sv and swpwm.sv
//--------------------------------------------------------------------------------------------------------
`timescale 1ps/1ps