diff --git a/SIM/tb_svpwm.sv b/SIM/tb_svpwm.sv
index 5e0ab79..2d87d38 100644
--- a/SIM/tb_svpwm.sv
+++ b/SIM/tb_svpwm.sv
@@ -3,7 +3,7 @@
 // Module  : tb_swpwm
 // Type    : simulation, top
 // Standard: SystemVerilog 2005 (IEEE1800-2005)
-// Function: testbench for swpwm.sv
+// Function: testbench for cartesian2polar.sv and swpwm.sv
 //--------------------------------------------------------------------------------------------------------
 
 `timescale 1ps/1ps