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8 Commits

Author SHA1 Message Date
WangXuan95
33eb8bb9e9 change to Verilog2001 2023-06-09 20:54:43 +08:00
WangXuan95
de26548026 update 2022-04-06 20:57:18 +08:00
WangXuan95
8fef02d6ce update 2022-04-05 10:34:50 +08:00
WangXuan95
f235eb2588 update 2022-04-04 18:42:13 +08:00
WangXuan95
88f4b72b85 update 2022-04-01 17:10:25 +08:00
WangXuan95
7c5ef655f0 update 2022-04-01 05:22:10 +08:00
WangXuan95
84188c6653 fix adc_ad7928.sv, make MISO sampled at SCK's falling edge 2021-09-07 16:41:40 +08:00
WangXuan95
728ba144e2 first commit 2021-02-22 14:17:59 +08:00