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68 lines
2.3 KiB
Verilog
68 lines
2.3 KiB
Verilog
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//--------------------------------------------------------------------------------------------------------
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// 模块： clark_tr
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// Type : synthesizable
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// Standard: Verilog 2001 (IEEE1364-2001)
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// 功能： clark 变换
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//--------------------------------------------------------------------------------------------------------
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module clark_tr(
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input wire rstn,
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input wire clk,
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input wire i_en,
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input wire signed [15:0] i_ia, i_ib, i_ic, // range -8191 ~ 8191
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output reg o_en,
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output reg signed [15:0] o_ialpha, o_ibeta
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);
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// registers for pipeline stage 1
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reg en_s1;
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reg signed [15:0] ax2_s1, bmc_s1, bpc_s1;
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// registers for pipeline stage 2
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reg en_s2;
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reg signed [15:0] ialpha_s2, i_beta1_s2, i_beta2_s2, i_beta3_s2;
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// pipeline stage 1
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always @ (posedge clk or negedge rstn)
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if(~rstn) begin
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{en_s1, ax2_s1, bmc_s1, bpc_s1} <= 0;
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end else begin
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en_s1 <= i_en;
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ax2_s1 <= i_ia << 1;
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bmc_s1 <= i_ib - i_ic;
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bpc_s1 <= i_ib + i_ic;
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end
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// pipeline stage 2
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always @ (posedge clk or negedge rstn)
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if(~rstn) begin
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{en_s2, ialpha_s2, i_beta1_s2, i_beta2_s2, i_beta3_s2} <= 0;
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end else begin
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en_s2 <= en_s1;
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ialpha_s2 <= ax2_s1 - bpc_s1;
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i_beta1_s2 <= bmc_s1 +
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$signed({{ 1{bmc_s1[15]}}, bmc_s1[15: 1]}) +
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$signed({{ 3{bmc_s1[15]}}, bmc_s1[15: 3]});
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i_beta2_s2 <= $signed({{ 4{bmc_s1[15]}}, bmc_s1[15: 4]}) +
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$signed({{ 5{bmc_s1[15]}}, bmc_s1[15: 5]}) +
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$signed({{ 7{bmc_s1[15]}}, bmc_s1[15: 7]});
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i_beta3_s2 <= $signed({{ 8{bmc_s1[15]}}, bmc_s1[15: 8]}) +
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$signed({{10{bmc_s1[15]}}, bmc_s1[15:10]}) +
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$signed({{11{bmc_s1[15]}}, bmc_s1[15:11]});
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end
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// pipeline stage output
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always @ (posedge clk or negedge rstn)
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if(~rstn) begin
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{o_en, o_ialpha, o_ibeta} <= 1'b0;
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end else begin
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o_en <= en_s2;
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if(en_s2) begin
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o_ialpha <= ialpha_s2;
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o_ibeta <= i_beta1_s2 + i_beta2_s2 + i_beta3_s2;
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end
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end
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endmodule
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