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109 lines
4.5 KiB
Verilog
109 lines
4.5 KiB
Verilog
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//--------------------------------------------------------------------------------------------------------
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// Module : tb_clark_park_tr
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// Type : simulation, top
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// Standard: Verilog 2001 (IEEE1364-2001)
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// Function: testbench for sincos.sv , clark_tr.sv , park_tr.sv
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//--------------------------------------------------------------------------------------------------------
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module tb_clark_park_tr();
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initial $dumpvars(1, tb_clark_park_tr);
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reg rstn = 1'b0;
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reg clk = 1'b1;
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always #(13563) clk = ~clk; // 36.864MHz
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initial begin repeat(4) @(posedge clk); rstn<=1'b1; end
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reg en_theta = 0;
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reg [11:0] theta = 0; // 当前电角度(简记为 ψ)。取值范围0~4095。0对应0°;1024对应90°;2048对应180°;3072对应270°。
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localparam [11:0] PI_M2_D3 = (2*4096/3); // (2/3)*π
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localparam [11:0] PI_D3 = ( 4096/3); // (1/3)*π
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wire en_iabc;
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wire signed [15:0] ia, ib, ic;
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wire en_ialphabeta;
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wire signed [15:0] ialpha, ibeta;
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wire en_idq;
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wire signed [15:0] id;
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wire signed [15:0] iq;
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// 这里只是刚好借助了 sincos 模块来生成正弦波给 clark_tr ,只是为了仿真。在 FOC 设计中 sincos 模块并不是用来给 clark_tr 提供输入数据的,而是被 park_tr 调用。
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sincos u1_sincos (
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.rstn ( rstn ),
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.clk ( clk ),
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.i_en ( en_theta ),
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.i_theta ( theta + PI_M2_D3 ), // input : θ + (2/3)*π
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.o_en ( en_iabc ),
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.o_sin ( ia ), // output: Ia, 振幅为±16384,初相位为 (4/3)*π 的正弦波
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.o_cos ( )
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);
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sincos u2_sincos (
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.rstn ( rstn ),
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.clk ( clk ),
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.i_en ( en_theta ),
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.i_theta ( theta + PI_D3 ), // input : θ + (1/3)*π
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.o_en ( ),
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.o_sin ( ib ), // output: Ib, 振幅为±16384,初相位为 (2/3)*π 的正弦波
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.o_cos ( )
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);
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sincos u3_sincos (
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.rstn ( rstn ),
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.clk ( clk ),
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.i_en ( en_theta ),
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.i_theta ( theta ), // input : θ
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.o_en ( ),
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.o_sin ( ic ), // output: Ic, 振幅为±16384,初相位为 0 的正弦波
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.o_cos ( )
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);
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// clark 变换
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clark_tr u_clark_tr (
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.rstn ( rstn ),
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.clk ( clk ),
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.i_en ( en_iabc ),
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.i_ia ( ia / 16'sd2 ), // input : 振幅为±8192,初相位为 (4/3)*π 的正弦波
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.i_ib ( ib / 16'sd2 ), // input : 振幅为±8192,初相位为 (2/3)*π 的正弦波
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.i_ic ( ic / 16'sd2 ), // input : 振幅为±8192,初相位为 0 的正弦波
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.o_en ( en_ialphabeta ),
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.o_ialpha ( ialpha ), // output: Iα ,应该为初相位为 (4/3)*π 的正弦波
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.o_ibeta ( ibeta ) // output: Iβ ,相位应该比 Iα 滞后 (1/2)*π ,也就是与 Iα 正交
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);
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// park 变换
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park_tr u_park_tr (
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.rstn ( rstn ),
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.clk ( clk ),
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.psi ( theta + 12'd512 ), // input : θ + (1/4)*π
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.i_en ( en_ialphabeta ),
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.i_ialpha ( ialpha ), // input : Iα
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.i_ibeta ( ibeta ), // input : Iβ
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.o_en ( en_idq ),
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.o_id ( id ), // output: Id ,应该变为一个定值,因为 park 变换把转子又变回定子了
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.o_iq ( iq ) // output: Iq ,应该变为一个定值,因为 park 变换把转子又变回定子了
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);
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integer i;
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initial begin
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while(~rstn) @ (posedge clk);
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for (i=0; i<1000; i=i+1) @ (posedge clk) begin
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en_theta <= 1'b1;
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theta <= theta + 12'd10;
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@ (posedge clk);
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en_theta <= 1'b0;
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repeat (9) @ (posedge clk);
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end
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$finish;
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end
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endmodule
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