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58 lines
1.5 KiB
Systemverilog
58 lines
1.5 KiB
Systemverilog
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// 模块： park_tr
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// Type : synthesizable
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// Standard: SystemVerilog 2005 (IEEE1800-2005)
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// 功能： park 变换器
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module park_tr(
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input wire rstn,
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input wire clk,
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input wire [11:0] psi,
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input wire i_en,
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input wire signed [15:0] i_ialpha, i_ibeta,
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output reg o_en,
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output reg signed [15:0] o_id, o_iq
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);
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reg signed [15:0] sin_psi, cos_psi; // -1~+1 is mapped to -16384~+16384
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reg en_s1;
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reg signed [31:0] alpha_cos, alpha_sin, beta_cos, beta_sin;
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wire signed[31:0] ide = alpha_cos + beta_sin;
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wire signed[31:0] iqe = beta_cos - alpha_sin;
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sincos sincos_i(
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.rstn ( rstn ),
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.clk ( clk ),
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.i_en ( 1'b1 ),
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.i_theta ( psi ),
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.o_en ( ),
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.o_sin ( sin_psi ),
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.o_cos ( cos_psi )
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);
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always @ (posedge clk or negedge rstn)
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if(~rstn) begin
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{en_s1, alpha_cos, alpha_sin, beta_cos, beta_sin} <= '0;
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end else begin
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en_s1 <= i_en;
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alpha_cos <= i_ialpha * cos_psi;
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alpha_sin <= i_ialpha * sin_psi;
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beta_cos <= i_ibeta * cos_psi;
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beta_sin <= i_ibeta * sin_psi;
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end
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always @ (posedge clk or negedge rstn)
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if(~rstn) begin
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{o_en, o_id, o_iq} <= '0;
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end else begin
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o_en <= en_s1;
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if(en_s1) begin
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o_id <= ide[31:16];
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o_iq <= iqe[31:16];
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end
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end
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endmodule
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