Hard-JPEG-LS/SIM/tb_jls_encoder_run_iverilog.bat

mirror of https://github.com/WangXuan95/Hard-JPEG-LS.git synced 2025-01-28 21:12:53 +08:00
del sim.out dump.vcd
iverilog  -g2001  -o sim.out  tb_jls_encoder.v  ../RTL/jls_encoder.v
vvp -n sim.out
del sim.out
pause
release v1.0 2023-03-03 20:48:37 +08:00			`del sim.out dump.vcd`
change to Verilog2001 2023-06-03 21:15:55 +08:00			`iverilog -g2001 -o sim.out tb_jls_encoder.v ../RTL/jls_encoder.v`
release v1.0 2023-03-03 20:48:37 +08:00			`vvp -n sim.out`
			`del sim.out`
			`pause`