FPGA/Hard-JPEG-LS
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change to Verilog2001

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WangXuan95 2023-06-03 21:18:57 +08:00
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commit fa4a5c93b2
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SIM/tb_jls_encoder.v
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@ -2,7 +2,7 @@
//--------------------------------------------------------------------------------------------------------
// Module : tb_jls_encoder
// Type : simulation, top
// Standard: SystemVerilog 2005 (IEEE1800-2005)
// Standard: Verilog 2001 (IEEE1364-2001)
// Function: testbench for jls_encoder,
// load some .pgm files (uncompressed image file), and push them to jls_encoder.
// get output JPEG-LS stream from jls_encoder, and write them to .jls files (JPEG-LS image file)