FPGA/Hard-PNG
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WangXuan95 2022-04-08 14:02:37 +08:00
parent 432e4d0440
commit d717e5481f
1 changed files with 6 additions and 6 deletions
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RTL/hard_png.sv
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@ -917,12 +917,12 @@ function automatic logic [7:0] paeth(input [7:0] a, input [7:0] b, input [7:0] c
pa = p > sa ? p - sa : sa - p; pa = p > sa ? p - sa : sa - p;
pb = p > sb ? p - sb : sb - p; pb = p > sb ? p - sb : sb - p;
pc = p > sc ? p - sc : sc - p; pc = p > sc ? p - sc : sc - p;
if (pa <= pb && pa <= pc) if (pa <= pb && pa <= pc)
return a; return a;
else if (pb <= pc) else if (pb <= pc)
return b; return b;
else else
return c; return c;
endfunction endfunction
reg nfirstrow = 1'b0; reg nfirstrow = 1'b0;