mirror of
https://github.com/WangXuan95/Hard-PNG.git
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96 lines
2.4 KiB
Systemverilog
96 lines
2.4 KiB
Systemverilog
`timescale 1 ns/1 ns
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`define PNG_FILE "E:/FPGAcommon/Hard-PNG/images/test14.png" // the png file to decode
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`define OUT_FILE "E:/FPGAcommon/Hard-PNG/result/test14.txt" // decode result txt file
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`define OUT_ENABLE 1 // whether to write result to the decode result txt file
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module tb_hard_png();
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integer fppng, fptxt;
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reg [7:0] rbyte;
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reg rst = 1'b1;
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reg clk = 1'b1;
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always #5 clk = ~clk;
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reg ivalid = 1'b0;
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wire iready;
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reg [ 7:0] ibyte = '0;
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wire newframe;
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wire [ 1:0] colortype;
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wire [13:0] width;
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wire [31:0] height;
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wire ovalid;
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wire [ 7:0] opixelr, opixelg, opixelb, opixela;
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initial begin
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fppng = $fopen(`PNG_FILE, "rb");
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if(`OUT_ENABLE) fptxt = $fopen(`OUT_FILE, "w");
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rbyte = $fgetc(fppng);
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@(posedge clk) rst = 1'b1;
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@(posedge clk) rst = 1'b0;
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@(posedge clk) #1
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ivalid <= 1'b0;
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ibyte <= 1'b0;
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while(!$feof(fppng)) begin
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@(posedge clk) #1
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ivalid <= 1'b1;
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ibyte <= rbyte;
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#1 if(iready) begin
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rbyte = $fgetc(fppng);
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//@(posedge clk) #1
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//ivalid <= 1'b0;
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//ibyte <= '0;
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end
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end
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@(posedge clk) #1
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ivalid <= 1'b0;
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ibyte <= 1'b0;
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$fclose(fppng);
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if(`OUT_ENABLE) $fclose(fptxt);
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end
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hard_png hard_png_i(
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.rst ( rst ),
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.clk ( clk ),
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// data input
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.ivalid ( ivalid ),
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.iready ( iready ),
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.ibyte ( ibyte ),
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// image size output
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.newframe ( newframe ),
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.colortype ( colortype ),
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.width ( width ),
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.height ( height ),
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// data output
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.ovalid ( ovalid ),
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.opixelr ( opixelr ),
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.opixelg ( opixelg ),
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.opixelb ( opixelb ),
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.opixela ( opixela )
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);
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reg [31:0] pixcnt = 0;
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always @ (posedge clk)
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if(newframe) begin
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pixcnt <= 0;
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if(`OUT_ENABLE)
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$fwrite(fptxt, "\nframe type:%1d width:%1d height:%1d\n", colortype, width, height);
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else
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$write("\nframe type:%1d width:%1d height:%1d\n", colortype, width, height);
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end else if(ovalid) begin
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pixcnt <= pixcnt + 1;
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if(`OUT_ENABLE) $fwrite(fptxt, "%02x%02x%02x%02x ", opixelr, opixelg, opixelb, opixela);
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end
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endmodule
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