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RSSI Update

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This commit is contained in:
JefferyLi0903 2022-06-29 13:15:53 +08:00
parent da2100d054
commit 0a7e321de1
44 changed files with 891586 additions and 877212 deletions
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71
constraints/FM_SOC.adc
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@ -1,32 +1,39 @@
set_pin_assignment { LED[0] } { LOCATION = B14; IOSTANDARD = LVCMOS33; }
set_pin_assignment { LED[1] } { LOCATION = B15; IOSTANDARD = LVCMOS33; }
set_pin_assignment { LED[2] } { LOCATION = B16; IOSTANDARD = LVCMOS33; }
set_pin_assignment { LED[3] } { LOCATION = C15; IOSTANDARD = LVCMOS33; }
set_pin_assignment { LED[4] } { LOCATION = C16; IOSTANDARD = LVCMOS33; }
set_pin_assignment { LED[5] } { LOCATION = E13; IOSTANDARD = LVCMOS33; }
set_pin_assignment { LED[6] } { LOCATION = E16; IOSTANDARD = LVCMOS33; }
set_pin_assignment { LED[7] } { LOCATION = F16; IOSTANDARD = LVCMOS33; }
set_pin_assignment { MSI_REFCLK } { LOCATION = R15; IOSTANDARD = LVCMOS33; }
set_pin_assignment { MSI_SCLK } { LOCATION = M9; IOSTANDARD = LVCMOS33; }
set_pin_assignment { MSI_SDATA } { LOCATION = N9; IOSTANDARD = LVCMOS33; }
set_pin_assignment { MSI_CS } { LOCATION = P9; IOSTANDARD = LVCMOS33; }
set_pin_assignment { audio_pwm } { LOCATION = N8; IOSTANDARD = LVCMOS33; }
set_pin_assignment { RSTn } { LOCATION = A14; IOSTANDARD = LVCMOS33; }
set_pin_assignment { RXD } { LOCATION = F12; IOSTANDARD = LVCMOS33; }
set_pin_assignment { SWCLK } { LOCATION = R2; IOSTANDARD = LVCMOS33; }
set_pin_assignment { SWDIO } { LOCATION = P2; IOSTANDARD = LVCMOS33; }
set_pin_assignment { TXD } { LOCATION = D12; IOSTANDARD = LVCMOS33; }
set_pin_assignment { clk } { LOCATION = R7; IOSTANDARD = LVCMOS33; }
set_pin_assignment { sel[0] } { LOCATION = C9; IOSTANDARD = LVCMOS33; }
set_pin_assignment { sel[1] } { LOCATION = B6; IOSTANDARD = LVCMOS33; }
set_pin_assignment { sel[2] } { LOCATION = A5; IOSTANDARD = LVCMOS33; }
set_pin_assignment { sel[3] } { LOCATION = A3; IOSTANDARD = LVCMOS33; }
set_pin_assignment { seg[0] } { LOCATION = A4; IOSTANDARD = LVCMOS33; }
set_pin_assignment { seg[1] } { LOCATION = A6; IOSTANDARD = LVCMOS33; }
set_pin_assignment { seg[2] } { LOCATION = B8; IOSTANDARD = LVCMOS33; }
set_pin_assignment { seg[3] } { LOCATION = E8; IOSTANDARD = LVCMOS33; }
set_pin_assignment { seg[4] } { LOCATION = A7; IOSTANDARD = LVCMOS33; }
set_pin_assignment { seg[5] } { LOCATION = B5; IOSTANDARD = LVCMOS33; }
set_pin_assignment { seg[6] } { LOCATION = A8; IOSTANDARD = LVCMOS33; }
set_pin_assignment { seg[7] } { LOCATION = C8; IOSTANDARD = LVCMOS33; }
set_pin_assignment { LED[0] } { LOCATION = B14; IOSTANDARD = LVCMOS33; }
set_pin_assignment { LED[1] } { LOCATION = B15; IOSTANDARD = LVCMOS33; }
set_pin_assignment { LED[2] } { LOCATION = B16; IOSTANDARD = LVCMOS33; }
set_pin_assignment { LED[3] } { LOCATION = C15; IOSTANDARD = LVCMOS33; }
set_pin_assignment { LED[4] } { LOCATION = C16; IOSTANDARD = LVCMOS33; }
set_pin_assignment { LED[5] } { LOCATION = E13; IOSTANDARD = LVCMOS33; }
set_pin_assignment { LED[6] } { LOCATION = E16; IOSTANDARD = LVCMOS33; }
set_pin_assignment { LED[7] } { LOCATION = F16; IOSTANDARD = LVCMOS33; }
set_pin_assignment { MSI_REFCLK } { LOCATION = R15; IOSTANDARD = LVCMOS33; }
set_pin_assignment { MSI_SCLK } { LOCATION = M9; IOSTANDARD = LVCMOS33; }
set_pin_assignment { MSI_SDATA } { LOCATION = N9; IOSTANDARD = LVCMOS33; }
set_pin_assignment { MSI_CS } { LOCATION = P9; IOSTANDARD = LVCMOS33; }
set_pin_assignment { audio_pwm } { LOCATION = N8; IOSTANDARD = LVCMOS33; }
set_pin_assignment { RSTn } { LOCATION = A14; IOSTANDARD = LVCMOS33; }
set_pin_assignment { RXD } { LOCATION = F12; IOSTANDARD = LVCMOS33; }
set_pin_assignment { SWCLK } { LOCATION = R2; IOSTANDARD = LVCMOS33; }
set_pin_assignment { SWDIO } { LOCATION = P2; IOSTANDARD = LVCMOS33; }
set_pin_assignment { TXD } { LOCATION = D12; IOSTANDARD = LVCMOS33; }
set_pin_assignment { clk } { LOCATION = R7; IOSTANDARD = LVCMOS33; }
set_pin_assignment { sel[0] } { LOCATION = C9; IOSTANDARD = LVCMOS33; }
set_pin_assignment { sel[1] } { LOCATION = B6; IOSTANDARD = LVCMOS33; }
set_pin_assignment { sel[2] } { LOCATION = A5; IOSTANDARD = LVCMOS33; }
set_pin_assignment { sel[3] } { LOCATION = A3; IOSTANDARD = LVCMOS33; }
set_pin_assignment { seg[0] } { LOCATION = A4; IOSTANDARD = LVCMOS33; }
set_pin_assignment { seg[1] } { LOCATION = A6; IOSTANDARD = LVCMOS33; }
set_pin_assignment { seg[2] } { LOCATION = B8; IOSTANDARD = LVCMOS33; }
set_pin_assignment { seg[3] } { LOCATION = E8; IOSTANDARD = LVCMOS33; }
set_pin_assignment { seg[4] } { LOCATION = A7; IOSTANDARD = LVCMOS33; }
set_pin_assignment { seg[5] } { LOCATION = B5; IOSTANDARD = LVCMOS33; }
set_pin_assignment { seg[6] } { LOCATION = A8; IOSTANDARD = LVCMOS33; }
set_pin_assignment { seg[7] } { LOCATION = C8; IOSTANDARD = LVCMOS33; }
set_pin_assignment { col[0] } { LOCATION = E11; IOSTANDARD = LVTTL33; }
set_pin_assignment { col[1] } { LOCATION = D11; IOSTANDARD = LVTTL33; }
set_pin_assignment { col[2] } { LOCATION = C11; IOSTANDARD = LVTTL33; }
set_pin_assignment { col[3] } { LOCATION = F10; IOSTANDARD = LVTTL33; }
set_pin_assignment { row[0] } { LOCATION = E10; IOSTANDARD = LVTTL33; }
set_pin_assignment { row[1] } { LOCATION = C10; IOSTANDARD = LVTTL33; }
set_pin_assignment { row[2] } { LOCATION = F9; IOSTANDARD = LVTTL33; }
set_pin_assignment { row[3] } { LOCATION = D9; IOSTANDARD = LVTTL33; }

4
keil/ExtDll.iex
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@ -1,2 +1,2 @@
[EXTDLL]
Count=0
[EXTDLL]
Count=0

1926
keil/Listings/MMC.map
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1433
keil/Listings/startup_cmsdk_cm0.lst
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keil/MMC.axf
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140
keil/MMC.build_log.htm
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@ -1,77 +1,63 @@
<html>
<body>
<pre>
<h1><EFBFBD>Vision Build Log</h1>
<h2>Tool Versions:</h2>
IDE-Version: <20><>Vision V5.36.0.0
Copyright (C) 2021 ARM Ltd and ARM Germany GmbH. All rights reserved.
License Information: Muhan JefferyLi, Fudan University, LIC=----
Tool Versions:
Toolchain: MDK-Lite Version: 5.36.0.0
Toolchain Path: D:\Keil_v5\ARM\ARMCC\Bin
C Compiler: Armcc.exe V5.06 update 7 (build 960)
Assembler: Armasm.exe V5.06 update 7 (build 960)
Linker/Locator: ArmLink.exe V5.06 update 7 (build 960)
Library Manager: ArmAr.exe V5.06 update 7 (build 960)
Hex Converter: FromElf.exe V5.06 update 7 (build 960)
CPU DLL: SARMCM3.DLL V5.36.0.0
Dialog DLL: DARMCM1.DLL V1.19.4.0
Target DLL: CMSIS_AGDI.dll V1.33.0.0
Dialog DLL: TARMCM1.DLL V1.14.4.0
<h2>Project:</h2>
D:\Documents\MMC\keil\MMC.uvprojx
Project File Date: 06/25/2022
<h2>Output:</h2>
*** Using Compiler 'V5.06 update 7 (build 960)', folder: 'D:\Keil_v5\ARM\ARMCC\Bin'
Rebuild target 'Target 1'
assembling startup_CMSDK_CM0.s...
compiling main.c...
..\src\code_def.h(72): warning: #1-D: last line of file ends without a newline
void RSSI_scan_cmd(void);
..\src\main.c(11): warning: #177-D: variable "string" was declared but never referenced
char string[32] = {0};
..\src\main.c(13): warning: #177-D: variable "MSI_SPI_Data" was declared but never referenced
unsigned int MSI_SPI_Data= 0;
..\src\main.c(14): warning: #177-D: variable "ChannelControlDisplay" was declared but never referenced
ChannelControlType ChannelControlDisplay;
..\src\main.c: 4 warnings, 0 errors
compiling auxiliary.c...
..\src\code_def.h(72): warning: #1-D: last line of file ends without a newline
void RSSI_scan_cmd(void);
..\src\auxiliary.c(9): warning: #550-D: variable "isNegative" was set but never used
int isNegative = 0;
..\src\auxiliary.c: 2 warnings, 0 errors
compiling code_def.c...
..\src\code_def.h(72): warning: #1-D: last line of file ends without a newline
void RSSI_scan_cmd(void);
..\src\code_def.c: 1 warning, 0 errors
compiling channelSelection_control.c...
..\src\code_def.h(72): warning: #1-D: last line of file ends without a newline
void RSSI_scan_cmd(void);
..\src\channelSelection_control.c: 1 warning, 0 errors
linking...
.\MMC.axf: Warning: L6305W: Image does not have an entry point. (Not specified or not set due to multiple choices.)
Program Size: Code=10492 RO-data=176 RW-data=40 ZI-data=10664
Finished: 0 information, 1 warning and 0 error messages.
After Build - User command #1: fromelf -cvf .\MMC.axf --vhx --32x1 -o MMC.hex
After Build - User command #2: fromelf -cvf .\MMC.axf -o MMC.txt
".\MMC.axf" - 0 Error(s), 9 Warning(s).
<h2>Software Packages used:</h2>
Package Vendor: Keil
http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.1.8.0.pack
Keil.V2M-MPS2_CMx_BSP.1.8.0
ARM V2M-MPS2 Board Support PACK for Cortex-M System Design Kit Devices
<h2>Collection of Component include folders:</h2>
C:\Users\JefferyLi\AppData\Local\Arm\Packs\Keil\V2M-MPS2_CMx_BSP\1.8.0\Device\CMSDK_CM0\Include
<h2>Collection of Component Files used:</h2>
Build Time Elapsed: 00:00:01
</pre>
</body>
</html>
<html>
<body>
<pre>
<h1><EFBFBD>Vision Build Log</h1>
<h2>Tool Versions:</h2>
IDE-Version: <20><>Vision V5.36.0.0
Copyright (C) 2021 ARM Ltd and ARM Germany GmbH. All rights reserved.
License Information: Muhan JefferyLi, Fudan University, LIC=----
Tool Versions:
Toolchain: MDK-Lite Version: 5.36.0.0
Toolchain Path: D:\Keil_v5\ARM\ARMCC\Bin
C Compiler: Armcc.exe V5.06 update 7 (build 960)
Assembler: Armasm.exe V5.06 update 7 (build 960)
Linker/Locator: ArmLink.exe V5.06 update 7 (build 960)
Library Manager: ArmAr.exe V5.06 update 7 (build 960)
Hex Converter: FromElf.exe V5.06 update 7 (build 960)
CPU DLL: SARMCM3.DLL V5.36.0.0
Dialog DLL: DARMCM1.DLL V1.19.4.0
Target DLL: CMSIS_AGDI.dll V1.33.0.0
Dialog DLL: TARMCM1.DLL V1.14.4.0
<h2>Project:</h2>
D:\Documents\MMC\keil\MMC.uvprojx
Project File Date: 06/29/2022
<h2>Output:</h2>
*** Using Compiler 'V5.06 update 7 (build 960)', folder: 'D:\Keil_v5\ARM\ARMCC\Bin'
Rebuild target 'Target 1'
assembling startup_CMSDK_CM0.s...
compiling main.c...
compiling auxiliary.c...
..\src\auxiliary.c(9): warning: #550-D: variable "isNegative" was set but never used
int isNegative = 0;
..\src\auxiliary.c: 1 warning, 0 errors
compiling channelSelection_control.c...
compiling code_def.c...
..\src\code_def.c(228): warning: #177-D: variable "j" was declared but never referenced
int j;
..\src\code_def.c: 1 warning, 0 errors
linking...
.\MMC.axf: Warning: L6305W: Image does not have an entry point. (Not specified or not set due to multiple choices.)
Program Size: Code=12384 RO-data=240 RW-data=40 ZI-data=10920
Finished: 0 information, 1 warning and 0 error messages.
After Build - User command #1: fromelf -cvf .\MMC.axf --vhx --32x1 -o MMC.hex
After Build - User command #2: fromelf -cvf .\MMC.axf -o MMC.txt
".\MMC.axf" - 0 Error(s), 3 Warning(s).
<h2>Software Packages used:</h2>
Package Vendor: Keil
http://www.keil.com/pack/Keil.V2M-MPS2_CMx_BSP.1.8.0.pack
Keil.V2M-MPS2_CMx_BSP.1.8.0
ARM V2M-MPS2 Board Support PACK for Cortex-M System Design Kit Devices
<h2>Collection of Component include folders:</h2>
C:\Users\JefferyLi\AppData\Local\Arm\Packs\Keil\V2M-MPS2_CMx_BSP\1.8.0\Device\CMSDK_CM0\Include
<h2>Collection of Component Files used:</h2>
Build Time Elapsed: 00:00:01
</pre>
</body>
</html>

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keil/MMC.hex
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keil/MMC.htm
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18
keil/MMC.lnp
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@ -1,10 +1,10 @@
--cpu Cortex-M0
".\auxiliary.o"
".\code_def.o"
".\main.o"
".\startup_cmsdk_cm0.o"
".\channelselection_control.o"
--strict --scatter ".\MMC.sct"
--summary_stderr --info summarysizes --map --load_addr_map_info --xref --callgraph --symbols
--info sizes --info totals --info unused --info veneers
--cpu Cortex-M0
".\auxiliary.o"
".\code_def.o"
".\main.o"
".\startup_cmsdk_cm0.o"
".\channelselection_control.o"
--strict --scatter ".\MMC.sct"
--summary_stderr --info summarysizes --map --load_addr_map_info --xref --callgraph --symbols
--info sizes --info totals --info unused --info veneers
--list ".\Listings\MMC.map" -o .\MMC.axf

32
keil/MMC.sct
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@ -1,16 +1,16 @@
; *************************************************************
; *** Scatter-Loading Description File generated by uVision ***
; *************************************************************
LR_IROM1 0x00000000 0x00010000 { ; load region size_region
ER_IROM1 0x00000000 0x00010000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
.ANY (+XO)
}
RW_IRAM1 0x20000000 0x00010000 { ; RW data
.ANY (+RW +ZI)
}
}
; *************************************************************
; *** Scatter-Loading Description File generated by uVision ***
; *************************************************************
LR_IROM1 0x00000000 0x00010000 { ; load region size_region
ER_IROM1 0x00000000 0x00010000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
.ANY (+XO)
}
RW_IRAM1 0x20000000 0x00010000 { ; RW data
.ANY (+RW +ZI)
}
}

10961
keil/MMC.txt
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92
keil/MMC.uvguix.JefferyLi
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4
keil/MMC.uvoptx
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@ -173,12 +173,12 @@
<Ww>
<count>4</count>
<WinNumber>1</WinNumber>
<ItemText>i </ItemText>
<ItemText>rssilist[rssi_index].RSSI</ItemText>
</Ww>
<Ww>
<count>5</count>
<WinNumber>1</WinNumber>
<ItemText>rssilist[rssi_index].RSSI</ItemText>
<ItemText>channelcontrollist</ItemText>
</Ww>
</WatchWindow1>
<Tracepoint>

18
keil/MMC_Target 1.dep
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@ -1,21 +1,21 @@
Dependencies for Project 'MMC', Target 'Target 1': (DO NOT MODIFY !)
CompilerVersion: 5060960::V5.06 update 7 (build 960)::.\ARMCC
F (..\src\auxiliary.c)(0x6288D9F3)(-c --cpu Cortex-M0 -D__EVAL -g -O0 --apcs=interwork --split_sections -IC:\Users\JefferyLi\AppData\Local\Arm\Packs\Keil\V2M-MPS2_CMx_BSP\1.8.0\Device\CMSDK_CM0\Include -D__UVISION_VERSION="536" -DCMSDK_CM0 -o .\auxiliary.o --omf_browse .\auxiliary.crf --depend .\auxiliary.d)
I (..\src\code_def.h)(0x62B7A918)
I (..\src\code_def.h)(0x62BB11B0)
I (D:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x6025237E)
I (D:\Keil_v5\ARM\ARMCC\include\string.h)(0x6025237E)
F (..\src\code_def.c)(0x62B7F1D8)(-c --cpu Cortex-M0 -D__EVAL -g -O0 --apcs=interwork --split_sections -IC:\Users\JefferyLi\AppData\Local\Arm\Packs\Keil\V2M-MPS2_CMx_BSP\1.8.0\Device\CMSDK_CM0\Include -D__UVISION_VERSION="536" -DCMSDK_CM0 -o .\code_def.o --omf_browse .\code_def.crf --depend .\code_def.d)
I (..\src\code_def.h)(0x62B7A918)
F (..\src\code_def.c)(0x62BBD34E)(-c --cpu Cortex-M0 -D__EVAL -g -O0 --apcs=interwork --split_sections -IC:\Users\JefferyLi\AppData\Local\Arm\Packs\Keil\V2M-MPS2_CMx_BSP\1.8.0\Device\CMSDK_CM0\Include -D__UVISION_VERSION="536" -DCMSDK_CM0 -o .\code_def.o --omf_browse .\code_def.crf --depend .\code_def.d)
I (..\src\code_def.h)(0x62BB11B0)
I (D:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x6025237E)
I (D:\Keil_v5\ARM\ARMCC\include\string.h)(0x6025237E)
I (D:\Keil_v5\ARM\ARMCC\include\math.h)(0x60252378)
F (..\src\code_def.h)(0x62B7A918)()
F (..\src\main.c)(0x62B7DAD7)(-c --cpu Cortex-M0 -D__EVAL -g -O0 --apcs=interwork --split_sections -IC:\Users\JefferyLi\AppData\Local\Arm\Packs\Keil\V2M-MPS2_CMx_BSP\1.8.0\Device\CMSDK_CM0\Include -D__UVISION_VERSION="536" -DCMSDK_CM0 -o .\main.o --omf_browse .\main.crf --depend .\main.d)
I (..\src\code_def.h)(0x62B7A918)
F (..\src\code_def.h)(0x62BB11B0)()
F (..\src\main.c)(0x62B85C66)(-c --cpu Cortex-M0 -D__EVAL -g -O0 --apcs=interwork --split_sections -IC:\Users\JefferyLi\AppData\Local\Arm\Packs\Keil\V2M-MPS2_CMx_BSP\1.8.0\Device\CMSDK_CM0\Include -D__UVISION_VERSION="536" -DCMSDK_CM0 -o .\main.o --omf_browse .\main.crf --depend .\main.d)
I (..\src\code_def.h)(0x62BB11B0)
I (D:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x6025237E)
I (D:\Keil_v5\ARM\ARMCC\include\string.h)(0x6025237E)
F (..\src\startup_CMSDK_CM0.s)(0x62B69773)(--cpu Cortex-M0 --pd "__EVAL SETA 1" -g --apcs=interwork -IC:\Users\JefferyLi\AppData\Local\Arm\Packs\Keil\V2M-MPS2_CMx_BSP\1.8.0\Device\CMSDK_CM0\Include --pd "__UVISION_VERSION SETA 536" --pd "CMSDK_CM0 SETA 1" --list .\listings\startup_cmsdk_cm0.lst --xref -o .\startup_cmsdk_cm0.o --depend .\startup_cmsdk_cm0.d)
F (..\src\channelSelection_control.c)(0x62B7014F)(-c --cpu Cortex-M0 -D__EVAL -g -O0 --apcs=interwork --split_sections -IC:\Users\JefferyLi\AppData\Local\Arm\Packs\Keil\V2M-MPS2_CMx_BSP\1.8.0\Device\CMSDK_CM0\Include -D__UVISION_VERSION="536" -DCMSDK_CM0 -o .\channelselection_control.o --omf_browse .\channelselection_control.crf --depend .\channelselection_control.d)
I (..\src\code_def.h)(0x62B7A918)
F (..\src\startup_CMSDK_CM0.s)(0x62B85B7A)(--cpu Cortex-M0 --pd "__EVAL SETA 1" -g --apcs=interwork -IC:\Users\JefferyLi\AppData\Local\Arm\Packs\Keil\V2M-MPS2_CMx_BSP\1.8.0\Device\CMSDK_CM0\Include --pd "__UVISION_VERSION SETA 536" --pd "CMSDK_CM0 SETA 1" --list .\listings\startup_cmsdk_cm0.lst --xref -o .\startup_cmsdk_cm0.o --depend .\startup_cmsdk_cm0.d)
F (..\src\channelSelection_control.c)(0x62BBB5B7)(-c --cpu Cortex-M0 -D__EVAL -g -O0 --apcs=interwork --split_sections -IC:\Users\JefferyLi\AppData\Local\Arm\Packs\Keil\V2M-MPS2_CMx_BSP\1.8.0\Device\CMSDK_CM0\Include -D__UVISION_VERSION="536" -DCMSDK_CM0 -o .\channelselection_control.o --omf_browse .\channelselection_control.crf --depend .\channelselection_control.d)
I (..\src\code_def.h)(0x62BB11B0)
I (D:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x6025237E)
I (D:\Keil_v5\ARM\ARMCC\include\string.h)(0x6025237E)

16
keil/MMC_sct.Bak Normal file
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@ -0,0 +1,16 @@
; *************************************************************
; *** Scatter-Loading Description File generated by uVision ***
; *************************************************************
LR_IROM1 0x00000000 0x00100000 { ; load region size_region
ER_IROM1 0x00000000 0x00100000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
.ANY (+XO)
}
RW_IRAM1 0x20000000 0x00100000 { ; RW data
.ANY (+RW +ZI)
}
}

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keil/auxiliary.crf
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keil/channelselection_control.crf
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keil/code_def.crf
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keil/main.crf
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project/MMC.al
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<?xml version="1.0" encoding="UTF-8"?>
<Project Version="1" Path="D:/Documents/MMC/project">
<Project_Created_Time>2022-06-25 10:35:14</Project_Created_Time>
<TD_Version>5.0.43066</TD_Version>
<UCode>00011001</UCode>
<Name>MMC</Name>
<HardWare>
<Family>EG4</Family>
<Device>EG4S20BG256</Device>
</HardWare>
<Source_Files>
<Verilog>
<File Path="al_ip/PLL_Demodulation.v">
<FileInfo>
<Attr Name="UsedInSyn" Val="true"/>
<Attr Name="UsedInP&R" Val="true"/>
<Attr Name="BelongTo" Val="design_1"/>
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<MODULE>CortexM0_SoC</MODULE>
<CREATEINDEX></CREATEINDEX>
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<Property>
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</RtlProperty>
<GateProperty>
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<RouteProperty>
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<TimingProperty>
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<Device_Settings>
</Device_Settings>
<Configurations>
</Configurations>
<Project_Settings>
<Step_Last_Change>2022-06-26 14:36:01.445</Step_Last_Change>
<Current_Step>60</Current_Step>
<Step_Status>true</Step_Status>
</Project_Settings>
</Project>
<?xml version="1.0" encoding="UTF-8"?>
<Project Version="1" Path="D:/Documents/MMC/project">
<Project_Created_Time>2022-06-25 10:35:14</Project_Created_Time>
<TD_Version>5.0.43066</TD_Version>
<UCode>11111100</UCode>
<Name>MMC</Name>
<HardWare>
<Family>EG4</Family>
<Device>EG4S20BG256</Device>
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</File>
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</FileSets>
<TOP_MODULE>
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<MODULE>CortexM0_SoC</MODULE>
<CREATEINDEX></CREATEINDEX>
</TOP_MODULE>
<Property>
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<rtl_sim_model>on</rtl_sim_model>
</RtlProperty>
<GateProperty>
<gate_sim_model>on</gate_sim_model>
</GateProperty>
<RouteProperty>
<phy_sim_model>on</phy_sim_model>
</RouteProperty>
<TimingProperty>
<sdf>on</sdf>
</TimingProperty>
<SimProperty>
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</SimProperty>
</Property>
<Device_Settings>
</Device_Settings>
<Configurations>
</Configurations>
<Project_Settings>
<Step_Last_Change>2022-06-29 12:53:13.536</Step_Last_Change>
<Current_Step>60</Current_Step>
<Step_Status>true</Step_Status>
</Project_Settings>
</Project>

BIN
project/MMC.bit
View File

Binary file not shown.

88
project/MMC_gate.area
View File

@ -1,44 +1,44 @@
standard
***Report Model: CortexM0_SoC***
IO Statistics
#IO 31
#input 4
#output 26
#inout 1
LUT Statistics
#Total_luts 9608
#lut4 7075
#lut5 1631
#lut6 0
#lut5_mx41 0
#lut4_alu1b 902
Utilization Statistics
#lut 9608 out of 19600 49.02%
#reg 1921 out of 19600 9.80%
#le 0
#dsp 26 out of 29 89.66%
#bram 32 out of 64 50.00%
#bram9k 32
#fifo9k 0
#bram32k 0 out of 16 0.00%
#dram 1040
#adc 1 out of 1 100.00%
#pad 31 out of 186 16.67%
#ireg 0
#oreg 0
#treg 0
#pll 2 out of 4 50.00%
Report Hierarchy Area:
+------------------------------------------------------------------------------+
|Instance |Module |lut |ripple |seq |bram |dsp |
+------------------------------------------------------------------------------+
|top |CortexM0_SoC |8706 |902 |1921 |32 |26 |
| FM_Display |FM_Display |180 |90 |81 |0 |0 |
| FM_HW |FM_HW |3473 |595 |391 |0 |23 |
| FM_Demodulation |FM_Demodulation |12 |422 |268 |0 |22 |
| u_logic |cortexm0ds_logic |4719 |173 |1301 |0 |3 |
+------------------------------------------------------------------------------+
standard
***Report Model: CortexM0_SoC***
IO Statistics
#IO 39
#input 8
#output 30
#inout 1
LUT Statistics
#Total_luts 9828
#lut4 7291
#lut5 1581
#lut6 0
#lut5_mx41 0
#lut4_alu1b 956
Utilization Statistics
#lut 9828 out of 19600 50.14%
#reg 2074 out of 19600 10.58%
#le 0
#dsp 26 out of 29 89.66%
#bram 32 out of 64 50.00%
#bram9k 32
#fifo9k 0
#bram32k 0 out of 16 0.00%
#dram 1040
#adc 1 out of 1 100.00%
#pad 39 out of 186 20.97%
#ireg 0
#oreg 0
#treg 0
#pll 2 out of 4 50.00%
Report Hierarchy Area:
+------------------------------------------------------------------------------+
|Instance |Module |lut |ripple |seq |bram |dsp |
+------------------------------------------------------------------------------+
|top |CortexM0_SoC |8872 |956 |2074 |32 |26 |
| FM_Display |FM_Display |180 |90 |81 |0 |0 |
| FM_HW |FM_HW |3473 |595 |391 |0 |23 |
| FM_Demodulation |FM_Demodulation |12 |422 |268 |0 |22 |
| u_logic |cortexm0ds_logic |4791 |173 |1317 |0 |3 |
+------------------------------------------------------------------------------+

69
project/MMC_inst.bid
View File

@ -1,6 +1,6 @@
<?xml version="1.0" encoding="UTF-8"?>
<All_Bram_Infos>
<Ucode>00011001</Ucode>
<Ucode>11111100</Ucode>
<AL_PHY_BRAM>
<INST_1>
<rid>0X0004</rid>
@ -1002,11 +1002,11 @@
<is_debuggable>y</is_debuggable>
<is_initialize>n</is_initialize>
<model_type>AL_PHY_BRAM32K</model_type>
<name>auto_chipwatcher_0_logicbram_4096x53_sub_000000_000</name>
<name>auto_chipwatcher_0_logicbram_4096x48_sub_000000_000</name>
<width_a>8</width_a>
<width_b>8</width_b>
<logic_name>auto_chipwatcher_0_logicbram</logic_name>
<logic_width>53</logic_width>
<logic_width>48</logic_width>
<logic_depth>4096</logic_depth>
<sub_bid_info>
<address_offset>0</address_offset>
@ -1014,7 +1014,7 @@
<depth>4096</depth>
<width>8</width>
<num_section>1</num_section>
<section_size>53</section_size>
<section_size>48</section_size>
<width_per_section>8</width_per_section>
<bytes_in_per_section>1</bytes_in_per_section>
<working_mode>
@ -1033,11 +1033,11 @@
<is_debuggable>y</is_debuggable>
<is_initialize>n</is_initialize>
<model_type>AL_PHY_BRAM32K</model_type>
<name>auto_chipwatcher_0_logicbram_4096x53_sub_000000_008</name>
<name>auto_chipwatcher_0_logicbram_4096x48_sub_000000_008</name>
<width_a>8</width_a>
<width_b>8</width_b>
<logic_name>auto_chipwatcher_0_logicbram</logic_name>
<logic_width>53</logic_width>
<logic_width>48</logic_width>
<logic_depth>4096</logic_depth>
<sub_bid_info>
<address_offset>0</address_offset>
@ -1045,7 +1045,7 @@
<depth>4096</depth>
<width>8</width>
<num_section>1</num_section>
<section_size>53</section_size>
<section_size>48</section_size>
<width_per_section>8</width_per_section>
<bytes_in_per_section>1</bytes_in_per_section>
<working_mode>
@ -1064,11 +1064,11 @@
<is_debuggable>y</is_debuggable>
<is_initialize>n</is_initialize>
<model_type>AL_PHY_BRAM32K</model_type>
<name>auto_chipwatcher_0_logicbram_4096x53_sub_000000_016</name>
<name>auto_chipwatcher_0_logicbram_4096x48_sub_000000_016</name>
<width_a>8</width_a>
<width_b>8</width_b>
<logic_name>auto_chipwatcher_0_logicbram</logic_name>
<logic_width>53</logic_width>
<logic_width>48</logic_width>
<logic_depth>4096</logic_depth>
<sub_bid_info>
<address_offset>0</address_offset>
@ -1076,7 +1076,7 @@
<depth>4096</depth>
<width>8</width>
<num_section>1</num_section>
<section_size>53</section_size>
<section_size>48</section_size>
<width_per_section>8</width_per_section>
<bytes_in_per_section>1</bytes_in_per_section>
<working_mode>
@ -1095,11 +1095,11 @@
<is_debuggable>y</is_debuggable>
<is_initialize>n</is_initialize>
<model_type>AL_PHY_BRAM32K</model_type>
<name>auto_chipwatcher_0_logicbram_4096x53_sub_000000_024</name>
<name>auto_chipwatcher_0_logicbram_4096x48_sub_000000_024</name>
<width_a>8</width_a>
<width_b>8</width_b>
<logic_name>auto_chipwatcher_0_logicbram</logic_name>
<logic_width>53</logic_width>
<logic_width>48</logic_width>
<logic_depth>4096</logic_depth>
<sub_bid_info>
<address_offset>0</address_offset>
@ -1107,7 +1107,7 @@
<depth>4096</depth>
<width>8</width>
<num_section>1</num_section>
<section_size>53</section_size>
<section_size>48</section_size>
<width_per_section>8</width_per_section>
<bytes_in_per_section>1</bytes_in_per_section>
<working_mode>
@ -1126,11 +1126,11 @@
<is_debuggable>y</is_debuggable>
<is_initialize>n</is_initialize>
<model_type>AL_PHY_BRAM32K</model_type>
<name>auto_chipwatcher_0_logicbram_4096x53_sub_000000_032</name>
<name>auto_chipwatcher_0_logicbram_4096x48_sub_000000_032</name>
<width_a>8</width_a>
<width_b>8</width_b>
<logic_name>auto_chipwatcher_0_logicbram</logic_name>
<logic_width>53</logic_width>
<logic_width>48</logic_width>
<logic_depth>4096</logic_depth>
<sub_bid_info>
<address_offset>0</address_offset>
@ -1138,7 +1138,7 @@
<depth>4096</depth>
<width>8</width>
<num_section>1</num_section>
<section_size>53</section_size>
<section_size>48</section_size>
<width_per_section>8</width_per_section>
<bytes_in_per_section>1</bytes_in_per_section>
<working_mode>
@ -1157,11 +1157,11 @@
<is_debuggable>y</is_debuggable>
<is_initialize>n</is_initialize>
<model_type>AL_PHY_BRAM32K</model_type>
<name>auto_chipwatcher_0_logicbram_4096x53_sub_000000_040</name>
<name>auto_chipwatcher_0_logicbram_4096x48_sub_000000_040</name>
<width_a>8</width_a>
<width_b>8</width_b>
<logic_name>auto_chipwatcher_0_logicbram</logic_name>
<logic_width>53</logic_width>
<logic_width>48</logic_width>
<logic_depth>4096</logic_depth>
<sub_bid_info>
<address_offset>0</address_offset>
@ -1169,7 +1169,7 @@
<depth>4096</depth>
<width>8</width>
<num_section>1</num_section>
<section_size>53</section_size>
<section_size>48</section_size>
<width_per_section>8</width_per_section>
<bytes_in_per_section>1</bytes_in_per_section>
<working_mode>
@ -1182,36 +1182,5 @@
</working_mode>
</sub_bid_info>
</INST_6>
<INST_7>
<rid>0X003C</rid>
<wid>0X003C</wid>
<is_debuggable>y</is_debuggable>
<is_initialize>n</is_initialize>
<model_type>AL_PHY_BRAM32K</model_type>
<name>auto_chipwatcher_0_logicbram_4096x53_sub_000000_048</name>
<width_a>8</width_a>
<width_b>8</width_b>
<logic_name>auto_chipwatcher_0_logicbram</logic_name>
<logic_width>53</logic_width>
<logic_depth>4096</logic_depth>
<sub_bid_info>
<address_offset>0</address_offset>
<data_offset>48</data_offset>
<depth>4096</depth>
<width>5</width>
<num_section>1</num_section>
<section_size>53</section_size>
<width_per_section>5</width_per_section>
<bytes_in_per_section>1</bytes_in_per_section>
<working_mode>
<address_step>1</address_step>
<depth>4096</depth>
<mode_type>113</mode_type>
<width>8</width>
<num_byte>1</num_byte>
<ecc>0</ecc>
</working_mode>
</sub_bid_info>
</INST_7>
</AL_PHY_BRAM32K>
</All_Bram_Infos>

180
project/MMC_phy.area
View File

@ -1,86 +1,94 @@
standard
***Report Model: CortexM0_SoC***
IO Statistics
#IO 31
#input 4
#output 26
#inout 1
Utilization Statistics
#lut 17306 out of 19600 88.30%
#reg 2390 out of 19600 12.19%
#le 17629
#lut only 15239 out of 17629 86.44%
#reg only 323 out of 17629 1.83%
#lut&reg 2067 out of 17629 11.72%
#dsp 26 out of 29 89.66%
#bram 32 out of 64 50.00%
#bram9k 32
#fifo9k 0
#bram32k 7 out of 16 43.75%
#adc 1 out of 1 100.00%
#pad 31 out of 186 16.67%
#ireg 0
#oreg 0
#treg 0
#pll 2 out of 4 50.00%
#gclk 13 out of 16 81.25%
Detailed IO Report
Name Direction Location IOStandard DriveStrength PullType PackReg
RSTn INPUT A14 LVCMOS33 N/A PULLUP NONE
RXD INPUT F12 LVCMOS33 N/A PULLUP NONE
SWCLK INPUT R2 LVCMOS33 N/A PULLUP NONE
clk INPUT R7 LVCMOS33 N/A PULLUP NONE
LED[7] OUTPUT F16 LVCMOS33 8 NONE NONE
LED[6] OUTPUT E16 LVCMOS33 8 NONE NONE
LED[5] OUTPUT E13 LVCMOS33 8 NONE NONE
LED[4] OUTPUT C16 LVCMOS33 8 NONE NONE
LED[3] OUTPUT C15 LVCMOS33 8 NONE NONE
LED[2] OUTPUT B16 LVCMOS33 8 NONE NONE
LED[1] OUTPUT B15 LVCMOS33 8 NONE NONE
LED[0] OUTPUT B14 LVCMOS33 8 NONE NONE
MSI_CS OUTPUT P9 LVCMOS33 8 NONE NONE
MSI_REFCLK OUTPUT R15 LVCMOS33 8 NONE NONE
MSI_SCLK OUTPUT M9 LVCMOS33 8 NONE NONE
MSI_SDATA OUTPUT N9 LVCMOS33 8 NONE NONE
TXD OUTPUT D12 LVCMOS33 8 NONE NONE
audio_pwm OUTPUT N8 LVCMOS33 8 NONE NONE
seg[7] OUTPUT C8 LVCMOS33 8 NONE NONE
seg[6] OUTPUT A8 LVCMOS33 8 NONE NONE
seg[5] OUTPUT B5 LVCMOS33 8 NONE NONE
seg[4] OUTPUT A7 LVCMOS33 8 NONE NONE
seg[3] OUTPUT E8 LVCMOS33 8 NONE NONE
seg[2] OUTPUT B8 LVCMOS33 8 NONE NONE
seg[1] OUTPUT A6 LVCMOS33 8 NONE NONE
seg[0] OUTPUT A4 LVCMOS33 8 NONE NONE
sel[3] OUTPUT A3 LVCMOS33 8 NONE NONE
sel[2] OUTPUT A5 LVCMOS33 8 NONE NONE
sel[1] OUTPUT B6 LVCMOS33 8 NONE NONE
sel[0] OUTPUT C9 LVCMOS33 8 NONE NONE
SWDIO INOUT P2 LVCMOS33 8 PULLUP NONE
Report Hierarchy Area:
+----------------------------------------------------------------------+
|Instance |Module |le |lut |ripple |seq |bram |dsp |
+----------------------------------------------------------------------+
|top |CortexM0_SoC |17629 |16853 |453 |2390 |39 |26 |
+----------------------------------------------------------------------+
DataNet Average Fanout:
Index Fanout Nets
#1 1 15409
#2 2 10176
#3 3 643
#4 4 487
#5 5-10 684
#6 11-50 472
#7 51-100 39
#8 101-500 9
#9 >500 18
Average 3.11
standard
***Report Model: CortexM0_SoC***
IO Statistics
#IO 39
#input 8
#output 30
#inout 1
Utilization Statistics
#lut 17402 out of 19600 88.79%
#reg 2517 out of 19600 12.84%
#le 17610
#lut only 15093 out of 17610 85.71%
#reg only 208 out of 17610 1.18%
#lut&reg 2309 out of 17610 13.11%
#dsp 26 out of 29 89.66%
#bram 32 out of 64 50.00%
#bram9k 32
#fifo9k 0
#bram32k 6 out of 16 37.50%
#adc 1 out of 1 100.00%
#pad 39 out of 186 20.97%
#ireg 0
#oreg 0
#treg 0
#pll 2 out of 4 50.00%
#gclk 14 out of 16 87.50%
Detailed IO Report
Name Direction Location IOStandard DriveStrength PullType PackReg
RSTn INPUT A14 LVCMOS33 N/A PULLUP NONE
RXD INPUT F12 LVCMOS33 N/A PULLUP NONE
SWCLK INPUT R2 LVCMOS33 N/A PULLUP NONE
clk INPUT R7 LVCMOS33 N/A PULLUP NONE
col[3] INPUT F10 LVTTL33 N/A PULLUP NONE
col[2] INPUT C11 LVTTL33 N/A PULLUP NONE
col[1] INPUT D11 LVTTL33 N/A PULLUP NONE
col[0] INPUT E11 LVTTL33 N/A PULLUP NONE
LED[7] OUTPUT F16 LVCMOS33 8 NONE NONE
LED[6] OUTPUT E16 LVCMOS33 8 NONE NONE
LED[5] OUTPUT E13 LVCMOS33 8 NONE NONE
LED[4] OUTPUT C16 LVCMOS33 8 NONE NONE
LED[3] OUTPUT C15 LVCMOS33 8 NONE NONE
LED[2] OUTPUT B16 LVCMOS33 8 NONE NONE
LED[1] OUTPUT B15 LVCMOS33 8 NONE NONE
LED[0] OUTPUT B14 LVCMOS33 8 NONE NONE
MSI_CS OUTPUT P9 LVCMOS33 8 NONE NONE
MSI_REFCLK OUTPUT R15 LVCMOS33 8 NONE NONE
MSI_SCLK OUTPUT M9 LVCMOS33 8 NONE NONE
MSI_SDATA OUTPUT N9 LVCMOS33 8 NONE NONE
TXD OUTPUT D12 LVCMOS33 8 NONE NONE
audio_pwm OUTPUT N8 LVCMOS33 8 NONE NONE
row[3] OUTPUT D9 LVTTL33 8 NONE NONE
row[2] OUTPUT F9 LVTTL33 8 NONE NONE
row[1] OUTPUT C10 LVTTL33 8 NONE NONE
row[0] OUTPUT E10 LVTTL33 8 NONE NONE
seg[7] OUTPUT C8 LVCMOS33 8 NONE NONE
seg[6] OUTPUT A8 LVCMOS33 8 NONE NONE
seg[5] OUTPUT B5 LVCMOS33 8 NONE NONE
seg[4] OUTPUT A7 LVCMOS33 8 NONE NONE
seg[3] OUTPUT E8 LVCMOS33 8 NONE NONE
seg[2] OUTPUT B8 LVCMOS33 8 NONE NONE
seg[1] OUTPUT A6 LVCMOS33 8 NONE NONE
seg[0] OUTPUT A4 LVCMOS33 8 NONE NONE
sel[3] OUTPUT A3 LVCMOS33 8 NONE NONE
sel[2] OUTPUT A5 LVCMOS33 8 NONE NONE
sel[1] OUTPUT B6 LVCMOS33 8 NONE NONE
sel[0] OUTPUT C9 LVCMOS33 8 NONE NONE
SWDIO INOUT P2 LVCMOS33 8 PULLUP NONE
Report Hierarchy Area:
+----------------------------------------------------------------------+
|Instance |Module |le |lut |ripple |seq |bram |dsp |
+----------------------------------------------------------------------+
|top |CortexM0_SoC |17610 |16929 |473 |2517 |38 |26 |
+----------------------------------------------------------------------+
DataNet Average Fanout:
Index Fanout Nets
#1 1 15657
#2 2 10209
#3 3 657
#4 4 524
#5 5-10 653
#6 11-50 473
#7 51-100 36
#8 101-500 9
#9 >500 18
Average 3.09

2227
project/MMC_phy.timing
View File

File diff suppressed because it is too large Load Diff

824
project/MMC_phy.tsm
View File

@ -1,392 +1,432 @@
eagle_s20
12 22 609 18220 1000000000 9 0
-10.879 0.249 CortexM0_SoC eagle_s20 BG256 Detail 8 1
clock: DeriveClock
12 1000000000 18220 4
Setup check
22 3
Endpoint: FM_HW/FM_Dump_Data_IQ/reg0_b5|FM_HW/FM_Dump_Data_IQ/reg0_b3
22 -10.879000 40816291 3
Timing path: u_logic/_al_u2680|u_logic/Vzupw6_reg.clk->FM_HW/FM_Dump_Data_IQ/reg0_b5|FM_HW/FM_Dump_Data_IQ/reg0_b3
u_logic/_al_u2680|u_logic/Vzupw6_reg.clk
FM_HW/FM_Dump_Data_IQ/reg0_b5|FM_HW/FM_Dump_Data_IQ/reg0_b3
24 -10.879000 19.884000 30.763000 20 20
u_logic/Vzupw6 u_logic/_al_u4224|u_logic/_al_u121.c[0]
u_logic/Vo3ju6_lutinv u_logic/_al_u1992|u_logic/_al_u2497.a[0]
u_logic/_al_u2497_o u_logic/_al_u2340|u_logic/_al_u2499.b[0]
u_logic/_al_u2499_o u_logic/_al_u2508|u_logic/_al_u1569.a[1]
u_logic/_al_u2508_o u_logic/_al_u2509|u_logic/_al_u4626.d[1]
u_logic/_al_u2509_o u_logic/_al_u2510|u_logic/W8hbx6_reg.d[1]
u_logic/_al_u2510_o u_logic/_al_u2587|u_logic/L6lax6_reg.d[1]
u_logic/_al_u2587_o u_logic/_al_u2588|u_logic/T5yax6_reg.b[1]
u_logic/R0ghu6 u_logic/add2/ucin_al_u4737.b[0]
u_logic/N5fpw6[3] u_logic/_al_u2550|u_logic/_al_u2560.d[0]
u_logic/_al_u2560_o u_logic/_al_u2561|u_logic/_al_u2551.b[1]
u_logic/_al_u2561_o u_logic/_al_u4281|RAMDATA_Interface/reg0_b2.b[0]
HADDR[4] FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_r79_c1_m0.c[1]
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_i79_005 FM_HW/_al_u2796|FM_HW/_al_u3251.b[1]
FM_HW/_al_u2796_o FM_HW/_al_u2606|FM_HW/_al_u2797.c[0]
FM_HW/_al_u2797_o FM_HW/_al_u2798.c[1]
FM_HW/_al_u2798_o FM_HW/_al_u3903|FM_HW/_al_u2801.a[0]
FM_HW/_al_u2801_o FM_HW/_al_u1343|FM_HW/_al_u2813.b[0]
FM_HW/_al_u2813_o FM_HW/FM_Demodulation/reg5_b113.b[0]
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_mux_b5/B7_0 FM_HW/FM_Dump_Data_IQ/reg0_b5|FM_HW/FM_Dump_Data_IQ/reg0_b3.a[1]
Timing path: u_logic/_al_u2680|u_logic/Vzupw6_reg.clk->FM_HW/FM_Dump_Data_IQ/reg0_b5|FM_HW/FM_Dump_Data_IQ/reg0_b3
u_logic/_al_u2680|u_logic/Vzupw6_reg.clk
FM_HW/FM_Dump_Data_IQ/reg0_b5|FM_HW/FM_Dump_Data_IQ/reg0_b3
89 -10.879000 19.884000 30.763000 20 20
u_logic/Vzupw6 u_logic/_al_u4224|u_logic/_al_u121.c[0]
u_logic/Vo3ju6_lutinv u_logic/_al_u1992|u_logic/_al_u2497.a[0]
u_logic/_al_u2497_o u_logic/_al_u2340|u_logic/_al_u2499.b[0]
u_logic/_al_u2499_o u_logic/_al_u2508|u_logic/_al_u1569.a[1]
u_logic/_al_u2508_o u_logic/_al_u2509|u_logic/_al_u4626.d[1]
u_logic/_al_u2509_o u_logic/_al_u2510|u_logic/W8hbx6_reg.d[1]
u_logic/_al_u2510_o u_logic/_al_u2587|u_logic/L6lax6_reg.d[1]
u_logic/_al_u2587_o u_logic/_al_u2588|u_logic/T5yax6_reg.b[1]
u_logic/R0ghu6 u_logic/add2/ucin_al_u4737.b[0]
u_logic/N5fpw6[3] u_logic/_al_u2550|u_logic/_al_u2560.d[0]
u_logic/_al_u2560_o u_logic/_al_u2561|u_logic/_al_u2551.b[1]
u_logic/_al_u2561_o u_logic/_al_u4281|RAMDATA_Interface/reg0_b2.b[0]
HADDR[4] FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_r79_c1_m0.c[1]
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_i79_005 FM_HW/_al_u2796|FM_HW/_al_u3251.b[1]
FM_HW/_al_u2796_o FM_HW/_al_u2606|FM_HW/_al_u2797.c[0]
FM_HW/_al_u2797_o FM_HW/_al_u2798.c[0]
FM_HW/_al_u2798_o FM_HW/_al_u3903|FM_HW/_al_u2801.a[0]
FM_HW/_al_u2801_o FM_HW/_al_u1343|FM_HW/_al_u2813.b[0]
FM_HW/_al_u2813_o FM_HW/FM_Demodulation/reg5_b113.b[0]
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_mux_b5/B7_0 FM_HW/FM_Dump_Data_IQ/reg0_b5|FM_HW/FM_Dump_Data_IQ/reg0_b3.a[1]
Timing path: u_logic/_al_u2662|u_logic/Ufopw6_reg.clk->FM_HW/FM_Dump_Data_IQ/reg0_b5|FM_HW/FM_Dump_Data_IQ/reg0_b3
u_logic/_al_u2662|u_logic/Ufopw6_reg.clk
FM_HW/FM_Dump_Data_IQ/reg0_b5|FM_HW/FM_Dump_Data_IQ/reg0_b3
154 -10.864000 19.884000 30.748000 20 20
u_logic/Ufopw6 u_logic/_al_u4224|u_logic/_al_u121.d[0]
u_logic/Vo3ju6_lutinv u_logic/_al_u1992|u_logic/_al_u2497.a[0]
u_logic/_al_u2497_o u_logic/_al_u2340|u_logic/_al_u2499.b[0]
u_logic/_al_u2499_o u_logic/_al_u2508|u_logic/_al_u1569.a[1]
u_logic/_al_u2508_o u_logic/_al_u2509|u_logic/_al_u4626.d[1]
u_logic/_al_u2509_o u_logic/_al_u2510|u_logic/W8hbx6_reg.d[1]
u_logic/_al_u2510_o u_logic/_al_u2587|u_logic/L6lax6_reg.d[1]
u_logic/_al_u2587_o u_logic/_al_u2588|u_logic/T5yax6_reg.b[1]
u_logic/R0ghu6 u_logic/add2/ucin_al_u4737.b[0]
u_logic/N5fpw6[3] u_logic/_al_u2550|u_logic/_al_u2560.d[0]
u_logic/_al_u2560_o u_logic/_al_u2561|u_logic/_al_u2551.b[1]
u_logic/_al_u2561_o u_logic/_al_u4281|RAMDATA_Interface/reg0_b2.b[0]
HADDR[4] FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_r79_c1_m0.c[1]
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_i79_005 FM_HW/_al_u2796|FM_HW/_al_u3251.b[1]
FM_HW/_al_u2796_o FM_HW/_al_u2606|FM_HW/_al_u2797.c[0]
FM_HW/_al_u2797_o FM_HW/_al_u2798.c[1]
FM_HW/_al_u2798_o FM_HW/_al_u3903|FM_HW/_al_u2801.a[0]
FM_HW/_al_u2801_o FM_HW/_al_u1343|FM_HW/_al_u2813.b[0]
FM_HW/_al_u2813_o FM_HW/FM_Demodulation/reg5_b113.b[0]
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_mux_b5/B7_0 FM_HW/FM_Dump_Data_IQ/reg0_b5|FM_HW/FM_Dump_Data_IQ/reg0_b3.a[1]
Endpoint: FM_HW/_al_u3093|FM_HW/FM_Dump_Data_IQ/reg0_b4
219 -10.773000 47643106 3
Timing path: u_logic/_al_u2680|u_logic/Vzupw6_reg.clk->FM_HW/_al_u3093|FM_HW/FM_Dump_Data_IQ/reg0_b4
u_logic/_al_u2680|u_logic/Vzupw6_reg.clk
FM_HW/_al_u3093|FM_HW/FM_Dump_Data_IQ/reg0_b4
221 -10.773000 19.884000 30.657000 20 20
u_logic/Vzupw6 u_logic/_al_u4224|u_logic/_al_u121.c[0]
u_logic/Vo3ju6_lutinv u_logic/_al_u1992|u_logic/_al_u2497.a[0]
u_logic/_al_u2497_o u_logic/_al_u2340|u_logic/_al_u2499.b[0]
u_logic/_al_u2499_o u_logic/_al_u2508|u_logic/_al_u1569.a[1]
u_logic/_al_u2508_o u_logic/_al_u2509|u_logic/_al_u4626.d[1]
u_logic/_al_u2509_o u_logic/_al_u2510|u_logic/W8hbx6_reg.d[1]
u_logic/_al_u2510_o u_logic/_al_u2587|u_logic/L6lax6_reg.d[1]
u_logic/_al_u2587_o u_logic/_al_u2588|u_logic/T5yax6_reg.b[1]
u_logic/R0ghu6 u_logic/add2/ucin_al_u4737.b[0]
u_logic/N5fpw6[3] u_logic/_al_u2550|u_logic/_al_u2560.d[0]
u_logic/_al_u2560_o u_logic/_al_u2561|u_logic/_al_u2551.b[1]
u_logic/_al_u2561_o u_logic/_al_u4281|RAMDATA_Interface/reg0_b2.b[0]
HADDR[4] FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_r79_c1_m0.c[0]
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_i79_004 FM_HW/_al_u2796|FM_HW/_al_u3251.b[0]
FM_HW/_al_u3251_o FM_HW/_al_u2795|FM_HW/_al_u3252.c[0]
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_mux_b4/B1_19 FM_HW/_al_u1320|FM_HW/_al_u3255.a[0]
FM_HW/_al_u3255_o FM_HW/_al_u3256|FM_HW/_al_u2777.b[1]
FM_HW/_al_u3256_o FM_HW/_al_u3267.a[1]
FM_HW/_al_u3267_o FM_HW/_al_u2184|FM_HW/_al_u3332.a[0]
FM_HW/_al_u3332_o FM_HW/_al_u3093|FM_HW/FM_Dump_Data_IQ/reg0_b4.c[0]
Timing path: u_logic/_al_u2680|u_logic/Vzupw6_reg.clk->FM_HW/_al_u3093|FM_HW/FM_Dump_Data_IQ/reg0_b4
u_logic/_al_u2680|u_logic/Vzupw6_reg.clk
FM_HW/_al_u3093|FM_HW/FM_Dump_Data_IQ/reg0_b4
286 -10.773000 19.884000 30.657000 20 20
u_logic/Vzupw6 u_logic/_al_u4224|u_logic/_al_u121.c[0]
u_logic/Vo3ju6_lutinv u_logic/_al_u1992|u_logic/_al_u2497.a[0]
u_logic/_al_u2497_o u_logic/_al_u2340|u_logic/_al_u2499.b[0]
u_logic/_al_u2499_o u_logic/_al_u2508|u_logic/_al_u1569.a[1]
u_logic/_al_u2508_o u_logic/_al_u2509|u_logic/_al_u4626.d[1]
u_logic/_al_u2509_o u_logic/_al_u2510|u_logic/W8hbx6_reg.d[1]
u_logic/_al_u2510_o u_logic/_al_u2587|u_logic/L6lax6_reg.d[1]
u_logic/_al_u2587_o u_logic/_al_u2588|u_logic/T5yax6_reg.b[1]
u_logic/R0ghu6 u_logic/add2/ucin_al_u4737.b[0]
u_logic/N5fpw6[3] u_logic/_al_u2550|u_logic/_al_u2560.d[0]
u_logic/_al_u2560_o u_logic/_al_u2561|u_logic/_al_u2551.b[1]
u_logic/_al_u2561_o u_logic/_al_u4281|RAMDATA_Interface/reg0_b2.b[0]
HADDR[4] FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_r79_c1_m0.c[0]
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_i79_004 FM_HW/_al_u2796|FM_HW/_al_u3251.b[0]
FM_HW/_al_u3251_o FM_HW/_al_u2795|FM_HW/_al_u3252.c[0]
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_mux_b4/B1_19 FM_HW/_al_u1320|FM_HW/_al_u3255.a[0]
FM_HW/_al_u3255_o FM_HW/_al_u3256|FM_HW/_al_u2777.b[1]
FM_HW/_al_u3256_o FM_HW/_al_u3267.a[0]
FM_HW/_al_u3267_o FM_HW/_al_u2184|FM_HW/_al_u3332.a[0]
FM_HW/_al_u3332_o FM_HW/_al_u3093|FM_HW/FM_Dump_Data_IQ/reg0_b4.c[0]
Timing path: u_logic/_al_u2662|u_logic/Ufopw6_reg.clk->FM_HW/_al_u3093|FM_HW/FM_Dump_Data_IQ/reg0_b4
u_logic/_al_u2662|u_logic/Ufopw6_reg.clk
FM_HW/_al_u3093|FM_HW/FM_Dump_Data_IQ/reg0_b4
351 -10.758000 19.884000 30.642000 20 20
u_logic/Ufopw6 u_logic/_al_u4224|u_logic/_al_u121.d[0]
u_logic/Vo3ju6_lutinv u_logic/_al_u1992|u_logic/_al_u2497.a[0]
u_logic/_al_u2497_o u_logic/_al_u2340|u_logic/_al_u2499.b[0]
u_logic/_al_u2499_o u_logic/_al_u2508|u_logic/_al_u1569.a[1]
u_logic/_al_u2508_o u_logic/_al_u2509|u_logic/_al_u4626.d[1]
u_logic/_al_u2509_o u_logic/_al_u2510|u_logic/W8hbx6_reg.d[1]
u_logic/_al_u2510_o u_logic/_al_u2587|u_logic/L6lax6_reg.d[1]
u_logic/_al_u2587_o u_logic/_al_u2588|u_logic/T5yax6_reg.b[1]
u_logic/R0ghu6 u_logic/add2/ucin_al_u4737.b[0]
u_logic/N5fpw6[3] u_logic/_al_u2550|u_logic/_al_u2560.d[0]
u_logic/_al_u2560_o u_logic/_al_u2561|u_logic/_al_u2551.b[1]
u_logic/_al_u2561_o u_logic/_al_u4281|RAMDATA_Interface/reg0_b2.b[0]
HADDR[4] FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_r79_c1_m0.c[0]
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_i79_004 FM_HW/_al_u2796|FM_HW/_al_u3251.b[0]
FM_HW/_al_u3251_o FM_HW/_al_u2795|FM_HW/_al_u3252.c[0]
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_mux_b4/B1_19 FM_HW/_al_u1320|FM_HW/_al_u3255.a[0]
FM_HW/_al_u3255_o FM_HW/_al_u3256|FM_HW/_al_u2777.b[1]
FM_HW/_al_u3256_o FM_HW/_al_u3267.a[1]
FM_HW/_al_u3267_o FM_HW/_al_u2184|FM_HW/_al_u3332.a[0]
FM_HW/_al_u3332_o FM_HW/_al_u3093|FM_HW/FM_Dump_Data_IQ/reg0_b4.c[0]
Endpoint: FM_HW/_al_u1257|FM_HW/FM_Dump_Data_IQ/reg0_b2
416 -10.589000 31524130 3
Timing path: u_logic/_al_u2680|u_logic/Vzupw6_reg.clk->FM_HW/_al_u1257|FM_HW/FM_Dump_Data_IQ/reg0_b2
u_logic/_al_u2680|u_logic/Vzupw6_reg.clk
FM_HW/_al_u1257|FM_HW/FM_Dump_Data_IQ/reg0_b2
418 -10.589000 19.884000 30.473000 19 19
u_logic/Vzupw6 u_logic/_al_u4224|u_logic/_al_u121.c[0]
u_logic/Vo3ju6_lutinv u_logic/_al_u1992|u_logic/_al_u2497.a[0]
u_logic/_al_u2497_o u_logic/_al_u2340|u_logic/_al_u2499.b[0]
u_logic/_al_u2499_o u_logic/_al_u2508|u_logic/_al_u1569.a[1]
u_logic/_al_u2508_o u_logic/_al_u2509|u_logic/_al_u4626.d[1]
u_logic/_al_u2509_o u_logic/_al_u2510|u_logic/W8hbx6_reg.d[1]
u_logic/_al_u2510_o u_logic/_al_u2587|u_logic/L6lax6_reg.d[1]
u_logic/_al_u2587_o u_logic/_al_u2588|u_logic/T5yax6_reg.b[1]
u_logic/R0ghu6 u_logic/add2/ucin_al_u4737.b[0]
u_logic/N5fpw6[3] u_logic/_al_u2550|u_logic/_al_u2560.d[0]
u_logic/_al_u2560_o u_logic/_al_u2561|u_logic/_al_u2551.b[1]
u_logic/_al_u2561_o u_logic/_al_u4281|RAMDATA_Interface/reg0_b2.b[0]
HADDR[4] FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_r65_c0_m1.c[0]
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_i65_002 FM_HW/_al_u1318|FM_HW/_al_u1743.b[1]
FM_HW/_al_u1318_o FM_HW/_al_u1746|FM_HW/_al_u1319.b[0]
FM_HW/_al_u1319_o FM_HW/_al_u1320|FM_HW/_al_u3255.c[1]
FM_HW/_al_u1320_o FM_HW/_al_u1321|FM_HW/_al_u3874.b[1]
FM_HW/_al_u1321_o FM_HW/_al_u1344.b[1]
FM_HW/_al_u1344_o FM_HW/_al_u1257|FM_HW/FM_Dump_Data_IQ/reg0_b2.c[0]
Timing path: u_logic/_al_u2680|u_logic/Vzupw6_reg.clk->FM_HW/_al_u1257|FM_HW/FM_Dump_Data_IQ/reg0_b2
u_logic/_al_u2680|u_logic/Vzupw6_reg.clk
FM_HW/_al_u1257|FM_HW/FM_Dump_Data_IQ/reg0_b2
481 -10.589000 19.884000 30.473000 19 19
u_logic/Vzupw6 u_logic/_al_u4224|u_logic/_al_u121.c[0]
u_logic/Vo3ju6_lutinv u_logic/_al_u1992|u_logic/_al_u2497.a[0]
u_logic/_al_u2497_o u_logic/_al_u2340|u_logic/_al_u2499.b[0]
u_logic/_al_u2499_o u_logic/_al_u2508|u_logic/_al_u1569.a[1]
u_logic/_al_u2508_o u_logic/_al_u2509|u_logic/_al_u4626.d[1]
u_logic/_al_u2509_o u_logic/_al_u2510|u_logic/W8hbx6_reg.d[1]
u_logic/_al_u2510_o u_logic/_al_u2587|u_logic/L6lax6_reg.d[1]
u_logic/_al_u2587_o u_logic/_al_u2588|u_logic/T5yax6_reg.b[1]
u_logic/R0ghu6 u_logic/add2/ucin_al_u4737.b[0]
u_logic/N5fpw6[3] u_logic/_al_u2550|u_logic/_al_u2560.d[0]
u_logic/_al_u2560_o u_logic/_al_u2561|u_logic/_al_u2551.b[1]
u_logic/_al_u2561_o u_logic/_al_u4281|RAMDATA_Interface/reg0_b2.b[0]
HADDR[4] FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_r65_c0_m1.c[0]
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_i65_002 FM_HW/_al_u1318|FM_HW/_al_u1743.b[1]
FM_HW/_al_u1318_o FM_HW/_al_u1746|FM_HW/_al_u1319.b[0]
FM_HW/_al_u1319_o FM_HW/_al_u1320|FM_HW/_al_u3255.c[1]
FM_HW/_al_u1320_o FM_HW/_al_u1321|FM_HW/_al_u3874.b[1]
FM_HW/_al_u1321_o FM_HW/_al_u1344.b[0]
FM_HW/_al_u1344_o FM_HW/_al_u1257|FM_HW/FM_Dump_Data_IQ/reg0_b2.c[0]
Timing path: u_logic/_al_u2662|u_logic/Ufopw6_reg.clk->FM_HW/_al_u1257|FM_HW/FM_Dump_Data_IQ/reg0_b2
u_logic/_al_u2662|u_logic/Ufopw6_reg.clk
FM_HW/_al_u1257|FM_HW/FM_Dump_Data_IQ/reg0_b2
544 -10.574000 19.884000 30.458000 19 19
u_logic/Ufopw6 u_logic/_al_u4224|u_logic/_al_u121.d[0]
u_logic/Vo3ju6_lutinv u_logic/_al_u1992|u_logic/_al_u2497.a[0]
u_logic/_al_u2497_o u_logic/_al_u2340|u_logic/_al_u2499.b[0]
u_logic/_al_u2499_o u_logic/_al_u2508|u_logic/_al_u1569.a[1]
u_logic/_al_u2508_o u_logic/_al_u2509|u_logic/_al_u4626.d[1]
u_logic/_al_u2509_o u_logic/_al_u2510|u_logic/W8hbx6_reg.d[1]
u_logic/_al_u2510_o u_logic/_al_u2587|u_logic/L6lax6_reg.d[1]
u_logic/_al_u2587_o u_logic/_al_u2588|u_logic/T5yax6_reg.b[1]
u_logic/R0ghu6 u_logic/add2/ucin_al_u4737.b[0]
u_logic/N5fpw6[3] u_logic/_al_u2550|u_logic/_al_u2560.d[0]
u_logic/_al_u2560_o u_logic/_al_u2561|u_logic/_al_u2551.b[1]
u_logic/_al_u2561_o u_logic/_al_u4281|RAMDATA_Interface/reg0_b2.b[0]
HADDR[4] FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_r65_c0_m1.c[0]
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_i65_002 FM_HW/_al_u1318|FM_HW/_al_u1743.b[1]
FM_HW/_al_u1318_o FM_HW/_al_u1746|FM_HW/_al_u1319.b[0]
FM_HW/_al_u1319_o FM_HW/_al_u1320|FM_HW/_al_u3255.c[1]
FM_HW/_al_u1320_o FM_HW/_al_u1321|FM_HW/_al_u3874.b[1]
FM_HW/_al_u1321_o FM_HW/_al_u1344.b[1]
FM_HW/_al_u1344_o FM_HW/_al_u1257|FM_HW/FM_Dump_Data_IQ/reg0_b2.c[0]
Hold check
607 3
Endpoint: RAM_CODE/ram_mem_unify_al_u20_4096x8_sub_000000_000
609 0.249000 12 3
Timing path: RAMCODE_Interface/reg0_b10|RAMCODE_Interface/reg0_b7.clk->RAM_CODE/ram_mem_unify_al_u20_4096x8_sub_000000_000
RAMCODE_Interface/reg0_b10|RAMCODE_Interface/reg0_b7.clk
RAM_CODE/ram_mem_unify_al_u20_4096x8_sub_000000_000
611 0.249000 0.200000 0.449000 0 1
RAMCODE_WADDR[7] RAM_CODE/ram_mem_unify_al_u20_4096x8_sub_000000_000.addra[8]
Timing path: RAMCODE_Interface/reg0_b6|RAMCODE_Interface/reg0_b4.clk->RAM_CODE/ram_mem_unify_al_u20_4096x8_sub_000000_000
RAMCODE_Interface/reg0_b6|RAMCODE_Interface/reg0_b4.clk
RAM_CODE/ram_mem_unify_al_u20_4096x8_sub_000000_000
638 0.259000 0.200000 0.459000 0 1
RAMCODE_WADDR[4] RAM_CODE/ram_mem_unify_al_u20_4096x8_sub_000000_000.addra[5]
Timing path: RAMCODE_Interface/reg0_b6|RAMCODE_Interface/reg0_b4.clk->RAM_CODE/ram_mem_unify_al_u20_4096x8_sub_000000_000
RAMCODE_Interface/reg0_b6|RAMCODE_Interface/reg0_b4.clk
RAM_CODE/ram_mem_unify_al_u20_4096x8_sub_000000_000
665 0.411000 0.200000 0.611000 0 1
RAMCODE_WADDR[6] RAM_CODE/ram_mem_unify_al_u20_4096x8_sub_000000_000.addra[7]
Endpoint: SPI_TX/FIFO_SPI/al_ram_mem_r0_c1_l
692 0.304000 94 3
Timing path: _al_u376|SPI_TX/FIFO_SPI/reg1_b2.clk->SPI_TX/FIFO_SPI/al_ram_mem_r0_c1_l
_al_u376|SPI_TX/FIFO_SPI/reg1_b2.clk
SPI_TX/FIFO_SPI/al_ram_mem_r0_c1_l
694 0.304000 0.134000 0.438000 1 1
SPI_TX/FIFO_SPI/wp[2] SPI_TX/FIFO_SPI/al_ram_mem_r0_c1_l.c[0]
Timing path: _al_u294|SPI_Interface/wr_en_reg_reg.clk->SPI_TX/FIFO_SPI/al_ram_mem_r0_c1_l
_al_u294|SPI_Interface/wr_en_reg_reg.clk
SPI_TX/FIFO_SPI/al_ram_mem_r0_c1_l
721 1.964000 0.134000 2.098000 2 2
SPI_Interface/wr_en_reg _al_u114|_al_u116.d[0]
SPI_TX_Data[6] SPI_TX/FIFO_SPI/al_ram_mem_r0_c1_l.c[1]
Timing path: u_logic/_al_u2859|u_logic/Wvgax6_reg.clk->SPI_TX/FIFO_SPI/al_ram_mem_r0_c1_l
u_logic/_al_u2859|u_logic/Wvgax6_reg.clk
SPI_TX/FIFO_SPI/al_ram_mem_r0_c1_l
750 3.117000 0.134000 3.251000 3 3
u_logic/Wvgax6 u_logic/_al_u2540|u_logic/Z9abx6_reg.d[0]
HWDATA[6] _al_u114|_al_u116.c[0]
SPI_TX_Data[6] SPI_TX/FIFO_SPI/al_ram_mem_r0_c1_l.c[1]
Endpoint: FM_HW/FM_Demodulation/mult20_
781 0.308000 10 3
Timing path: FM_HW/FM_Demodulation/reg5_b30|FM_HW/FM_Demodulation/reg5_b31.clk->FM_HW/FM_Demodulation/mult20_
FM_HW/FM_Demodulation/reg5_b30|FM_HW/FM_Demodulation/reg5_b31.clk
FM_HW/FM_Demodulation/mult20_
783 0.308000 0.100000 0.408000 0 1
FM_HW/FM_Demodulation/dmd_data_filter[3][0] FM_HW/FM_Demodulation/mult20_.a[0]
Timing path: FM_HW/FM_Demodulation/reg5_b30|FM_HW/FM_Demodulation/reg5_b31.clk->FM_HW/FM_Demodulation/mult20_
FM_HW/FM_Demodulation/reg5_b30|FM_HW/FM_Demodulation/reg5_b31.clk
FM_HW/FM_Demodulation/mult20_
810 0.320000 0.100000 0.420000 0 1
FM_HW/FM_Demodulation/dmd_data_filter[3][1] FM_HW/FM_Demodulation/mult20_.a[1]
Timing path: FM_HW/FM_Demodulation/reg5_b36|FM_HW/FM_Demodulation/reg5_b37.clk->FM_HW/FM_Demodulation/mult20_
FM_HW/FM_Demodulation/reg5_b36|FM_HW/FM_Demodulation/reg5_b37.clk
FM_HW/FM_Demodulation/mult20_
837 0.320000 0.100000 0.420000 0 1
FM_HW/FM_Demodulation/dmd_data_filter[3][6] FM_HW/FM_Demodulation/mult20_.a[6]
Recovery check
864 3
Endpoint: cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b212|cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b208
866 6.858000 1 1
Timing path: cw_top/wrapper_cwc_top/cfg_int_inst/tap_inst/rst_reg.clk->cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b212|cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b208
cw_top/wrapper_cwc_top/cfg_int_inst/tap_inst/rst_reg.clk
cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b212|cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b208
868 6.858000 9.700000 2.842000 0 1
cw_top/wrapper_cwc_top/cfg_int_inst/rst cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b212|cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b208.sr
Endpoint: cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b140|cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b144
895 6.858000 1 1
Timing path: cw_top/wrapper_cwc_top/cfg_int_inst/tap_inst/rst_reg.clk->cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b140|cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b144
cw_top/wrapper_cwc_top/cfg_int_inst/tap_inst/rst_reg.clk
cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b140|cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b144
897 6.858000 9.700000 2.842000 0 1
cw_top/wrapper_cwc_top/cfg_int_inst/rst cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b140|cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b144.sr
Endpoint: cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg1_b47|cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg1_b48
924 6.929000 1 1
Timing path: cw_top/wrapper_cwc_top/cfg_int_inst/tap_inst/rst_reg.clk->cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg1_b47|cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg1_b48
cw_top/wrapper_cwc_top/cfg_int_inst/tap_inst/rst_reg.clk
cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg1_b47|cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg1_b48
926 6.929000 9.700000 2.771000 0 1
cw_top/wrapper_cwc_top/cfg_int_inst/rst cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg1_b47|cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg1_b48.sr
Removal check
953 3
Endpoint: cw_top/wrapper_cwc_top/trigger_inst/reg1_b15|cw_top/wrapper_cwc_top/trigger_inst/reg1_b14
955 0.426000 1 1
Timing path: _al_u300|cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg1_b0.clk->cw_top/wrapper_cwc_top/trigger_inst/reg1_b15|cw_top/wrapper_cwc_top/trigger_inst/reg1_b14
_al_u300|cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg1_b0.clk
cw_top/wrapper_cwc_top/trigger_inst/reg1_b15|cw_top/wrapper_cwc_top/trigger_inst/reg1_b14
957 0.426000 0.300000 0.726000 0 1
cw_top/wrapper_cwc_top/control[0] cw_top/wrapper_cwc_top/trigger_inst/reg1_b15|cw_top/wrapper_cwc_top/trigger_inst/reg1_b14.sr
Endpoint: cw_top/wrapper_cwc_top/trigger_inst/sub0/ucin_al_u598
984 0.503000 1 1
Timing path: _al_u300|cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg1_b0.clk->cw_top/wrapper_cwc_top/trigger_inst/sub0/ucin_al_u598
_al_u300|cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg1_b0.clk
cw_top/wrapper_cwc_top/trigger_inst/sub0/ucin_al_u598
986 0.503000 0.300000 0.803000 0 1
cw_top/wrapper_cwc_top/control[0] cw_top/wrapper_cwc_top/trigger_inst/sub0/ucin_al_u598.sr
Endpoint: cw_top/wrapper_cwc_top/trigger_inst/reg2_b2
1013 0.503000 1 1
Timing path: _al_u300|cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg1_b0.clk->cw_top/wrapper_cwc_top/trigger_inst/reg2_b2
_al_u300|cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg1_b0.clk
cw_top/wrapper_cwc_top/trigger_inst/reg2_b2
1015 0.503000 0.300000 0.803000 0 1
cw_top/wrapper_cwc_top/control[0] cw_top/wrapper_cwc_top/trigger_inst/reg2_b2.sr
Timing group statistics:
Clock constraints:
Clock Name Min Period Max Freq Skew Fanout TNS
DeriveClock (50.0MHz) 30.879ns 32MHz 0.000ns 2706 -552.899ns
Minimum input arrival time before clock: no constraint path
Maximum output required time after clock: no constraint path
Maximum combinational path delay: no constraint path
Warning: No clock constraint on 13 clock net(s):
CW_CLK_MSI
FM_Display/clk_1KHz
FM_HW/ADC_CLK
FM_HW/CW_CLK
FM_HW/EOC
FM_HW/FM_Demodulation/EOC_Count_Demodulate
FM_HW/FM_RSSI_SCAN/EOC_Count_Demodulate
FM_HW/clk_PWM1
FM_HW/clk_fm_demo_sampling
MSI_REFCLK_pad
clk_pad
jtck
u_logic/SWCLKTCK_pad
eagle_s20
12 22 687 18594 896242330 9 0
-13.826 0.304 CortexM0_SoC eagle_s20 BG256 Detail 8 1
clock: DeriveClock
12 896242330 18594 4
Setup check
22 3
Endpoint: FM_HW/FM_Dump_Data_IQ/reg0_b1|FM_HW/FM_Dump_Data_IQ/reg0_b4
22 -13.826000 48997858 3
Timing path: u_logic/P5vpw6_reg.clk->FM_HW/FM_Dump_Data_IQ/reg0_b1|FM_HW/FM_Dump_Data_IQ/reg0_b4
u_logic/P5vpw6_reg.clk
FM_HW/FM_Dump_Data_IQ/reg0_b1|FM_HW/FM_Dump_Data_IQ/reg0_b4
24 -13.826000 19.884000 33.710000 24 24
u_logic/P5vpw6 cw_top/wrapper_cwc_top/trigger_inst/HAS_BUS_DETECTOR$BUS_DETECTOR[0]$bus_detector_inst1/reg0_b7|cw_top/wrapper_cwc_top/trigger_inst/HAS_BUS_DETECTOR$BUS_DETECTOR[0]$bus_detector_inst1/reg0_b6.b[0]
u_logic/Llaow6_lutinv u_logic/_al_u1671|u_logic/_al_u2549.a[0]
u_logic/_al_u2549_o u_logic/_al_u2551|u_logic/Fpnpw6_reg.a[1]
u_logic/_al_u2551_o u_logic/_al_u2552.a[1]
u_logic/_al_u2552_o u_logic/_al_u2556|u_logic/_al_u1730.a[1]
u_logic/_al_u2556_o u_logic/_al_u2563|u_logic/_al_u159.a[1]
u_logic/_al_u2563_o u_logic/_al_u2564|u_logic/_al_u4431.d[1]
u_logic/_al_u2564_o u_logic/_al_u2565|u_logic/_al_u2892.d[1]
u_logic/_al_u2565_o u_logic/_al_u2566|u_logic/_al_u2882.d[1]
u_logic/_al_u2566_o u_logic/_al_u2641|u_logic/_al_u2759.d[1]
u_logic/Vtzhu6 u_logic/_al_u2643.d[0]
u_logic/R0ghu6 u_logic/add2/ucin_al_u4809.b[0]
u_logic/add2/c3 u_logic/add2/u3_al_u4810.fci
u_logic/N5fpw6[4] u_logic/_al_u4753|u_logic/_al_u2604.c[0]
u_logic/_al_u2604_o u_logic/_al_u2605|u_logic/Ibqpw6_reg.d[1]
u_logic/_al_u2605_o u_logic/_al_u3990|RAMDATA_Interface/reg0_b3.b[0]
HADDR[5] FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_r478_c1_m0.d[0]
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_i478_004 FM_HW/_al_u3089|FM_HW/_al_u3091.b[0]
FM_HW/_al_u3091_o FM_HW/_al_u3090|FM_HW/_al_u3092.c[0]
FM_HW/_al_u3092_o FM_HW/_al_u2670|FM_HW/_al_u3093.b[0]
FM_HW/_al_u3093_o FM_HW/_al_u1562|FM_HW/_al_u3094.c[0]
FM_HW/_al_u3094_o FM_HW/_al_u3115.a[1]
FM_HW/_al_u3115_o FM_HW/_al_u1583|FM_HW/FM_Demodulation/reg5_b57.a[0]
FM_HW/_al_u3159_o FM_HW/FM_Dump_Data_IQ/reg0_b1|FM_HW/FM_Dump_Data_IQ/reg0_b4.a[0]
Timing path: u_logic/P5vpw6_reg.clk->FM_HW/FM_Dump_Data_IQ/reg0_b1|FM_HW/FM_Dump_Data_IQ/reg0_b4
u_logic/P5vpw6_reg.clk
FM_HW/FM_Dump_Data_IQ/reg0_b1|FM_HW/FM_Dump_Data_IQ/reg0_b4
97 -13.826000 19.884000 33.710000 24 24
u_logic/P5vpw6 cw_top/wrapper_cwc_top/trigger_inst/HAS_BUS_DETECTOR$BUS_DETECTOR[0]$bus_detector_inst1/reg0_b7|cw_top/wrapper_cwc_top/trigger_inst/HAS_BUS_DETECTOR$BUS_DETECTOR[0]$bus_detector_inst1/reg0_b6.b[0]
u_logic/Llaow6_lutinv u_logic/_al_u1671|u_logic/_al_u2549.a[0]
u_logic/_al_u2549_o u_logic/_al_u2551|u_logic/Fpnpw6_reg.a[1]
u_logic/_al_u2551_o u_logic/_al_u2552.a[0]
u_logic/_al_u2552_o u_logic/_al_u2556|u_logic/_al_u1730.a[1]
u_logic/_al_u2556_o u_logic/_al_u2563|u_logic/_al_u159.a[1]
u_logic/_al_u2563_o u_logic/_al_u2564|u_logic/_al_u4431.d[1]
u_logic/_al_u2564_o u_logic/_al_u2565|u_logic/_al_u2892.d[1]
u_logic/_al_u2565_o u_logic/_al_u2566|u_logic/_al_u2882.d[1]
u_logic/_al_u2566_o u_logic/_al_u2641|u_logic/_al_u2759.d[1]
u_logic/Vtzhu6 u_logic/_al_u2643.d[0]
u_logic/R0ghu6 u_logic/add2/ucin_al_u4809.b[0]
u_logic/add2/c3 u_logic/add2/u3_al_u4810.fci
u_logic/N5fpw6[4] u_logic/_al_u4753|u_logic/_al_u2604.c[0]
u_logic/_al_u2604_o u_logic/_al_u2605|u_logic/Ibqpw6_reg.d[1]
u_logic/_al_u2605_o u_logic/_al_u3990|RAMDATA_Interface/reg0_b3.b[0]
HADDR[5] FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_r478_c1_m0.d[0]
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_i478_004 FM_HW/_al_u3089|FM_HW/_al_u3091.b[0]
FM_HW/_al_u3091_o FM_HW/_al_u3090|FM_HW/_al_u3092.c[0]
FM_HW/_al_u3092_o FM_HW/_al_u2670|FM_HW/_al_u3093.b[0]
FM_HW/_al_u3093_o FM_HW/_al_u1562|FM_HW/_al_u3094.c[0]
FM_HW/_al_u3094_o FM_HW/_al_u3115.a[1]
FM_HW/_al_u3115_o FM_HW/_al_u1583|FM_HW/FM_Demodulation/reg5_b57.a[0]
FM_HW/_al_u3159_o FM_HW/FM_Dump_Data_IQ/reg0_b1|FM_HW/FM_Dump_Data_IQ/reg0_b4.a[0]
Timing path: u_logic/P5vpw6_reg.clk->FM_HW/FM_Dump_Data_IQ/reg0_b1|FM_HW/FM_Dump_Data_IQ/reg0_b4
u_logic/P5vpw6_reg.clk
FM_HW/FM_Dump_Data_IQ/reg0_b1|FM_HW/FM_Dump_Data_IQ/reg0_b4
170 -13.826000 19.884000 33.710000 24 24
u_logic/P5vpw6 cw_top/wrapper_cwc_top/trigger_inst/HAS_BUS_DETECTOR$BUS_DETECTOR[0]$bus_detector_inst1/reg0_b7|cw_top/wrapper_cwc_top/trigger_inst/HAS_BUS_DETECTOR$BUS_DETECTOR[0]$bus_detector_inst1/reg0_b6.b[0]
u_logic/Llaow6_lutinv u_logic/_al_u1671|u_logic/_al_u2549.a[0]
u_logic/_al_u2549_o u_logic/_al_u2551|u_logic/Fpnpw6_reg.a[1]
u_logic/_al_u2551_o u_logic/_al_u2552.a[1]
u_logic/_al_u2552_o u_logic/_al_u2556|u_logic/_al_u1730.a[1]
u_logic/_al_u2556_o u_logic/_al_u2563|u_logic/_al_u159.a[1]
u_logic/_al_u2563_o u_logic/_al_u2564|u_logic/_al_u4431.d[1]
u_logic/_al_u2564_o u_logic/_al_u2565|u_logic/_al_u2892.d[1]
u_logic/_al_u2565_o u_logic/_al_u2566|u_logic/_al_u2882.d[1]
u_logic/_al_u2566_o u_logic/_al_u2641|u_logic/_al_u2759.d[1]
u_logic/Vtzhu6 u_logic/_al_u2643.d[0]
u_logic/R0ghu6 u_logic/add2/ucin_al_u4809.b[0]
u_logic/add2/c3 u_logic/add2/u3_al_u4810.fci
u_logic/N5fpw6[4] u_logic/_al_u4753|u_logic/_al_u2604.c[0]
u_logic/_al_u2604_o u_logic/_al_u2605|u_logic/Ibqpw6_reg.d[1]
u_logic/_al_u2605_o u_logic/_al_u3990|RAMDATA_Interface/reg0_b3.b[0]
HADDR[5] FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_r478_c1_m0.d[0]
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_i478_004 FM_HW/_al_u3089|FM_HW/_al_u3091.b[0]
FM_HW/_al_u3091_o FM_HW/_al_u3090|FM_HW/_al_u3092.c[0]
FM_HW/_al_u3092_o FM_HW/_al_u2670|FM_HW/_al_u3093.b[0]
FM_HW/_al_u3093_o FM_HW/_al_u1562|FM_HW/_al_u3094.c[0]
FM_HW/_al_u3094_o FM_HW/_al_u3115.a[0]
FM_HW/_al_u3115_o FM_HW/_al_u1583|FM_HW/FM_Demodulation/reg5_b57.a[0]
FM_HW/_al_u3159_o FM_HW/FM_Dump_Data_IQ/reg0_b1|FM_HW/FM_Dump_Data_IQ/reg0_b4.a[0]
Endpoint: FM_HW/_al_u3650|FM_HW/FM_Dump_Data_IQ/reg0_b7
243 -13.737000 33724860 3
Timing path: u_logic/P5vpw6_reg.clk->FM_HW/_al_u3650|FM_HW/FM_Dump_Data_IQ/reg0_b7
u_logic/P5vpw6_reg.clk
FM_HW/_al_u3650|FM_HW/FM_Dump_Data_IQ/reg0_b7
245 -13.737000 19.884000 33.621000 24 24
u_logic/P5vpw6 cw_top/wrapper_cwc_top/trigger_inst/HAS_BUS_DETECTOR$BUS_DETECTOR[0]$bus_detector_inst1/reg0_b7|cw_top/wrapper_cwc_top/trigger_inst/HAS_BUS_DETECTOR$BUS_DETECTOR[0]$bus_detector_inst1/reg0_b6.b[0]
u_logic/Llaow6_lutinv u_logic/_al_u1671|u_logic/_al_u2549.a[0]
u_logic/_al_u2549_o u_logic/_al_u2551|u_logic/Fpnpw6_reg.a[1]
u_logic/_al_u2551_o u_logic/_al_u2552.a[1]
u_logic/_al_u2552_o u_logic/_al_u2556|u_logic/_al_u1730.a[1]
u_logic/_al_u2556_o u_logic/_al_u2563|u_logic/_al_u159.a[1]
u_logic/_al_u2563_o u_logic/_al_u2564|u_logic/_al_u4431.d[1]
u_logic/_al_u2564_o u_logic/_al_u2565|u_logic/_al_u2892.d[1]
u_logic/_al_u2565_o u_logic/_al_u2566|u_logic/_al_u2882.d[1]
u_logic/_al_u2566_o u_logic/_al_u2641|u_logic/_al_u2759.d[1]
u_logic/Vtzhu6 u_logic/_al_u2643.d[0]
u_logic/R0ghu6 u_logic/add2/ucin_al_u4809.b[0]
u_logic/add2/c3 u_logic/add2/u3_al_u4810.fci
u_logic/N5fpw6[4] u_logic/_al_u4753|u_logic/_al_u2604.c[0]
u_logic/_al_u2604_o u_logic/_al_u2605|u_logic/Ibqpw6_reg.d[1]
u_logic/_al_u2605_o u_logic/_al_u3990|RAMDATA_Interface/reg0_b3.b[0]
HADDR[5] FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_r399_c1_m1.d[1]
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_i399_007 FM_HW/_al_u2331|FM_HW/_al_u2330.b[0]
FM_HW/_al_u2330_o FM_HW/_al_u2331|FM_HW/_al_u2330.c[1]
FM_HW/_al_u2331_o FM_HW/FM_Demodulation/reg5_b19|FM_HW/FM_Demodulation/reg5_b18.b[1]
FM_HW/_al_u2334_o FM_HW/_al_u2338.b[1]
FM_HW/_al_u2338_o FM_HW/FM_Demodulation/reg5_b53|FM_HW/FM_Demodulation/reg5_b59.b[1]
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_mux_b7/B6_3 FM_HW/_al_u2380|FM_HW/_al_u850.b[1]
FM_HW/_al_u2380_o FM_HW/_al_u3650|FM_HW/FM_Dump_Data_IQ/reg0_b7.c[0]
Timing path: u_logic/P5vpw6_reg.clk->FM_HW/_al_u3650|FM_HW/FM_Dump_Data_IQ/reg0_b7
u_logic/P5vpw6_reg.clk
FM_HW/_al_u3650|FM_HW/FM_Dump_Data_IQ/reg0_b7
318 -13.737000 19.884000 33.621000 24 24
u_logic/P5vpw6 cw_top/wrapper_cwc_top/trigger_inst/HAS_BUS_DETECTOR$BUS_DETECTOR[0]$bus_detector_inst1/reg0_b7|cw_top/wrapper_cwc_top/trigger_inst/HAS_BUS_DETECTOR$BUS_DETECTOR[0]$bus_detector_inst1/reg0_b6.b[0]
u_logic/Llaow6_lutinv u_logic/_al_u1671|u_logic/_al_u2549.a[0]
u_logic/_al_u2549_o u_logic/_al_u2551|u_logic/Fpnpw6_reg.a[1]
u_logic/_al_u2551_o u_logic/_al_u2552.a[0]
u_logic/_al_u2552_o u_logic/_al_u2556|u_logic/_al_u1730.a[1]
u_logic/_al_u2556_o u_logic/_al_u2563|u_logic/_al_u159.a[1]
u_logic/_al_u2563_o u_logic/_al_u2564|u_logic/_al_u4431.d[1]
u_logic/_al_u2564_o u_logic/_al_u2565|u_logic/_al_u2892.d[1]
u_logic/_al_u2565_o u_logic/_al_u2566|u_logic/_al_u2882.d[1]
u_logic/_al_u2566_o u_logic/_al_u2641|u_logic/_al_u2759.d[1]
u_logic/Vtzhu6 u_logic/_al_u2643.d[0]
u_logic/R0ghu6 u_logic/add2/ucin_al_u4809.b[0]
u_logic/add2/c3 u_logic/add2/u3_al_u4810.fci
u_logic/N5fpw6[4] u_logic/_al_u4753|u_logic/_al_u2604.c[0]
u_logic/_al_u2604_o u_logic/_al_u2605|u_logic/Ibqpw6_reg.d[1]
u_logic/_al_u2605_o u_logic/_al_u3990|RAMDATA_Interface/reg0_b3.b[0]
HADDR[5] FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_r399_c1_m1.d[1]
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_i399_007 FM_HW/_al_u2331|FM_HW/_al_u2330.b[0]
FM_HW/_al_u2330_o FM_HW/_al_u2331|FM_HW/_al_u2330.c[1]
FM_HW/_al_u2331_o FM_HW/FM_Demodulation/reg5_b19|FM_HW/FM_Demodulation/reg5_b18.b[1]
FM_HW/_al_u2334_o FM_HW/_al_u2338.b[1]
FM_HW/_al_u2338_o FM_HW/FM_Demodulation/reg5_b53|FM_HW/FM_Demodulation/reg5_b59.b[1]
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_mux_b7/B6_3 FM_HW/_al_u2380|FM_HW/_al_u850.b[1]
FM_HW/_al_u2380_o FM_HW/_al_u3650|FM_HW/FM_Dump_Data_IQ/reg0_b7.c[0]
Timing path: u_logic/P5vpw6_reg.clk->FM_HW/_al_u3650|FM_HW/FM_Dump_Data_IQ/reg0_b7
u_logic/P5vpw6_reg.clk
FM_HW/_al_u3650|FM_HW/FM_Dump_Data_IQ/reg0_b7
391 -13.737000 19.884000 33.621000 24 24
u_logic/P5vpw6 cw_top/wrapper_cwc_top/trigger_inst/HAS_BUS_DETECTOR$BUS_DETECTOR[0]$bus_detector_inst1/reg0_b7|cw_top/wrapper_cwc_top/trigger_inst/HAS_BUS_DETECTOR$BUS_DETECTOR[0]$bus_detector_inst1/reg0_b6.b[0]
u_logic/Llaow6_lutinv u_logic/_al_u1671|u_logic/_al_u2549.a[0]
u_logic/_al_u2549_o u_logic/_al_u2551|u_logic/Fpnpw6_reg.a[1]
u_logic/_al_u2551_o u_logic/_al_u2552.a[1]
u_logic/_al_u2552_o u_logic/_al_u2556|u_logic/_al_u1730.a[1]
u_logic/_al_u2556_o u_logic/_al_u2563|u_logic/_al_u159.a[1]
u_logic/_al_u2563_o u_logic/_al_u2564|u_logic/_al_u4431.d[1]
u_logic/_al_u2564_o u_logic/_al_u2565|u_logic/_al_u2892.d[1]
u_logic/_al_u2565_o u_logic/_al_u2566|u_logic/_al_u2882.d[1]
u_logic/_al_u2566_o u_logic/_al_u2641|u_logic/_al_u2759.d[1]
u_logic/Vtzhu6 u_logic/_al_u2643.d[0]
u_logic/R0ghu6 u_logic/add2/ucin_al_u4809.b[0]
u_logic/add2/c3 u_logic/add2/u3_al_u4810.fci
u_logic/N5fpw6[4] u_logic/_al_u4753|u_logic/_al_u2604.c[0]
u_logic/_al_u2604_o u_logic/_al_u2605|u_logic/Ibqpw6_reg.d[1]
u_logic/_al_u2605_o u_logic/_al_u3990|RAMDATA_Interface/reg0_b3.b[0]
HADDR[5] FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_r399_c1_m1.d[1]
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_i399_007 FM_HW/_al_u2331|FM_HW/_al_u2330.b[0]
FM_HW/_al_u2330_o FM_HW/_al_u2331|FM_HW/_al_u2330.c[1]
FM_HW/_al_u2331_o FM_HW/FM_Demodulation/reg5_b19|FM_HW/FM_Demodulation/reg5_b18.b[1]
FM_HW/_al_u2334_o FM_HW/_al_u2338.b[0]
FM_HW/_al_u2338_o FM_HW/FM_Demodulation/reg5_b53|FM_HW/FM_Demodulation/reg5_b59.b[1]
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_mux_b7/B6_3 FM_HW/_al_u2380|FM_HW/_al_u850.b[1]
FM_HW/_al_u2380_o FM_HW/_al_u3650|FM_HW/FM_Dump_Data_IQ/reg0_b7.c[0]
Endpoint: FM_HW/_al_u3584|FM_HW/FM_Dump_Data_IQ/reg0_b5
464 -13.686000 37671203 3
Timing path: u_logic/P5vpw6_reg.clk->FM_HW/_al_u3584|FM_HW/FM_Dump_Data_IQ/reg0_b5
u_logic/P5vpw6_reg.clk
FM_HW/_al_u3584|FM_HW/FM_Dump_Data_IQ/reg0_b5
466 -13.686000 19.884000 33.570000 24 24
u_logic/P5vpw6 cw_top/wrapper_cwc_top/trigger_inst/HAS_BUS_DETECTOR$BUS_DETECTOR[0]$bus_detector_inst1/reg0_b7|cw_top/wrapper_cwc_top/trigger_inst/HAS_BUS_DETECTOR$BUS_DETECTOR[0]$bus_detector_inst1/reg0_b6.b[0]
u_logic/Llaow6_lutinv u_logic/_al_u1671|u_logic/_al_u2549.a[0]
u_logic/_al_u2549_o u_logic/_al_u2551|u_logic/Fpnpw6_reg.a[1]
u_logic/_al_u2551_o u_logic/_al_u2552.a[1]
u_logic/_al_u2552_o u_logic/_al_u2556|u_logic/_al_u1730.a[1]
u_logic/_al_u2556_o u_logic/_al_u2563|u_logic/_al_u159.a[1]
u_logic/_al_u2563_o u_logic/_al_u2564|u_logic/_al_u4431.d[1]
u_logic/_al_u2564_o u_logic/_al_u2565|u_logic/_al_u2892.d[1]
u_logic/_al_u2565_o u_logic/_al_u2566|u_logic/_al_u2882.d[1]
u_logic/_al_u2566_o u_logic/_al_u2641|u_logic/_al_u2759.d[1]
u_logic/Vtzhu6 u_logic/_al_u2643.d[0]
u_logic/R0ghu6 u_logic/add2/ucin_al_u4809.b[0]
u_logic/add2/c3 u_logic/add2/u3_al_u4810.fci
u_logic/N5fpw6[4] u_logic/_al_u4753|u_logic/_al_u2604.c[0]
u_logic/_al_u2604_o u_logic/_al_u2605|u_logic/Ibqpw6_reg.d[1]
u_logic/_al_u2605_o u_logic/_al_u3990|RAMDATA_Interface/reg0_b3.b[0]
HADDR[5] FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_r475_c1_m0.d[1]
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_i475_005 FM_HW/_al_u2351|FM_HW/_al_u3012.b[0]
FM_HW/_al_u3012_o FM_HW/_al_u3013|FM_HW/_al_u2666.c[1]
FM_HW/_al_u3013_o FM_HW/_al_u3016.b[1]
FM_HW/_al_u3016_o FM_HW/_al_u1918|FM_HW/_al_u3019.a[0]
FM_HW/_al_u3019_o FM_HW/_al_u3030|FM_HW/_al_u795.b[1]
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_mux_b5/B5_7 FM_HW/_al_u3158|FM_HW/FM_Demodulation/reg5_b52.a[0]
FM_HW/_al_u3072_o FM_HW/_al_u3584|FM_HW/FM_Dump_Data_IQ/reg0_b5.c[0]
Timing path: u_logic/P5vpw6_reg.clk->FM_HW/_al_u3584|FM_HW/FM_Dump_Data_IQ/reg0_b5
u_logic/P5vpw6_reg.clk
FM_HW/_al_u3584|FM_HW/FM_Dump_Data_IQ/reg0_b5
539 -13.686000 19.884000 33.570000 24 24
u_logic/P5vpw6 cw_top/wrapper_cwc_top/trigger_inst/HAS_BUS_DETECTOR$BUS_DETECTOR[0]$bus_detector_inst1/reg0_b7|cw_top/wrapper_cwc_top/trigger_inst/HAS_BUS_DETECTOR$BUS_DETECTOR[0]$bus_detector_inst1/reg0_b6.b[0]
u_logic/Llaow6_lutinv u_logic/_al_u1671|u_logic/_al_u2549.a[0]
u_logic/_al_u2549_o u_logic/_al_u2551|u_logic/Fpnpw6_reg.a[1]
u_logic/_al_u2551_o u_logic/_al_u2552.a[0]
u_logic/_al_u2552_o u_logic/_al_u2556|u_logic/_al_u1730.a[1]
u_logic/_al_u2556_o u_logic/_al_u2563|u_logic/_al_u159.a[1]
u_logic/_al_u2563_o u_logic/_al_u2564|u_logic/_al_u4431.d[1]
u_logic/_al_u2564_o u_logic/_al_u2565|u_logic/_al_u2892.d[1]
u_logic/_al_u2565_o u_logic/_al_u2566|u_logic/_al_u2882.d[1]
u_logic/_al_u2566_o u_logic/_al_u2641|u_logic/_al_u2759.d[1]
u_logic/Vtzhu6 u_logic/_al_u2643.d[0]
u_logic/R0ghu6 u_logic/add2/ucin_al_u4809.b[0]
u_logic/add2/c3 u_logic/add2/u3_al_u4810.fci
u_logic/N5fpw6[4] u_logic/_al_u4753|u_logic/_al_u2604.c[0]
u_logic/_al_u2604_o u_logic/_al_u2605|u_logic/Ibqpw6_reg.d[1]
u_logic/_al_u2605_o u_logic/_al_u3990|RAMDATA_Interface/reg0_b3.b[0]
HADDR[5] FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_r475_c1_m0.d[1]
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_i475_005 FM_HW/_al_u2351|FM_HW/_al_u3012.b[0]
FM_HW/_al_u3012_o FM_HW/_al_u3013|FM_HW/_al_u2666.c[1]
FM_HW/_al_u3013_o FM_HW/_al_u3016.b[1]
FM_HW/_al_u3016_o FM_HW/_al_u1918|FM_HW/_al_u3019.a[0]
FM_HW/_al_u3019_o FM_HW/_al_u3030|FM_HW/_al_u795.b[1]
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_mux_b5/B5_7 FM_HW/_al_u3158|FM_HW/FM_Demodulation/reg5_b52.a[0]
FM_HW/_al_u3072_o FM_HW/_al_u3584|FM_HW/FM_Dump_Data_IQ/reg0_b5.c[0]
Timing path: u_logic/P5vpw6_reg.clk->FM_HW/_al_u3584|FM_HW/FM_Dump_Data_IQ/reg0_b5
u_logic/P5vpw6_reg.clk
FM_HW/_al_u3584|FM_HW/FM_Dump_Data_IQ/reg0_b5
612 -13.686000 19.884000 33.570000 24 24
u_logic/P5vpw6 cw_top/wrapper_cwc_top/trigger_inst/HAS_BUS_DETECTOR$BUS_DETECTOR[0]$bus_detector_inst1/reg0_b7|cw_top/wrapper_cwc_top/trigger_inst/HAS_BUS_DETECTOR$BUS_DETECTOR[0]$bus_detector_inst1/reg0_b6.b[0]
u_logic/Llaow6_lutinv u_logic/_al_u1671|u_logic/_al_u2549.a[0]
u_logic/_al_u2549_o u_logic/_al_u2551|u_logic/Fpnpw6_reg.a[1]
u_logic/_al_u2551_o u_logic/_al_u2552.a[1]
u_logic/_al_u2552_o u_logic/_al_u2556|u_logic/_al_u1730.a[1]
u_logic/_al_u2556_o u_logic/_al_u2563|u_logic/_al_u159.a[1]
u_logic/_al_u2563_o u_logic/_al_u2564|u_logic/_al_u4431.d[1]
u_logic/_al_u2564_o u_logic/_al_u2565|u_logic/_al_u2892.d[1]
u_logic/_al_u2565_o u_logic/_al_u2566|u_logic/_al_u2882.d[1]
u_logic/_al_u2566_o u_logic/_al_u2641|u_logic/_al_u2759.d[1]
u_logic/Vtzhu6 u_logic/_al_u2643.d[0]
u_logic/R0ghu6 u_logic/add2/ucin_al_u4809.b[0]
u_logic/add2/c3 u_logic/add2/u3_al_u4810.fci
u_logic/N5fpw6[4] u_logic/_al_u4753|u_logic/_al_u2604.c[0]
u_logic/_al_u2604_o u_logic/_al_u2605|u_logic/Ibqpw6_reg.d[1]
u_logic/_al_u2605_o u_logic/_al_u3990|RAMDATA_Interface/reg0_b3.b[0]
HADDR[5] FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_r475_c1_m0.d[1]
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_i475_005 FM_HW/_al_u2351|FM_HW/_al_u3012.b[0]
FM_HW/_al_u3012_o FM_HW/_al_u3013|FM_HW/_al_u2666.c[1]
FM_HW/_al_u3013_o FM_HW/_al_u3016.b[0]
FM_HW/_al_u3016_o FM_HW/_al_u1918|FM_HW/_al_u3019.a[0]
FM_HW/_al_u3019_o FM_HW/_al_u3030|FM_HW/_al_u795.b[1]
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_mux_b5/B5_7 FM_HW/_al_u3158|FM_HW/FM_Demodulation/reg5_b52.a[0]
FM_HW/_al_u3072_o FM_HW/_al_u3584|FM_HW/FM_Dump_Data_IQ/reg0_b5.c[0]
Hold check
685 3
Endpoint: SPI_TX/FIFO_SPI/al_ram_mem_r1_c1_l
687 0.304000 94 3
Timing path: _al_u270|SPI_TX/FIFO_SPI/reg1_b0.clk->SPI_TX/FIFO_SPI/al_ram_mem_r1_c1_l
_al_u270|SPI_TX/FIFO_SPI/reg1_b0.clk
SPI_TX/FIFO_SPI/al_ram_mem_r1_c1_l
689 0.304000 0.134000 0.438000 1 1
SPI_TX/FIFO_SPI/wp[0] SPI_TX/FIFO_SPI/al_ram_mem_r1_c1_l.a[0]
Timing path: UART_Interface/rd_en_reg_reg|SPI_Interface/wr_en_reg_reg.clk->SPI_TX/FIFO_SPI/al_ram_mem_r1_c1_l
UART_Interface/rd_en_reg_reg|SPI_Interface/wr_en_reg_reg.clk
SPI_TX/FIFO_SPI/al_ram_mem_r1_c1_l
716 1.596000 0.134000 1.730000 2 2
SPI_Interface/wr_en_reg _al_u128|_al_u130.d[1]
SPI_TX_Data[4] SPI_TX/FIFO_SPI/al_ram_mem_r1_c1_l.a[1]
Timing path: u_logic/_al_u3978|u_logic/Wvgax6_reg.clk->SPI_TX/FIFO_SPI/al_ram_mem_r1_c1_l
u_logic/_al_u3978|u_logic/Wvgax6_reg.clk
SPI_TX/FIFO_SPI/al_ram_mem_r1_c1_l
745 3.696000 0.134000 3.830000 3 3
u_logic/Wvgax6 u_logic/_al_u3342|u_logic/Kqhbx6_reg.d[0]
HWDATA[4] _al_u128|_al_u130.c[1]
SPI_TX_Data[4] SPI_TX/FIFO_SPI/al_ram_mem_r1_c1_l.a[1]
Endpoint: FM_HW/FM_Demodulation/mult7_
776 0.308000 10 3
Timing path: FM_HW/FM_RSSI_SCAN/add2/ucin_al_u4000.clk->FM_HW/FM_Demodulation/mult7_
FM_HW/FM_RSSI_SCAN/add2/ucin_al_u4000.clk
FM_HW/FM_Demodulation/mult7_
778 0.308000 0.100000 0.408000 0 1
FM_HW/FM_Demodulation/dmd_data_filter[16][3] FM_HW/FM_Demodulation/mult7_.a[3]
Timing path: FM_HW/FM_Demodulation/reg5_b160|FM_HW/FM_Demodulation/reg5_b162.clk->FM_HW/FM_Demodulation/mult7_
FM_HW/FM_Demodulation/reg5_b160|FM_HW/FM_Demodulation/reg5_b162.clk
FM_HW/FM_Demodulation/mult7_
805 0.320000 0.100000 0.420000 0 1
FM_HW/FM_Demodulation/dmd_data_filter[16][2] FM_HW/FM_Demodulation/mult7_.a[2]
Timing path: FM_HW/FM_Demodulation/sub0_2/u0|sub0_2/ucin.clk->FM_HW/FM_Demodulation/mult7_
FM_HW/FM_Demodulation/sub0_2/u0|sub0_2/ucin.clk
FM_HW/FM_Demodulation/mult7_
832 0.466000 0.100000 0.566000 0 1
FM_HW/FM_Demodulation/dmd_data_filter[16][8] FM_HW/FM_Demodulation/mult7_.a[8]
Endpoint: RAM_CODE/ram_mem_unify_al_u10_4096x8_sub_000000_006
859 0.313000 12 3
Timing path: RAMCODE_Interface/reg0_b9|RAMCODE_Interface/reg0_b8.clk->RAM_CODE/ram_mem_unify_al_u10_4096x8_sub_000000_006
RAMCODE_Interface/reg0_b9|RAMCODE_Interface/reg0_b8.clk
RAM_CODE/ram_mem_unify_al_u10_4096x8_sub_000000_006
861 0.313000 0.200000 0.513000 0 1
RAMCODE_WADDR[8] RAM_CODE/ram_mem_unify_al_u10_4096x8_sub_000000_006.addra[9]
Timing path: RAMCODE_Interface/reg0_b9|RAMCODE_Interface/reg0_b8.clk->RAM_CODE/ram_mem_unify_al_u10_4096x8_sub_000000_006
RAMCODE_Interface/reg0_b9|RAMCODE_Interface/reg0_b8.clk
RAM_CODE/ram_mem_unify_al_u10_4096x8_sub_000000_006
888 0.579000 0.200000 0.779000 0 1
RAMCODE_WADDR[9] RAM_CODE/ram_mem_unify_al_u10_4096x8_sub_000000_006.addra[10]
Timing path: RAMCODE_Interface/reg0_b11|RAMCODE_Interface/reg0_b10.clk->RAM_CODE/ram_mem_unify_al_u10_4096x8_sub_000000_006
RAMCODE_Interface/reg0_b11|RAMCODE_Interface/reg0_b10.clk
RAM_CODE/ram_mem_unify_al_u10_4096x8_sub_000000_006
915 0.582000 0.200000 0.782000 0 1
RAMCODE_WADDR[10] RAM_CODE/ram_mem_unify_al_u10_4096x8_sub_000000_006.addra[11]
Recovery check
942 3
Endpoint: cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b55|cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b68
944 7.068000 1 1
Timing path: _al_u570|cw_top/wrapper_cwc_top/cfg_int_inst/tap_inst/rst_reg.clk->cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b55|cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b68
_al_u570|cw_top/wrapper_cwc_top/cfg_int_inst/tap_inst/rst_reg.clk
cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b55|cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b68
946 7.068000 9.700000 2.632000 0 1
cw_top/wrapper_cwc_top/cfg_int_inst/rst cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b55|cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b68.sr
Endpoint: cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b63|cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b64
973 7.068000 1 1
Timing path: _al_u570|cw_top/wrapper_cwc_top/cfg_int_inst/tap_inst/rst_reg.clk->cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b63|cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b64
_al_u570|cw_top/wrapper_cwc_top/cfg_int_inst/tap_inst/rst_reg.clk
cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b63|cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b64
975 7.068000 9.700000 2.632000 0 1
cw_top/wrapper_cwc_top/cfg_int_inst/rst cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b63|cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b64.sr
Endpoint: cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b140|cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b141
1002 7.197000 1 1
Timing path: _al_u570|cw_top/wrapper_cwc_top/cfg_int_inst/tap_inst/rst_reg.clk->cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b140|cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b141
_al_u570|cw_top/wrapper_cwc_top/cfg_int_inst/tap_inst/rst_reg.clk
cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b140|cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b141
1004 7.197000 9.700000 2.503000 0 1
cw_top/wrapper_cwc_top/cfg_int_inst/rst cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b140|cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b141.sr
Removal check
1031 3
Endpoint: u_logic/_al_u2894|u_logic/Wfspw6_reg
1033 0.438000 1 1
Timing path: u_logic/_al_u2275|cpuresetn_reg.clk->u_logic/_al_u2894|u_logic/Wfspw6_reg
u_logic/_al_u2275|cpuresetn_reg.clk
u_logic/_al_u2894|u_logic/Wfspw6_reg
1035 0.438000 0.300000 0.738000 0 1
cpuresetn u_logic/_al_u2894|u_logic/Wfspw6_reg.sr
Endpoint: u_logic/_al_u3144|u_logic/Kojpw6_reg
1062 0.465000 1 1
Timing path: u_logic/_al_u2275|cpuresetn_reg.clk->u_logic/_al_u3144|u_logic/Kojpw6_reg
u_logic/_al_u2275|cpuresetn_reg.clk
u_logic/_al_u3144|u_logic/Kojpw6_reg
1064 0.465000 0.300000 0.765000 0 1
cpuresetn u_logic/_al_u3144|u_logic/Kojpw6_reg.sr
Endpoint: cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg1_b5|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg1_b6
1091 0.475000 1 1
Timing path: cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg1_b0.clk->cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg1_b5|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg1_b6
cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg1_b0.clk
cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg1_b5|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg1_b6
1093 0.475000 0.300000 0.775000 0 1
cw_top/wrapper_cwc_top/control[0] cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg1_b5|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg1_b6.sr
Timing group statistics:
Clock constraints:
Clock Name Min Period Max Freq Skew Fanout TNS
DeriveClock (50.0MHz) 33.826ns 29MHz 0.000ns 2795 -2264.715ns
Minimum input arrival time before clock: no constraint path
Maximum output required time after clock: no constraint path
Maximum combinational path delay: no constraint path
Warning: No clock constraint on 14 clock net(s):
CW_CLK_MSI
FM_Display/clk_1KHz
FM_HW/ADC_CLK
FM_HW/CW_CLK
FM_HW/EOC
FM_HW/FM_Demodulation/EOC_Count_Demodulate
FM_HW/FM_RSSI_SCAN/EOC_Count_Demodulate
FM_HW/clk_PWM1
FM_HW/clk_fm_demo_sampling
MSI_REFCLK_pad
clk_pad
jtck
scan_unit/scan_clk
u_logic/SWCLKTCK_pad

148
project/MMC_place.area
View File

@ -1,70 +1,78 @@
standard
***Report Model: CortexM0_SoC***
IO Statistics
#IO 31
#input 4
#output 26
#inout 1
Utilization Statistics
#lut 16425 out of 19600 83.80%
#reg 2390 out of 19600 12.19%
#le 16791
#lut only 14401 out of 16791 85.77%
#reg only 366 out of 16791 2.18%
#lut&reg 2024 out of 16791 12.05%
#dsp 26 out of 29 89.66%
#bram 32 out of 64 50.00%
#bram9k 32
#fifo9k 0
#bram32k 7 out of 16 43.75%
#adc 1 out of 1 100.00%
#pad 31 out of 186 16.67%
#ireg 0
#oreg 0
#treg 0
#pll 2 out of 4 50.00%
Detailed IO Report
Name Direction Location IOStandard DriveStrength PullType PackReg
RSTn INPUT A14 LVCMOS33 N/A PULLUP NONE
RXD INPUT F12 LVCMOS33 N/A PULLUP NONE
SWCLK INPUT R2 LVCMOS33 N/A PULLUP NONE
clk INPUT R7 LVCMOS33 N/A PULLUP NONE
LED[7] OUTPUT F16 LVCMOS33 8 NONE NONE
LED[6] OUTPUT E16 LVCMOS33 8 NONE NONE
LED[5] OUTPUT E13 LVCMOS33 8 NONE NONE
LED[4] OUTPUT C16 LVCMOS33 8 NONE NONE
LED[3] OUTPUT C15 LVCMOS33 8 NONE NONE
LED[2] OUTPUT B16 LVCMOS33 8 NONE NONE
LED[1] OUTPUT B15 LVCMOS33 8 NONE NONE
LED[0] OUTPUT B14 LVCMOS33 8 NONE NONE
MSI_CS OUTPUT P9 LVCMOS33 8 NONE NONE
MSI_REFCLK OUTPUT R15 LVCMOS33 8 NONE NONE
MSI_SCLK OUTPUT M9 LVCMOS33 8 NONE NONE
MSI_SDATA OUTPUT N9 LVCMOS33 8 NONE NONE
TXD OUTPUT D12 LVCMOS33 8 NONE NONE
audio_pwm OUTPUT N8 LVCMOS33 8 NONE NONE
seg[7] OUTPUT C8 LVCMOS33 8 NONE NONE
seg[6] OUTPUT A8 LVCMOS33 8 NONE NONE
seg[5] OUTPUT B5 LVCMOS33 8 NONE NONE
seg[4] OUTPUT A7 LVCMOS33 8 NONE NONE
seg[3] OUTPUT E8 LVCMOS33 8 NONE NONE
seg[2] OUTPUT B8 LVCMOS33 8 NONE NONE
seg[1] OUTPUT A6 LVCMOS33 8 NONE NONE
seg[0] OUTPUT A4 LVCMOS33 8 NONE NONE
sel[3] OUTPUT A3 LVCMOS33 8 NONE NONE
sel[2] OUTPUT A5 LVCMOS33 8 NONE NONE
sel[1] OUTPUT B6 LVCMOS33 8 NONE NONE
sel[0] OUTPUT C9 LVCMOS33 8 NONE NONE
SWDIO INOUT P2 LVCMOS33 8 PULLUP NONE
Report Hierarchy Area:
+----------------------------------------------------------------------+
|Instance |Module |le |lut |ripple |seq |bram |dsp |
+----------------------------------------------------------------------+
|top |CortexM0_SoC |16791 |15972 |453 |2390 |39 |26 |
+----------------------------------------------------------------------+
standard
***Report Model: CortexM0_SoC***
IO Statistics
#IO 39
#input 8
#output 30
#inout 1
Utilization Statistics
#lut 16581 out of 19600 84.60%
#reg 2517 out of 19600 12.84%
#le 16834
#lut only 14317 out of 16834 85.05%
#reg only 253 out of 16834 1.50%
#lut&reg 2264 out of 16834 13.45%
#dsp 26 out of 29 89.66%
#bram 32 out of 64 50.00%
#bram9k 32
#fifo9k 0
#bram32k 6 out of 16 37.50%
#adc 1 out of 1 100.00%
#pad 39 out of 186 20.97%
#ireg 0
#oreg 0
#treg 0
#pll 2 out of 4 50.00%
Detailed IO Report
Name Direction Location IOStandard DriveStrength PullType PackReg
RSTn INPUT A14 LVCMOS33 N/A PULLUP NONE
RXD INPUT F12 LVCMOS33 N/A PULLUP NONE
SWCLK INPUT R2 LVCMOS33 N/A PULLUP NONE
clk INPUT R7 LVCMOS33 N/A PULLUP NONE
col[3] INPUT F10 LVTTL33 N/A PULLUP NONE
col[2] INPUT C11 LVTTL33 N/A PULLUP NONE
col[1] INPUT D11 LVTTL33 N/A PULLUP NONE
col[0] INPUT E11 LVTTL33 N/A PULLUP NONE
LED[7] OUTPUT F16 LVCMOS33 8 NONE NONE
LED[6] OUTPUT E16 LVCMOS33 8 NONE NONE
LED[5] OUTPUT E13 LVCMOS33 8 NONE NONE
LED[4] OUTPUT C16 LVCMOS33 8 NONE NONE
LED[3] OUTPUT C15 LVCMOS33 8 NONE NONE
LED[2] OUTPUT B16 LVCMOS33 8 NONE NONE
LED[1] OUTPUT B15 LVCMOS33 8 NONE NONE
LED[0] OUTPUT B14 LVCMOS33 8 NONE NONE
MSI_CS OUTPUT P9 LVCMOS33 8 NONE NONE
MSI_REFCLK OUTPUT R15 LVCMOS33 8 NONE NONE
MSI_SCLK OUTPUT M9 LVCMOS33 8 NONE NONE
MSI_SDATA OUTPUT N9 LVCMOS33 8 NONE NONE
TXD OUTPUT D12 LVCMOS33 8 NONE NONE
audio_pwm OUTPUT N8 LVCMOS33 8 NONE NONE
row[3] OUTPUT D9 LVTTL33 8 NONE NONE
row[2] OUTPUT F9 LVTTL33 8 NONE NONE
row[1] OUTPUT C10 LVTTL33 8 NONE NONE
row[0] OUTPUT E10 LVTTL33 8 NONE NONE
seg[7] OUTPUT C8 LVCMOS33 8 NONE NONE
seg[6] OUTPUT A8 LVCMOS33 8 NONE NONE
seg[5] OUTPUT B5 LVCMOS33 8 NONE NONE
seg[4] OUTPUT A7 LVCMOS33 8 NONE NONE
seg[3] OUTPUT E8 LVCMOS33 8 NONE NONE
seg[2] OUTPUT B8 LVCMOS33 8 NONE NONE
seg[1] OUTPUT A6 LVCMOS33 8 NONE NONE
seg[0] OUTPUT A4 LVCMOS33 8 NONE NONE
sel[3] OUTPUT A3 LVCMOS33 8 NONE NONE
sel[2] OUTPUT A5 LVCMOS33 8 NONE NONE
sel[1] OUTPUT B6 LVCMOS33 8 NONE NONE
sel[0] OUTPUT C9 LVCMOS33 8 NONE NONE
SWDIO INOUT P2 LVCMOS33 8 PULLUP NONE
Report Hierarchy Area:
+----------------------------------------------------------------------+
|Instance |Module |le |lut |ripple |seq |bram |dsp |
+----------------------------------------------------------------------+
|top |CortexM0_SoC |16834 |16108 |473 |2517 |38 |26 |
+----------------------------------------------------------------------+

80
project/MMC_rtl.area
View File

@ -1,40 +1,40 @@
standard
***Report Model: CortexM0_SoC***
IO Statistics
#IO 31
#input 4
#output 26
#inout 1
Gate Statistics
#Basic gates 20809
#and 9619
#nand 0
#or 2076
#nor 0
#xor 76
#xnor 0
#buf 0
#not 6556
#bufif1 1
#MX21 547
#FADD 0
#DFF 1934
#LATCH 0
#MACRO_ADD 64
#MACRO_EQ 110
#MACRO_MULT 26
#MACRO_MUX 590
#MACRO_OTHERS 13
Report Hierarchy Area:
+--------------------------------------------------------------+
|Instance |Module |gates |seq |macros |
+--------------------------------------------------------------+
|top |CortexM0_SoC |18875 |1934 |213 |
| FM_Display |FM_Display |45 |81 |38 |
| FM_HW |FM_HW |105 |403 |85 |
| FM_Demodulation |FM_Demodulation |7 |280 |49 |
| u_logic |cortexm0ds_logic |18489 |1302 |14 |
+--------------------------------------------------------------+
standard
***Report Model: CortexM0_SoC***
IO Statistics
#IO 39
#input 8
#output 30
#inout 1
Gate Statistics
#Basic gates 21235
#and 9763
#nand 0
#or 2092
#nor 0
#xor 76
#xnor 0
#buf 0
#not 6669
#bufif1 1
#MX21 547
#FADD 0
#DFF 2087
#LATCH 0
#MACRO_ADD 66
#MACRO_EQ 112
#MACRO_MULT 26
#MACRO_MUX 626
#MACRO_OTHERS 13
Report Hierarchy Area:
+--------------------------------------------------------------+
|Instance |Module |gates |seq |macros |
+--------------------------------------------------------------+
|top |CortexM0_SoC |19148 |2087 |217 |
| FM_Display |FM_Display |45 |81 |38 |
| FM_HW |FM_HW |105 |403 |85 |
| FM_Demodulation |FM_Demodulation |7 |280 |49 |
| u_logic |cortexm0ds_logic |18681 |1318 |14 |
+--------------------------------------------------------------+

86
project/MMC_watcherInst.v
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@ -1,43 +1,43 @@
module CW_TOP_WRAPPER(jtdi, jtck, jrstn, jscan, jshift, jupdate, jtdo, non_bus_din, bus_din, trig_clk, wt_ce, wt_en, wt_addr);
localparam DEFAULT_CTRL_REG_LEN = 231;
localparam DEFAULT_STAT_REG_LEN = 18;
localparam DEFAULT_STOP_LEN = 2730;
localparam DEFAULT_NON_BUS_NODE_NUM = 2;
localparam DEFAULT_BUS_NODE_NUM = 48;
localparam DEFAULT_BUS_NUM = 3;
localparam DEFAULT_BUS1_WIDTH = 32;
localparam DEFAULT_BUS2_WIDTH = 3;
localparam DEFAULT_BUS3_WIDTH = 13;
input jtdi;
input jtck;
input jrstn;
input [1:0] jscan;
input jshift;
input jupdate;
output [1:0] jtdo;
input trig_clk;
input [DEFAULT_NON_BUS_NODE_NUM-1:0] non_bus_din;
input [DEFAULT_BUS_NODE_NUM-1:0] bus_din;
output wt_ce;
output wt_en;
output [15:0] wt_addr;
cwc_top #(.BUS1_WIDTH(DEFAULT_BUS1_WIDTH), .BUS2_WIDTH(DEFAULT_BUS2_WIDTH), .BUS3_WIDTH(DEFAULT_BUS3_WIDTH), .CTRL_REG_LEN(DEFAULT_CTRL_REG_LEN), .STAT_REG_LEN(DEFAULT_STAT_REG_LEN), .STOP_LEN(DEFAULT_STOP_LEN), .NON_BUS_NODE_NUM(DEFAULT_NON_BUS_NODE_NUM), .BUS_NODE_NUM(DEFAULT_BUS_NODE_NUM), .BUS_NUM(DEFAULT_BUS_NUM))
wrapper_cwc_top(
.jtdi(jtdi),
.jtck(jtck),
.jrstn(jrstn),
.jscan(jscan),
.jshift(jshift),
.jupdate(jupdate),
.jtdo(jtdo),
.non_bus_din(non_bus_din),
.bus_din(bus_din),
.trig_clk(trig_clk),
.wt_ce(wt_ce),
.wt_en(wt_en),
.wt_addr(wt_addr)
);
endmodule
module CW_TOP_WRAPPER(jtdi, jtck, jrstn, jscan, jshift, jupdate, jtdo, non_bus_din, bus_din, trig_clk, wt_ce, wt_en, wt_addr);
localparam DEFAULT_CTRL_REG_LEN = 223;
localparam DEFAULT_STAT_REG_LEN = 18;
localparam DEFAULT_STOP_LEN = 2730;
localparam DEFAULT_NON_BUS_NODE_NUM = 0;
localparam DEFAULT_BUS_NODE_NUM = 48;
localparam DEFAULT_BUS_NUM = 3;
localparam DEFAULT_BUS1_WIDTH = 16;
localparam DEFAULT_BUS2_WIDTH = 16;
localparam DEFAULT_BUS3_WIDTH = 16;
input jtdi;
input jtck;
input jrstn;
input [1:0] jscan;
input jshift;
input jupdate;
output [1:0] jtdo;
input trig_clk;
input [DEFAULT_NON_BUS_NODE_NUM-1:0] non_bus_din;
input [DEFAULT_BUS_NODE_NUM-1:0] bus_din;
output wt_ce;
output wt_en;
output [15:0] wt_addr;
cwc_top #(.BUS1_WIDTH(DEFAULT_BUS1_WIDTH), .BUS2_WIDTH(DEFAULT_BUS2_WIDTH), .BUS3_WIDTH(DEFAULT_BUS3_WIDTH), .CTRL_REG_LEN(DEFAULT_CTRL_REG_LEN), .STAT_REG_LEN(DEFAULT_STAT_REG_LEN), .STOP_LEN(DEFAULT_STOP_LEN), .NON_BUS_NODE_NUM(DEFAULT_NON_BUS_NODE_NUM), .BUS_NODE_NUM(DEFAULT_BUS_NODE_NUM), .BUS_NUM(DEFAULT_BUS_NUM))
wrapper_cwc_top(
.jtdi(jtdi),
.jtck(jtck),
.jrstn(jrstn),
.jscan(jscan),
.jshift(jshift),
.jupdate(jupdate),
.jtdo(jtdo),
.non_bus_din(non_bus_din),
.bus_din(bus_din),
.trig_clk(trig_clk),
.wt_ce(wt_ce),
.wt_en(wt_en),
.wt_addr(wt_addr)
);
endmodule

360
project/rssi.cwc
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485259
project/simulation/MMC.sdf
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355437
project/simulation/MMC_gate_sim.v
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358996
project/simulation/MMC_phy_sim.v
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358998
project/simulation/MMC_phy_sim_sta.v
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178036
project/simulation/MMC_rtl_sim.v
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rtl/peripherals/KeyScan.v Normal file
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@ -0,0 +1,120 @@
module keyboard_scan(clk,col,row,key);
input clk;
input [3:0] col;
output reg [3:0] row = 4'b1110;
output reg [15:0] key;
reg [31:0] cnt = 0;
reg scan_clk = 0;
always@(posedge clk) begin
if(cnt == 2499) begin
cnt <= 0;
scan_clk <= ~scan_clk;
end
else
cnt <= cnt + 1;
end
always@(posedge scan_clk)
row <= {row[2:0],row[3]};
always@(negedge scan_clk)
case(row)
4'b1110 : key[3:0] <= col;
4'b1101 : key[7:4] <= col;
4'b1011 : key[11:8] <= col;
4'b0111 : key[15:12] <= col;
default : key <= 0;
endcase
endmodule
module key_filter(clk,rstn,key_in,key_deb,en);
input clk;
input rstn;
input [15:0] key_in;
output [15:0] key_deb;
output en;
// Counting
reg [19:0] cnt = 0;
parameter CNTMAX = 999_999;
always@(posedge clk or negedge rstn) begin
if(~rstn)
cnt <= 0;
else if(cnt == CNTMAX)
cnt <= 0;
else
cnt <= cnt + 1'b1;
end
// Sampling
reg [15:0] key_reg0;
reg [15:0] key_reg1;
reg [15:0] key_reg2;
always@(posedge clk or negedge rstn) begin
if(~rstn) begin
key_reg0 <= 16'hffff;
key_reg1 <= 16'hffff;
key_reg2 <= 16'hffff;
end
else if(cnt == CNTMAX) begin
key_reg0 <= key_in;
key_reg1 <= key_reg0;
key_reg2 <= key_reg1;
end
end
assign key_deb = (~key_reg0&~key_reg1& ~key_reg2)|(~key_reg0&~key_reg1&key_reg2);
// State_machine
parameter s0 = 1'b0 ;
parameter s1 = 1'b1 ;
reg [2:0] current_state ; //statement
reg [2:0] next_state ; //statement
reg [15:0] key_debb;// define the intermediate variable
reg en;
always@(posedge clk or negedge rstn) begin
if(~rstn) begin
current_state <= s0;
next_state <= s0;
end
else begin
current_state <= next_state;
key_debb <= key_deb;
case(current_state)
s0:if(key_deb == key_debb) begin//s0
next_state <= s0;
en <= 0;
end
else begin
next_state <= s1;
en <= 1;
end
s1:if(key_deb == key_debb) begin//s1
next_state <= s1;
en <= 0;
end
else begin
next_state <= s0;
en <= 0;
end
default:next_state<=s0;
endcase
end
end
endmodule
module pulse_gen
(
input clk,
input RSTn,
input [15:0] key_signal,
output [15:0] pulse
);
reg [15:0] key_reg_1;
reg [15:0] key_reg_2;
always @(posedge clk or negedge RSTn) begin
if (~RSTn) begin
key_reg_1 <= 0;
key_reg_2 <= 0;
end
else begin
key_reg_1 <= key_signal;
key_reg_2 <= key_reg_1;
end
end
assign pulse = (key_signal) & (~key_reg_2);
endmodule

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rtl/topmodule/CortexM0_SoC.v
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src/channelSelection_control.c
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694
src/code_def.c
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@ -1,249 +1,445 @@
#include "code_def.h"
#include <string.h>
#include <math.h>
#define REG_1_Gain_mask 0xe001
#define RSSI_Base 0x60000050
#define STEP 0.02
#define NUM 1060
//global variables
float freq_I=87.0;
RSSIType rssilist[NUM];
int rssi_index=0;
/*
//Insert your output declaration here
*/
/*
FM_Receiver_state:
STATE Command from uart
0: not started 'B'
1: started, 'A'
2: Gain adjust state, 'G'
3: INT adjust state, 'I'
4: FRAC adjust state. 'F'
5: FRAC adjust state. 'f'
*/
//extern unsigned int FM_Receiver_state; //0: not started 1: started, 2:Gain adjust state, 3: INT adjust state, 4: FRAC adjust state.
/*
unsigned int FM_Receiver_state=0;
unsigned int FM_current_gain=20; //0~63dB, step: 1dB
unsigned int FM_current_INT=31; //29~36; step:1
unsigned int FM_current_FRAC=400; //0~2999; step: 10
unsigned int FM_current_AFC=0; //0~2999; step: 10
unsigned int REG1=0x0000e201;
unsigned int REG2=0x0001f2bc2;
unsigned int REG3=0x00000003;
*/
void Delay(int interval)
{
int i = 0;
while(1)
{
i = i + 1;
if(i == interval) break;
}
}
char ReadUARTState()
{
char state;
state = UART -> UARTTX_STATE;
return(state);
}
char ReadUART()
{
char data;
data = UART -> UARTRX_DATA;
return(data);
}
void WriteUART(char data)
{
while(ReadUARTState());
UART -> UARTTX_DATA = data;
}
void UARTString(char *stri)
{
int i;
for(i=0;i<(strlen(stri));i++)
{
Delay(1000);
WriteUART(stri[i]);
}
}
void UARTHandle()
{
unsigned int data;
//unsigned int MSI_SPI_Data= 0;
//char* intstring;
data = ReadUART();
ChannelSelection_control(data);
}
void SPI_RFD(volatile uint32_t MSI_SPI_Data)
{
SPITX->SPITX_DATA = MSI_SPI_Data;
}
void Start_FM_command(void)
{
(*(volatile unsigned int *)FM_Control_Base)=( unsigned int)16;
}
void Stop_FM_command(void)
{
(*(volatile unsigned int *)FM_Control_Base)=( unsigned int)32;
}
void IQ_Dump_command(void)
{
(*(volatile unsigned int *)FM_Control_Base)=( unsigned int)1;
}
void UARTFM_IQ_Dump_Done_Handler(void)
{
unsigned int IQdata,ii;
char* intstring;
NVIC_ICER_ADDR=0;
#ifndef SIM_PROFILE
UARTString("Start dump IQ Data! \n");
#endif
(*(volatile unsigned int *)FM_Control_Base)=( unsigned int) 2;
for(ii=0;ii<=7935;ii++)
{
IQdata=*(volatile unsigned int *)(IQ_Data_BASE+ii*4);
intstring=int_to_str(IQdata);
#ifndef SIM_PROFILE
UARTString(intstring);
UARTString("\n");
#endif
}
(*(volatile unsigned int *)FM_Control_Base)=( unsigned int) 4;
}
void Demodulated_Data_Dump_command(void)
{
(*(volatile unsigned int *)FM_Control_Base)=( unsigned int)64;
}
void UARTFM_Demodulated_Data_Dump_Done_Handler(void)
{
unsigned int DemodulatedData,ii;
char* intstring;
#ifndef SIM_PROFILE
UARTString("Start dump demodulated Data! \n");
#endif
(*(volatile unsigned int *)FM_Control_Base)=( unsigned int) 128;
for(ii=0;ii<=7935;ii++)
{
DemodulatedData=*(volatile unsigned int *)(IQ_Data_BASE+ii*4);
intstring=int_to_str(DemodulatedData);
#ifndef SIM_PROFILE
UARTString(intstring);
UARTString("\n");
#endif
}
(*(volatile unsigned int *)FM_Control_Base)=( unsigned int) 192;
}
void Channel_control(ChannelControlType ChanelControlData)
{
unsigned int controldisplay;
unsigned int freq;
controldisplay = ChanelControlData.channel_no;
freq = (unsigned int)((ChanelControlData.freq)*10); //changed to int
controldisplay = controldisplay + (freq%10)*32; //fraction part
freq = freq/10;
controldisplay = controldisplay + (freq%10)*512; //single digit part
freq = freq/10;
controldisplay = controldisplay + (freq%10)*8192; //percentage digit part
freq = freq/10;
controldisplay = controldisplay + (freq%10)*131072; //percentage digit part
(*(volatile unsigned int *)FM_ChannelControl_Base)=controldisplay;
};
void SPIwrite(int INT, int FRAC, int AFC, int Gain)
{
SPI_RFD(0x00043420);
SPI_RFD(0x0028bb85);
SPI_RFD(INT*65536 + FRAC*16 + 2);
SPI_RFD(0x16001 + Gain*16);
SPI_RFD(0x00200016);
SPI_RFD(0x00000004);
SPI_RFD(AFC*16+3);
}
void singleFrequencyRSSI()
{
int INT=floor(freq_I/3);
int FRAC=(freq_I/3-INT)*3000;
int Gain=15;
int AFC=0;
SPIwrite(INT,FRAC,AFC,Gain);
}
void RSSI_scan_cmd(void)
{
(*(volatile unsigned int *)FM_Control_Base)=( unsigned int)256;
}
int RSSI_read(void)
{
return (*(volatile unsigned int *)(RSSI_Base));
}
void RSSI_done(void)
{
(*(volatile unsigned int *)FM_Control_Base)=( unsigned int)512;
}
void RSSIScanHandler(void)
{
int j;
rssilist[rssi_index].RSSI=RSSI_read();
RSSI_done();
rssilist[rssi_index].index=rssi_index;
freq_I += STEP;
rssi_index += 1;
if(freq_I<108){
singleFrequencyRSSI();
RSSI_scan_cmd();
}
else{
freq_I=87;
rssi_index=0;
#ifndef SIM_PROFILE
// Used for Debug mode.
for(j=0;j<NUM;j++){
UARTString(int_to_str(rssilist[j].RSSI));
UARTString("\n");
}
#endif
/*
//The function is supposed to be called here.
*/
}
}
/*
//Insert the complete function here
*/
#include "code_def.h"
#include <string.h>
#include <math.h>
#define REG_1_Gain_mask 0xe001
#define RSSI_Base 0x60000050
#define STEP 0.02
#define NUM 1060
#define OUTNUM 16
#define Thresh 1900
//global variables
float freq_I=87.0;
RSSIType rssilist[NUM];
int rssi_index=0;
ChannelControlType channelcontrollist[OUTNUM];
/*
FM_Receiver_state:
STATE Command from uart
0: not started 'B'
1: started, 'A'
2: Gain adjust state, 'G'
3: INT adjust state, 'I'
4: FRAC adjust state. 'F'
5: FRAC adjust state. 'f'
*/
//extern unsigned int FM_Receiver_state; //0: not started 1: started, 2:Gain adjust state, 3: INT adjust state, 4: FRAC adjust state.
/*
unsigned int FM_Receiver_state=0;
unsigned int FM_current_gain=20; //0~63dB, step: 1dB
unsigned int FM_current_INT=31; //29~36; step:1
unsigned int FM_current_FRAC=400; //0~2999; step: 10
unsigned int FM_current_AFC=0; //0~2999; step: 10
unsigned int REG1=0x0000e201;
unsigned int REG2=0x0001f2bc2;
unsigned int REG3=0x00000003;
*/
void Delay(int interval)
{
int i = 0;
while(1)
{
i = i + 1;
if(i == interval) break;
}
}
char ReadUARTState()
{
char state;
state = UART -> UARTTX_STATE;
return(state);
}
char ReadUART()
{
char data;
data = UART -> UARTRX_DATA;
return(data);
}
void WriteUART(char data)
{
while(ReadUARTState());
UART -> UARTTX_DATA = data;
}
void UARTString(char *stri)
{
int i;
for(i=0;i<(strlen(stri));i++)
{
Delay(1000);
WriteUART(stri[i]);
}
}
void UARTHandle()
{
unsigned int data;
//unsigned int MSI_SPI_Data= 0;
//char* intstring;
data = ReadUART();
ChannelSelection_control(data);
}
void SPI_RFD(volatile uint32_t MSI_SPI_Data)
{
SPITX->SPITX_DATA = MSI_SPI_Data;
}
void Start_FM_command(void)
{
(*(volatile unsigned int *)FM_Control_Base)=( unsigned int)16;
}
void Stop_FM_command(void)
{
(*(volatile unsigned int *)FM_Control_Base)=( unsigned int)32;
}
void IQ_Dump_command(void)
{
(*(volatile unsigned int *)FM_Control_Base)=( unsigned int)1;
}
void UARTFM_IQ_Dump_Done_Handler(void)
{
unsigned int IQdata,ii;
char* intstring;
NVIC_ICER_ADDR=0;
#ifndef SIM_PROFILE
UARTString("Start dump IQ Data! \n");
#endif
(*(volatile unsigned int *)FM_Control_Base)=( unsigned int) 2;
for(ii=0;ii<=7935;ii++)
{
IQdata=*(volatile unsigned int *)(IQ_Data_BASE+ii*4);
intstring=int_to_str(IQdata);
#ifndef SIM_PROFILE
UARTString(intstring);
UARTString("\n");
#endif
}
(*(volatile unsigned int *)FM_Control_Base)=( unsigned int) 4;
}
void Demodulated_Data_Dump_command(void)
{
(*(volatile unsigned int *)FM_Control_Base)=( unsigned int)64;
}
void UARTFM_Demodulated_Data_Dump_Done_Handler(void)
{
unsigned int DemodulatedData,ii;
char* intstring;
#ifndef SIM_PROFILE
UARTString("Start dump demodulated Data! \n");
#endif
(*(volatile unsigned int *)FM_Control_Base)=( unsigned int) 128;
for(ii=0;ii<=7935;ii++)
{
DemodulatedData=*(volatile unsigned int *)(IQ_Data_BASE+ii*4);
intstring=int_to_str(DemodulatedData);
#ifndef SIM_PROFILE
UARTString(intstring);
UARTString("\n");
#endif
}
(*(volatile unsigned int *)FM_Control_Base)=( unsigned int) 192;
}
void Channel_control(ChannelControlType ChanelControlData)
{
unsigned int controldisplay;
unsigned int freq;
controldisplay = ChanelControlData.channel_no;
freq = (unsigned int)((ChanelControlData.freq)*10); //changed to int
controldisplay = controldisplay + (freq%10)*32; //fraction part
freq = freq/10;
controldisplay = controldisplay + (freq%10)*512; //single digit part
freq = freq/10;
controldisplay = controldisplay + (freq%10)*8192; //percentage digit part
freq = freq/10;
controldisplay = controldisplay + (freq%10)*131072; //percentage digit part
(*(volatile unsigned int *)FM_ChannelControl_Base)=controldisplay;
};
void SPIwrite(int INT, int FRAC, int AFC, int Gain)
{
SPI_RFD(0x00043420);
SPI_RFD(0x0028bb85);
SPI_RFD(INT*65536 + FRAC*16 + 2);
SPI_RFD(0x16001 + Gain*16);
SPI_RFD(0x00200016);
SPI_RFD(0x00000004);
SPI_RFD(AFC*16+3);
}
void singleFrequencyRSSI()
{
int INT=floor(freq_I/3);
int FRAC=(freq_I/3-INT)*3000;
int Gain=15;
int AFC=0;
SPIwrite(INT,FRAC,AFC,Gain);
}
void regWrite(float freq)
{
int INT=floor(freq/3);
int FRAC=(freq/3-INT)*3000;
int Gain=15;
int AFC=0;
SPIwrite(INT,FRAC,AFC,Gain);
}
void RSSI_scan_cmd(void)
{
(*(volatile unsigned int *)FM_Control_Base)=( unsigned int)256;
}
int RSSI_read(void)
{
return (*(volatile unsigned int *)(RSSI_Base));
}
void RSSI_done(void)
{
(*(volatile unsigned int *)FM_Control_Base)=( unsigned int)512;
}
void RSSIScanHandler(void)
{
int j;
rssilist[rssi_index].RSSI=RSSI_read();
RSSI_done();
rssilist[rssi_index].index=rssi_index;
freq_I += STEP;
rssi_index += 1;
if(freq_I<108){
singleFrequencyRSSI();
RSSI_scan_cmd();
}
else{
freq_I=87;
rssi_index=0;
#ifndef SIM_PROFILE
// Used for Debug mode.
/*
for(j=0;j<NUM;j++){
UARTString(int_to_str(rssilist[j].RSSI));
UARTString("\n");
}
*/
#endif
RSSIScanscreen();
UARTString("Scan done!\n");
}
}
void RSSIScanscreen()
{
int i, j, k, n, rssi[OUTNUM];
float temp, freq;
freq = 87;
i = 0;
n = 1;
for (j = 0; freq += STEP, j < (NUM - 10); j++)
{
if (rssilist[j].RSSI < Thresh)
continue;
if ((rssilist[j].RSSI >= rssilist[j - 12].RSSI * 4) && (rssilist[j].RSSI >= rssilist[j + 12].RSSI * 4))
{
for (k = 0; (k <= i) && (k < 16); k++)
if ((freq - channelcontrollist[k].freq) < 0.2)
{
channelcontrollist[k].freq = (channelcontrollist[k].freq * n + freq) / (n + 1);
n += 1;
break;
}
if ((k <= i) && (k < 16))
continue;
else if (i == 0)
{
channelcontrollist[i].freq = freq;
rssi[i] = rssilist[j].RSSI;
i += 1;
}
else if (i < OUTNUM)
{
channelcontrollist[i].freq = freq;
rssi[i] = rssilist[j].RSSI;
if (rssilist[j].RSSI < rssi[0])
{
rssi[i] = rssi[0];
rssi[0] = rssilist[j].RSSI;
channelcontrollist[i].freq = channelcontrollist[0].freq;
channelcontrollist[0].freq = freq;
}
i += 1;
}
else if (rssilist[j].RSSI > rssi[0])
{
rssi[0] = rssilist[j].RSSI;
channelcontrollist[0].freq = freq;
Bubbling(rssi);
}
else
continue;
n = 1;
}
}
for (i = 0; i < OUTNUM; i++)
for (j = 1; j < (OUTNUM - i); j++)
{
if (channelcontrollist[j].freq < channelcontrollist[j - 1].freq)
{
temp = channelcontrollist[j].freq;
channelcontrollist[j].freq = channelcontrollist[j - 1].freq;
channelcontrollist[j - 1].freq = temp;
}
}
for (i = 0; i < OUTNUM; i++)
{
channelcontrollist[i].INT = floor(channelcontrollist[i].freq / 3);
channelcontrollist[i].FRAC = (channelcontrollist[i].freq / 3 - channelcontrollist[i].INT) * 3000;
channelcontrollist[i].channel_no = i+1;
}
}
int Bubbling(int* rssi)
{
int i, j, k;
float temp;
for (i = 0; i < OUTNUM; i++)
for (j = 1; j < (OUTNUM - i); j++)
{
if (rssi[j] < rssi[j - 1])
{
k = rssi[j];
rssi[j] = rssi[j - 1];
rssi[j - 1] = k;
temp = channelcontrollist[j].freq;
channelcontrollist[j].freq = channelcontrollist[j - 1].freq;
channelcontrollist[j - 1].freq = temp;
}
}
return rssi[0];
}
//Key_interrupt handlers
void KEY0(void)
{
UARTString("Channel0\n");
regWrite(channelcontrollist[0].freq);
Channel_control(channelcontrollist[0]);
}
void KEY1(void)
{
UARTString("Channel1\n");
regWrite(channelcontrollist[1].freq);
Channel_control(channelcontrollist[1]);
}
void KEY2(void)
{
UARTString("Channel2\n");
regWrite(channelcontrollist[2].freq);
Channel_control(channelcontrollist[2]);
}
void KEY3(void)
{
UARTString("Channel3\n");
regWrite(channelcontrollist[3].freq);
Channel_control(channelcontrollist[3]);
}
void KEY4(void)
{
UARTString("Channel4\n");
regWrite(channelcontrollist[4].freq);
Channel_control(channelcontrollist[4]);
}
void KEY5(void)
{
UARTString("Channel5\n");
regWrite(channelcontrollist[5].freq);
Channel_control(channelcontrollist[5]);
}
void KEY6(void)
{
UARTString("Channel6\n");
regWrite(channelcontrollist[6].freq);
Channel_control(channelcontrollist[6]);
}
void KEY7(void)
{
UARTString("Channel7\n");
regWrite(channelcontrollist[7].freq);
Channel_control(channelcontrollist[7]);
}
void KEY8(void)
{
UARTString("Channel8\n");
regWrite(channelcontrollist[8].freq);
Channel_control(channelcontrollist[8]);
}
void KEY9(void)
{
UARTString("Channel9\n");
regWrite(channelcontrollist[9].freq);
Channel_control(channelcontrollist[9]);
}
void KEY10(void)
{
UARTString("Channel10\n");
regWrite(channelcontrollist[10].freq);
Channel_control(channelcontrollist[10]);
}
void KEY11(void)
{
UARTString("Channel11\n");
regWrite(channelcontrollist[11].freq);
Channel_control(channelcontrollist[11]);
}
void KEY12(void)
{
UARTString("Channel12\n");
regWrite(channelcontrollist[12].freq);
Channel_control(channelcontrollist[12]);
}
void KEY13(void)
{
UARTString("Channel13\n");
regWrite(channelcontrollist[13].freq);
Channel_control(channelcontrollist[13]);
}
void KEY14(void)
{
UARTString("Channel14\n");
regWrite(channelcontrollist[14].freq);
Channel_control(channelcontrollist[14]);
}
void KEY15(void)
{
UARTString("Channel15\n");
regWrite(channelcontrollist[15].freq);
Channel_control(channelcontrollist[15]);
}

170
src/code_def.h
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@ -1,77 +1,93 @@
#include <stdint.h>
//INTERRUPT DEF
#define NVIC_CTRL_ADDR (*(volatile unsigned *)0xe000e100)
#define NVIC_ICER_ADDR (*(volatile unsigned *)0xe000e180)
#define INT_MAX 2147483647
#define INT_MIN (-2147483647-1)
//#define SIM_PROFILE
//UART DEF
typedef struct{
volatile uint32_t UARTRX_DATA;
volatile uint32_t UARTTX_STATE;
volatile uint32_t UARTTX_DATA;
}UARTType;
#define UART_BASE 0x40000010
#define UART ((UARTType *)UART_BASE)
#define SPI_BASE 0x50000010
#define IQ_Data_BASE 0x60000400
#define FM_Control_Base 0x60000010
#define FM_ChannelControl_Base 0x60000020
typedef struct{
unsigned int channel_no;
float freq;
unsigned int INT;
unsigned int FRAC;
}ChannelControlType;
typedef struct{
volatile uint32_t SPITX_DATA;
}SPIType;
#define SPITX ((SPIType*)SPI_BASE)
typedef struct{
int index;
int RSSI;
}RSSIType;
typedef struct{
int No;
int freq;
}Sel_Channel;
void Delay(int interval);
char ReadUARTState(void);
char ReadUART(void);
void WriteUART(char data);
void UARTString(char *stri);
void UARTHandle(void);
void SPI_RFD(volatile uint32_t MSI_SPI_Data);
void UARTFM_IQ_Dump_Done_Handle(void);
void IQ_Dump_command(void);
void Demodulated_Data_Dump_command(void);
void UARTFM_Demodulated_Data_Dump_Done_Handler(void);
char* int_to_str(int iVal);
void Start_FM_command(void);
void Stop_FM_command(void);
void ChannelSelection_control(unsigned int data);
void Channel_control(ChannelControlType ChanelControlData);
void singleFrequencyRSSI(void);
void SPIwrite(int INT, int FRAC, int AFC, int Gain);
int RSSI_Read(void);
void RSSIScanHandler(void);
void RSSI_scan_cmd(void);
/*
//Insert your Function declaration here
*/
#include <stdint.h>
//INTERRUPT DEF
#define NVIC_CTRL_ADDR (*(volatile unsigned *)0xe000e100)
#define NVIC_ICER_ADDR (*(volatile unsigned *)0xe000e180)
#define INT_MAX 2147483647
#define INT_MIN (-2147483647-1)
//#define SIM_PROFILE
//UART DEF
typedef struct{
volatile uint32_t UARTRX_DATA;
volatile uint32_t UARTTX_STATE;
volatile uint32_t UARTTX_DATA;
}UARTType;
#define UART_BASE 0x40000010
#define UART ((UARTType *)UART_BASE)
#define SPI_BASE 0x50000010
#define IQ_Data_BASE 0x60000400
#define FM_Control_Base 0x60000010
#define FM_ChannelControl_Base 0x60000020
typedef struct{
unsigned int channel_no;
float freq;
unsigned int INT;
unsigned int FRAC;
}ChannelControlType;
typedef struct{
volatile uint32_t SPITX_DATA;
}SPIType;
#define SPITX ((SPIType*)SPI_BASE)
typedef struct{
int index;
int RSSI;
}RSSIType;
typedef struct{
int No;
int freq;
}Sel_Channel;
void Delay(int interval);
char ReadUARTState(void);
char ReadUART(void);
void WriteUART(char data);
void UARTString(char *stri);
void UARTHandle(void);
void SPI_RFD(volatile uint32_t MSI_SPI_Data);
void UARTFM_IQ_Dump_Done_Handle(void);
void IQ_Dump_command(void);
void Demodulated_Data_Dump_command(void);
void UARTFM_Demodulated_Data_Dump_Done_Handler(void);
char* int_to_str(int iVal);
void Start_FM_command(void);
void Stop_FM_command(void);
void ChannelSelection_control(unsigned int data);
void Channel_control(ChannelControlType ChanelControlData);
void singleFrequencyRSSI(void);
void SPIwrite(int INT, int FRAC, int AFC, int Gain);
int RSSI_Read(void);
void RSSIScanHandler(void);
void RSSI_scan_cmd(void);
void RSSIScanscreen(void);
int Bubbling(int* rssi);
void regWrite(float freq);
//Key interrupt handlers
void KEY0(void);
void KEY1(void);
void KEY2(void);
void KEY3(void);
void KEY4(void);
void KEY5(void);
void KEY6(void);
void KEY7(void);
void KEY8(void);
void KEY9(void);
void KEY10(void);
void KEY11(void);
void KEY12(void);
void KEY13(void);
void KEY14(void);
void KEY15(void);

122
src/main.c
View File

@ -1,62 +1,60 @@
#include "code_def.h"
#include <string.h>
#include <stdint.h>
#define SPI_interword_interval 50000
int main()
{
char string[32] = {0};
unsigned int MSI_SPI_Data= 0;
ChannelControlType ChannelControlDisplay;
NVIC_CTRL_ADDR = 15; //enable lowest 2 interrupts
/*
MSI_SPI_Data = 0x00043420; //reg 0: 24M clk
SPI_RFD(MSI_SPI_Data);
MSI_SPI_Data = 0x0028bb85; //reg5: THRESH=3000
SPI_RFD(MSI_SPI_Data);
MSI_SPI_Data = 0x001f1902; //Reg2: INT=31,FRAC=400 LNA close; 93.4MHz in Shanghai
SPI_RFD(MSI_SPI_Data);
MSI_SPI_Data = 0x0000e141; //Reg1: BB Gain decrease 20dB LNA Gain redcution: 23dB
SPI_RFD(MSI_SPI_Data);
MSI_SPI_Data = 0x00200016; //Reg6: DC default value
SPI_RFD(MSI_SPI_Data);
MSI_SPI_Data = 0x00000004; //Reg4: Aux features
SPI_RFD(MSI_SPI_Data);
MSI_SPI_Data = 0x00000003; //Reg3:AFC = 0
SPI_RFD(MSI_SPI_Data);
// UARTString("start the normal FM receiver!\n");
// UARTString("start Dump Audio data!\n");
//Start_FM_command();
//Demodulated_Data_Dump_command();
// UARTString("start the normal FM receiver!\n");
// UARTString("start Dump IQ data!\n");
ChannelControlDisplay.channel_no =5;
ChannelControlDisplay.freq =93.4;
ChannelControlDisplay.INT =31;
ChannelControlDisplay.FRAC =400;
Channel_control(ChannelControlDisplay);
Start_FM_command();
*/
//IQ_Dump_command();
while(1)
{
Delay(15000);
}
}
#include "code_def.h"
#include <string.h>
#include <stdint.h>
#define SPI_interword_interval 50000
int main()
{
NVIC_CTRL_ADDR = 0xFFFFF; //enable lowest 2 interrupts
/*
char string[32] = {0};
unsigned int MSI_SPI_Data= 0;
ChannelControlType ChannelControlDisplay;
MSI_SPI_Data = 0x00043420; //reg 0: 24M clk
SPI_RFD(MSI_SPI_Data);
MSI_SPI_Data = 0x0028bb85; //reg5: THRESH=3000
SPI_RFD(MSI_SPI_Data);
MSI_SPI_Data = 0x001f1902; //Reg2: INT=31,FRAC=400 LNA close; 93.4MHz in Shanghai
SPI_RFD(MSI_SPI_Data);
MSI_SPI_Data = 0x0000e141; //Reg1: BB Gain decrease 20dB LNA Gain redcution: 23dB
SPI_RFD(MSI_SPI_Data);
MSI_SPI_Data = 0x00200016; //Reg6: DC default value
SPI_RFD(MSI_SPI_Data);
MSI_SPI_Data = 0x00000004; //Reg4: Aux features
SPI_RFD(MSI_SPI_Data);
MSI_SPI_Data = 0x00000003; //Reg3:AFC = 0
SPI_RFD(MSI_SPI_Data);
// UARTString("start the normal FM receiver!\n");
// UARTString("start Dump Audio data!\n");
//Start_FM_command();
//Demodulated_Data_Dump_command();
// UARTString("start the normal FM receiver!\n");
// UARTString("start Dump IQ data!\n");
ChannelControlDisplay.channel_no =5;
ChannelControlDisplay.freq =93.4;
ChannelControlDisplay.INT =31;
ChannelControlDisplay.FRAC =400;
Channel_control(ChannelControlDisplay);
Start_FM_command();
IQ_Dump_data();
*/
while(1)
{
Delay(15000);
}
}

473
src/startup_CMSDK_CM0.s
View File

@ -1,165 +1,308 @@
;/**************************************************************************//**
; * @file startup_CMSDK_CM0.s
; * @brief CMSIS Cortex-M0 Core Device Startup File for
; * Device CMSDK_CM0
; * @version V3.01
; * @date 06. March 2012
; *
; * @note
; * Copyright (C) 2012 ARM Limited. All rights reserved.
; *
; * @par
; * ARM Limited (ARM) is supplying this software for use with Cortex-M
; * processor based microcontrollers. This file can be freely distributed
; * within development tools that are supporting such ARM based processors.
; *
; * @par
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
; *
; ******************************************************************************/
;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;*/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=4
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000400
AREA HEAP, NOINIT, READWRITE, ALIGN=4
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD 0 ; NMI Handler
DCD 0 ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; PendSV Handler
DCD 0 ; SysTick Handler
DCD UART_Handler ; IRQ0 Handler
DCD FM_IQ_Dump_Done ; IRQ1 Handler
DCD Demodulated_Data_Dump_Done; IRQ2 Handler
DCD RSSI_Scan_Done ; IRQ3 Handler
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
GLOBAL Reset_Handler
ENTRY
IMPORT __main
LDR R0, =__main
MOV R8, R0
MOV R9, R8
BL __main
ENDP
Demodulated_Data_Dump_Done PROC
EXPORT Demodulated_Data_Dump_Done
IMPORT UARTFM_Demodulated_Data_Dump_Done_Handler
PUSH {R0,R1,R2,LR}
BL UARTFM_Demodulated_Data_Dump_Done_Handler
POP {R0,R1,R2,PC}
ENDP
FM_IQ_Dump_Done PROC
EXPORT FM_IQ_Dump_Done
IMPORT UARTFM_IQ_Dump_Done_Handler
PUSH {R0,R1,R2,LR}
BL UARTFM_IQ_Dump_Done_Handler
POP {R0,R1,R2,PC}
ENDP
UART_Handler PROC
EXPORT UART_Handler [WEAK]
IMPORT UARTHandle
PUSH {R0,R1,R2,LR}
BL UARTHandle
POP {R0,R1,R2,PC}
ENDP
RSSI_Scan_Done PROC
EXPORT RSSI_Scan_Done [WEAK]
IMPORT RSSIScanHandler
PUSH {R0,R1,R2,LR}
BL RSSIScanHandler
POP {R0,R1,R2,PC}
ENDP
ALIGN 4
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;/**************************************************************************//**
; * @file startup_CMSDK_CM0.s
; * @brief CMSIS Cortex-M0 Core Device Startup File for
; * Device CMSDK_CM0
; * @version V3.01
; * @date 06. March 2012
; *
; * @note
; * Copyright (C) 2012 ARM Limited. All rights reserved.
; *
; * @par
; * ARM Limited (ARM) is supplying this software for use with Cortex-M
; * processor based microcontrollers. This file can be freely distributed
; * within development tools that are supporting such ARM based processors.
; *
; * @par
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
; *
; ******************************************************************************/
;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;*/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=4
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000400
AREA HEAP, NOINIT, READWRITE, ALIGN=4
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD 0 ; NMI Handler
DCD 0 ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; PendSV Handler
DCD 0 ; SysTick Handler
DCD UART_Handler ; IRQ0 Handler
DCD FM_IQ_Dump_Done ; IRQ1 Handler
DCD Demodulated_Data_Dump_Done; IRQ2 Handler
DCD RSSI_Scan_Done ; IRQ3 Handler
DCD KEY15_Handler ; IRQ4 Handler
DCD KEY14_Handler ; IRQ5 Handler
DCD KEY13_Handler ; IRQ6 Handler
DCD KEY12_Handler ; IRQ7 Handler
DCD KEY11_Handler ; IRQ8 Handler
DCD KEY10_Handler ; IRQ9 Handler
DCD KEY9_Handler ; IRQ10 Handler
DCD KEY8_Handler ; IRQ11 Handler
DCD KEY7_Handler ; IRQ12 Handler
DCD KEY6_Handler ; IRQ13 Handler
DCD KEY5_Handler ; IRQ14 Handler
DCD KEY4_Handler ; IRQ15 Handler
DCD KEY3_Handler ; IRQ16 Handler
DCD KEY2_Handler ; IRQ17 Handler
DCD KEY1_Handler ; IRQ18 Handler
DCD KEY0_Handler ; IRQ19 Handler
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
GLOBAL Reset_Handler
ENTRY
IMPORT __main
LDR R0, =__main
MOV R8, R0
MOV R9, R8
BL __main
ENDP
Demodulated_Data_Dump_Done PROC
EXPORT Demodulated_Data_Dump_Done
IMPORT UARTFM_Demodulated_Data_Dump_Done_Handler
PUSH {R0,R1,R2,LR}
BL UARTFM_Demodulated_Data_Dump_Done_Handler
POP {R0,R1,R2,PC}
ENDP
FM_IQ_Dump_Done PROC
EXPORT FM_IQ_Dump_Done
IMPORT UARTFM_IQ_Dump_Done_Handler
PUSH {R0,R1,R2,LR}
BL UARTFM_IQ_Dump_Done_Handler
POP {R0,R1,R2,PC}
ENDP
UART_Handler PROC
EXPORT UART_Handler [WEAK]
IMPORT UARTHandle
PUSH {R0,R1,R2,LR}
BL UARTHandle
POP {R0,R1,R2,PC}
ENDP
RSSI_Scan_Done PROC
EXPORT RSSI_Scan_Done [WEAK]
IMPORT RSSIScanHandler
PUSH {R0,R1,R2,LR}
BL RSSIScanHandler
POP {R0,R1,R2,PC}
ENDP
KEY0_Handler PROC
EXPORT KEY0_Handler [WEAK]
IMPORT KEY0
PUSH {R0,R1,R2,LR}
BL KEY0
POP {R0,R1,R2,PC}
ENDP
KEY1_Handler PROC
EXPORT KEY1_Handler [WEAK]
IMPORT KEY1
PUSH {R0,R1,R2,LR}
BL KEY1
POP {R0,R1,R2,PC}
ENDP
KEY2_Handler PROC
EXPORT KEY2_Handler [WEAK]
IMPORT KEY2
PUSH {R0,R1,R2,LR}
BL KEY2
POP {R0,R1,R2,PC}
ENDP
KEY3_Handler PROC
EXPORT KEY3_Handler [WEAK]
IMPORT KEY3
PUSH {R0,R1,R2,LR}
BL KEY3
POP {R0,R1,R2,PC}
ENDP
KEY4_Handler PROC
EXPORT KEY4_Handler [WEAK]
IMPORT KEY4
PUSH {R0,R1,R2,LR}
BL KEY4
POP {R0,R1,R2,PC}
ENDP
KEY5_Handler PROC
EXPORT KEY5_Handler [WEAK]
IMPORT KEY5
PUSH {R0,R1,R2,LR}
BL KEY5
POP {R0,R1,R2,PC}
ENDP
KEY6_Handler PROC
EXPORT KEY6_Handler [WEAK]
IMPORT KEY6
PUSH {R0,R1,R2,LR}
BL KEY6
POP {R0,R1,R2,PC}
ENDP
KEY7_Handler PROC
EXPORT KEY7_Handler [WEAK]
IMPORT KEY7
PUSH {R0,R1,R2,LR}
BL KEY7
POP {R0,R1,R2,PC}
ENDP
KEY8_Handler PROC
EXPORT KEY8_Handler [WEAK]
IMPORT KEY8
PUSH {R0,R1,R2,LR}
BL KEY8
POP {R0,R1,R2,PC}
ENDP
KEY9_Handler PROC
EXPORT KEY9_Handler [WEAK]
IMPORT KEY9
PUSH {R0,R1,R2,LR}
BL KEY9
POP {R0,R1,R2,PC}
ENDP
KEY10_Handler PROC
EXPORT KEY10_Handler [WEAK]
IMPORT KEY10
PUSH {R0,R1,R2,LR}
BL KEY10
POP {R0,R1,R2,PC}
ENDP
KEY11_Handler PROC
EXPORT KEY11_Handler [WEAK]
IMPORT KEY11
PUSH {R0,R1,R2,LR}
BL KEY11
POP {R0,R1,R2,PC}
ENDP
KEY12_Handler PROC
EXPORT KEY12_Handler [WEAK]
IMPORT KEY12
PUSH {R0,R1,R2,LR}
BL KEY12
POP {R0,R1,R2,PC}
ENDP
KEY13_Handler PROC
EXPORT KEY13_Handler [WEAK]
IMPORT KEY13
PUSH {R0,R1,R2,LR}
BL KEY13
POP {R0,R1,R2,PC}
ENDP
KEY14_Handler PROC
EXPORT KEY14_Handler [WEAK]
IMPORT KEY14
PUSH {R0,R1,R2,LR}
BL KEY14
POP {R0,R1,R2,PC}
ENDP
KEY15_Handler PROC
EXPORT KEY15_Handler [WEAK]
IMPORT KEY15
PUSH {R0,R1,R2,LR}
BL KEY15
POP {R0,R1,R2,PC}
ENDP
ALIGN 4
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END

11
test/RSSI_Scan.asv
View File

@ -1,11 +0,0 @@
load RSSI_Scan.mat;
figure(1);
plot(linspace(87.02,107.98,1050),Dec_list);
title('RSSI Dec_list')
xlabel('Frequency(KHz)')
ylabel('RSSI')
figure(2);
plot(Log_list);
title('RSSI evaluation centered of real station channel')
xlabel('Frequency(KHz)')
ylabel('RSSI')

20
test/RSSI_Scan.m
View File

@ -1,11 +1,11 @@
load RSSI_Scan.mat;
figure(1);
plot(linspace(87.02,108,1050),Dec_list);
title('RSSI Dec_list')
xlabel('Frequency(KHz)')
ylabel('RSSI')
figure(2);
plot(linspace(87.02,108,1050),Log_list);
title('RSSI Log_list')
xlabel('Frequency(KHz)')
load RSSI_Scan.mat;
figure(1);
plot(linspace(87.02,108,1050),Dec_list);
title('RSSI Dec\_list')
xlabel('Frequency(KHz)')
ylabel('RSSI')
figure(2);
plot(linspace(87.02,108,1050),Log_list);
title('RSSI Log\_list')
xlabel('Frequency(KHz)')
ylabel('RSSI')