mirror of
https://github.com/JefferyLi0903/MMC.git
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RSSI Update
This commit is contained in:
JefferyLi0903
parent
da2100d054
commit
0a7e321de1
@ -29,4 +29,11 @@ set_pin_assignment { seg[4] } { LOCATION = A7; IOSTANDARD = LVCMOS33; }
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set_pin_assignment { seg[5] } { LOCATION = B5; IOSTANDARD = LVCMOS33; }
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set_pin_assignment { seg[6] } { LOCATION = A8; IOSTANDARD = LVCMOS33; }
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set_pin_assignment { seg[7] } { LOCATION = C8; IOSTANDARD = LVCMOS33; }
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set_pin_assignment { col[0] } { LOCATION = E11; IOSTANDARD = LVTTL33; }
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set_pin_assignment { col[1] } { LOCATION = D11; IOSTANDARD = LVTTL33; }
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set_pin_assignment { col[2] } { LOCATION = C11; IOSTANDARD = LVTTL33; }
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set_pin_assignment { col[3] } { LOCATION = F10; IOSTANDARD = LVTTL33; }
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set_pin_assignment { row[0] } { LOCATION = E10; IOSTANDARD = LVTTL33; }
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set_pin_assignment { row[1] } { LOCATION = C10; IOSTANDARD = LVTTL33; }
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set_pin_assignment { row[2] } { LOCATION = F9; IOSTANDARD = LVTTL33; }
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set_pin_assignment { row[3] } { LOCATION = D9; IOSTANDARD = LVTTL33; }
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File diff suppressed because it is too large
Load Diff
@ -114,109 +114,286 @@ ARM Macro Assembler Page 2
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79 00000048 00000000 DCD Demodulated_Data_Dump_Done
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; IRQ2 Handler
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80 0000004C 00000000 DCD RSSI_Scan_Done ; IRQ3 Handler
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81 00000050
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82 00000050
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83 00000050
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84 00000050 AREA |.text|, CODE, READONLY
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85 00000000
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86 00000000
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87 00000000 ; Reset Handler
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88 00000000
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89 00000000 Reset_Handler
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PROC
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90 00000000 GLOBAL Reset_Handler
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91 00000000 ENTRY
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92 00000000 IMPORT __main
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93 00000000 480D LDR R0, =__main
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81 00000050 00000000 DCD KEY15_Handler ; IRQ4 Handler
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82 00000054 00000000 DCD KEY14_Handler ; IRQ5 Handler
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83 00000058 00000000 DCD KEY13_Handler ; IRQ6 Handler
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84 0000005C 00000000 DCD KEY12_Handler ; IRQ7 Handler
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85 00000060 00000000 DCD KEY11_Handler ; IRQ8 Handler
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86 00000064 00000000 DCD KEY10_Handler ; IRQ9 Handler
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87 00000068 00000000 DCD KEY9_Handler ; IRQ10 Handler
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88 0000006C 00000000 DCD KEY8_Handler ; IRQ11 Handler
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89 00000070 00000000 DCD KEY7_Handler ; IRQ12 Handler
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90 00000074 00000000 DCD KEY6_Handler ; IRQ13 Handler
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91 00000078 00000000 DCD KEY5_Handler ; IRQ14 Handler
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92 0000007C 00000000 DCD KEY4_Handler ; IRQ15 Handler
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93 00000080 00000000 DCD KEY3_Handler ; IRQ16 Handler
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94 00000084 00000000 DCD KEY2_Handler ; IRQ17 Handler
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ARM Macro Assembler Page 3
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94 00000002 4680 MOV R8, R0
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95 00000004 46C1 MOV R9, R8
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96 00000006 F7FF FFFE BL __main
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97 0000000A ENDP
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98 0000000A
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99 0000000A
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100 0000000A
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101 0000000A Demodulated_Data_Dump_Done
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95 00000088 00000000 DCD KEY1_Handler ; IRQ18 Handler
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96 0000008C 00000000 DCD KEY0_Handler ; IRQ19 Handler
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97 00000090
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98 00000090
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99 00000090
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100 00000090 AREA |.text|, CODE, READONLY
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101 00000000
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102 00000000
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103 00000000 ; Reset Handler
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104 00000000
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105 00000000 Reset_Handler
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PROC
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102 0000000A
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103 0000000A EXPORT Demodulated_Data_Dump_Done
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104 0000000A IMPORT UARTFM_Demodulated_Data_Dump_Do
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106 00000000 GLOBAL Reset_Handler
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107 00000000 ENTRY
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108 00000000 IMPORT __main
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109 00000000 482D LDR R0, =__main
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110 00000002 4680 MOV R8, R0
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111 00000004 46C1 MOV R9, R8
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112 00000006 F7FF FFFE BL __main
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113 0000000A ENDP
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114 0000000A
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115 0000000A
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116 0000000A
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117 0000000A Demodulated_Data_Dump_Done
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PROC
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118 0000000A
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119 0000000A EXPORT Demodulated_Data_Dump_Done
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120 0000000A IMPORT UARTFM_Demodulated_Data_Dump_Do
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ne_Handler
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105 0000000A B507 PUSH {R0,R1,R2,LR}
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106 0000000C F7FF FFFE BL UARTFM_Demodulated_Data_Dump_Do
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121 0000000A B507 PUSH {R0,R1,R2,LR}
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122 0000000C F7FF FFFE BL UARTFM_Demodulated_Data_Dump_Do
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ne_Handler
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107 00000010 BD07 POP {R0,R1,R2,PC}
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108 00000012 ENDP
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109 00000012
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110 00000012 FM_IQ_Dump_Done
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123 00000010 BD07 POP {R0,R1,R2,PC}
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124 00000012 ENDP
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125 00000012
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126 00000012 FM_IQ_Dump_Done
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PROC
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111 00000012
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112 00000012
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113 00000012 EXPORT FM_IQ_Dump_Done
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114 00000012 IMPORT UARTFM_IQ_Dump_Done_Handler
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115 00000012 B507 PUSH {R0,R1,R2,LR}
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116 00000014 F7FF FFFE BL UARTFM_IQ_Dump_Done_Handler
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117 00000018 BD07 POP {R0,R1,R2,PC}
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118 0000001A ENDP
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119 0000001A
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120 0000001A
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121 0000001A
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122 0000001A UART_Handler
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127 00000012
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128 00000012
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129 00000012 EXPORT FM_IQ_Dump_Done
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130 00000012 IMPORT UARTFM_IQ_Dump_Done_Handler
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131 00000012 B507 PUSH {R0,R1,R2,LR}
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132 00000014 F7FF FFFE BL UARTFM_IQ_Dump_Done_Handler
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133 00000018 BD07 POP {R0,R1,R2,PC}
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134 0000001A ENDP
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135 0000001A
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136 0000001A
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137 0000001A
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138 0000001A UART_Handler
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PROC
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123 0000001A EXPORT UART_Handler [WEAK]
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124 0000001A IMPORT UARTHandle
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125 0000001A B507 PUSH {R0,R1,R2,LR}
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126 0000001C F7FF FFFE BL UARTHandle
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127 00000020 BD07 POP {R0,R1,R2,PC}
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128 00000022 ENDP
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129 00000022
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130 00000022
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131 00000022 RSSI_Scan_Done
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PROC
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132 00000022 EXPORT RSSI_Scan_Done [WEAK
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]
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133 00000022 IMPORT RSSIScanHandler
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134 00000022 B507 PUSH {R0,R1,R2,LR}
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135 00000024 F7FF FFFE BL RSSIScanHandler
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136 00000028 BD07 POP {R0,R1,R2,PC}
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137 0000002A ENDP
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138 0000002A
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139 0000002A
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140 0000002A 00 00 ALIGN 4
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141 0000002C
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142 0000002C IF :DEF:__MICROLIB
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149 0000002C
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150 0000002C IMPORT __use_two_region_memory
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151 0000002C EXPORT __user_initial_stackheap
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139 0000001A EXPORT UART_Handler [WEAK]
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140 0000001A IMPORT UARTHandle
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141 0000001A B507 PUSH {R0,R1,R2,LR}
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142 0000001C F7FF FFFE BL UARTHandle
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143 00000020 BD07 POP {R0,R1,R2,PC}
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144 00000022 ENDP
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145 00000022
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146 00000022
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147 00000022 RSSI_Scan_Done
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ARM Macro Assembler Page 4
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152 0000002C
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153 0000002C __user_initial_stackheap
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154 0000002C
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155 0000002C 4803 LDR R0, = Heap_Mem
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156 0000002E 4904 LDR R1, =(Stack_Mem + Stack_Size)
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157 00000030 4A04 LDR R2, = (Heap_Mem + Heap_Size)
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158 00000032 4B05 LDR R3, = Stack_Mem
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159 00000034 4770 BX LR
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160 00000036
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161 00000036 00 00 ALIGN
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162 00000038
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163 00000038 ENDIF
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164 00000038
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165 00000038 END
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PROC
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148 00000022 EXPORT RSSI_Scan_Done [WEAK
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]
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149 00000022 IMPORT RSSIScanHandler
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150 00000022 B507 PUSH {R0,R1,R2,LR}
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151 00000024 F7FF FFFE BL RSSIScanHandler
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152 00000028 BD07 POP {R0,R1,R2,PC}
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153 0000002A ENDP
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154 0000002A
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155 0000002A KEY0_Handler
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PROC
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156 0000002A EXPORT KEY0_Handler [WEAK]
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157 0000002A IMPORT KEY0
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158 0000002A B507 PUSH {R0,R1,R2,LR}
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159 0000002C F7FF FFFE BL KEY0
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160 00000030 BD07 POP {R0,R1,R2,PC}
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161 00000032 ENDP
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162 00000032
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163 00000032 KEY1_Handler
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PROC
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164 00000032 EXPORT KEY1_Handler [WEAK]
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165 00000032 IMPORT KEY1
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166 00000032 B507 PUSH {R0,R1,R2,LR}
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167 00000034 F7FF FFFE BL KEY1
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168 00000038 BD07 POP {R0,R1,R2,PC}
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169 0000003A ENDP
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170 0000003A
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171 0000003A KEY2_Handler
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PROC
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172 0000003A EXPORT KEY2_Handler [WEAK]
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173 0000003A IMPORT KEY2
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174 0000003A B507 PUSH {R0,R1,R2,LR}
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175 0000003C F7FF FFFE BL KEY2
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176 00000040 BD07 POP {R0,R1,R2,PC}
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177 00000042 ENDP
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178 00000042
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179 00000042 KEY3_Handler
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PROC
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180 00000042 EXPORT KEY3_Handler [WEAK]
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181 00000042 IMPORT KEY3
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182 00000042 B507 PUSH {R0,R1,R2,LR}
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183 00000044 F7FF FFFE BL KEY3
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184 00000048 BD07 POP {R0,R1,R2,PC}
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185 0000004A ENDP
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186 0000004A
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187 0000004A KEY4_Handler
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PROC
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188 0000004A EXPORT KEY4_Handler [WEAK]
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189 0000004A IMPORT KEY4
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190 0000004A B507 PUSH {R0,R1,R2,LR}
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191 0000004C F7FF FFFE BL KEY4
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192 00000050 BD07 POP {R0,R1,R2,PC}
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193 00000052 ENDP
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194 00000052
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195 00000052 KEY5_Handler
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PROC
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196 00000052 EXPORT KEY5_Handler [WEAK]
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197 00000052 IMPORT KEY5
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198 00000052 B507 PUSH {R0,R1,R2,LR}
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ARM Macro Assembler Page 5
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199 00000054 F7FF FFFE BL KEY5
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200 00000058 BD07 POP {R0,R1,R2,PC}
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201 0000005A ENDP
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202 0000005A
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203 0000005A KEY6_Handler
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PROC
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204 0000005A EXPORT KEY6_Handler [WEAK]
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205 0000005A IMPORT KEY6
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206 0000005A B507 PUSH {R0,R1,R2,LR}
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207 0000005C F7FF FFFE BL KEY6
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208 00000060 BD07 POP {R0,R1,R2,PC}
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209 00000062 ENDP
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210 00000062
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211 00000062 KEY7_Handler
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PROC
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212 00000062 EXPORT KEY7_Handler [WEAK]
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213 00000062 IMPORT KEY7
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214 00000062 B507 PUSH {R0,R1,R2,LR}
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215 00000064 F7FF FFFE BL KEY7
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216 00000068 BD07 POP {R0,R1,R2,PC}
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217 0000006A ENDP
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218 0000006A
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219 0000006A KEY8_Handler
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PROC
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220 0000006A EXPORT KEY8_Handler [WEAK]
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221 0000006A IMPORT KEY8
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222 0000006A B507 PUSH {R0,R1,R2,LR}
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223 0000006C F7FF FFFE BL KEY8
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224 00000070 BD07 POP {R0,R1,R2,PC}
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225 00000072 ENDP
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226 00000072
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227 00000072 KEY9_Handler
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PROC
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228 00000072 EXPORT KEY9_Handler [WEAK]
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229 00000072 IMPORT KEY9
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230 00000072 B507 PUSH {R0,R1,R2,LR}
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231 00000074 F7FF FFFE BL KEY9
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232 00000078 BD07 POP {R0,R1,R2,PC}
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233 0000007A ENDP
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234 0000007A
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235 0000007A KEY10_Handler
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PROC
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236 0000007A EXPORT KEY10_Handler [WEAK]
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237 0000007A IMPORT KEY10
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238 0000007A B507 PUSH {R0,R1,R2,LR}
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239 0000007C F7FF FFFE BL KEY10
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240 00000080 BD07 POP {R0,R1,R2,PC}
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241 00000082 ENDP
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242 00000082
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243 00000082 KEY11_Handler
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PROC
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244 00000082 EXPORT KEY11_Handler [WEAK]
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245 00000082 IMPORT KEY11
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246 00000082 B507 PUSH {R0,R1,R2,LR}
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247 00000084 F7FF FFFE BL KEY11
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248 00000088 BD07 POP {R0,R1,R2,PC}
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249 0000008A ENDP
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250 0000008A
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251 0000008A KEY12_Handler
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ARM Macro Assembler Page 6
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PROC
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252 0000008A EXPORT KEY12_Handler [WEAK]
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253 0000008A IMPORT KEY12
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254 0000008A B507 PUSH {R0,R1,R2,LR}
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255 0000008C F7FF FFFE BL KEY12
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256 00000090 BD07 POP {R0,R1,R2,PC}
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257 00000092 ENDP
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258 00000092
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259 00000092 KEY13_Handler
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PROC
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260 00000092 EXPORT KEY13_Handler [WEAK]
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261 00000092 IMPORT KEY13
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262 00000092 B507 PUSH {R0,R1,R2,LR}
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263 00000094 F7FF FFFE BL KEY13
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264 00000098 BD07 POP {R0,R1,R2,PC}
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265 0000009A ENDP
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266 0000009A
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267 0000009A KEY14_Handler
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PROC
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268 0000009A EXPORT KEY14_Handler [WEAK]
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269 0000009A IMPORT KEY14
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270 0000009A B507 PUSH {R0,R1,R2,LR}
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271 0000009C F7FF FFFE BL KEY14
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272 000000A0 BD07 POP {R0,R1,R2,PC}
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273 000000A2 ENDP
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274 000000A2
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275 000000A2 KEY15_Handler
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PROC
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276 000000A2 EXPORT KEY15_Handler [WEAK]
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277 000000A2 IMPORT KEY15
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278 000000A2 B507 PUSH {R0,R1,R2,LR}
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279 000000A4 F7FF FFFE BL KEY15
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280 000000A8 BD07 POP {R0,R1,R2,PC}
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281 000000AA ENDP
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282 000000AA
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283 000000AA 00 00 ALIGN 4
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284 000000AC
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285 000000AC IF :DEF:__MICROLIB
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292 000000AC
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293 000000AC IMPORT __use_two_region_memory
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294 000000AC EXPORT __user_initial_stackheap
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295 000000AC
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296 000000AC __user_initial_stackheap
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297 000000AC
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298 000000AC 4803 LDR R0, = Heap_Mem
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299 000000AE 4904 LDR R1, =(Stack_Mem + Stack_Size)
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300 000000B0 4A04 LDR R2, = (Heap_Mem + Heap_Size)
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301 000000B2 4B05 LDR R3, = Stack_Mem
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302 000000B4 4770 BX LR
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303 000000B6
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304 000000B6 00 00 ALIGN
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305 000000B8
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306 000000B8 ENDIF
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307 000000B8
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308 000000B8 END
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00000000
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00000000
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00000400
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00000400
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ARM Macro Assembler Page 7
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00000000
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Command Line: --debug --xref --diag_suppress=9931 --cpu=Cortex-M0 --apcs=interw
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ork --depend=.\startup_cmsdk_cm0.d -o.\startup_cmsdk_cm0.o -IC:\Users\JefferyLi
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@ -244,8 +421,8 @@ Symbol: Stack_Mem
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Definitions
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At line 36 in file ..\src\startup_CMSDK_CM0.s
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Uses
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At line 156 in file ..\src\startup_CMSDK_CM0.s
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At line 158 in file ..\src\startup_CMSDK_CM0.s
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At line 299 in file ..\src\startup_CMSDK_CM0.s
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At line 301 in file ..\src\startup_CMSDK_CM0.s
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__initial_sp 00000400
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@ -276,8 +453,8 @@ Symbol: Heap_Mem
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Definitions
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At line 48 in file ..\src\startup_CMSDK_CM0.s
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Uses
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At line 155 in file ..\src\startup_CMSDK_CM0.s
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At line 157 in file ..\src\startup_CMSDK_CM0.s
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At line 298 in file ..\src\startup_CMSDK_CM0.s
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At line 300 in file ..\src\startup_CMSDK_CM0.s
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__heap_base 00000000
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@ -329,7 +506,7 @@ Relocatable symbols
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Symbol: .text
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Definitions
|
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At line 84 in file ..\src\startup_CMSDK_CM0.s
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At line 100 in file ..\src\startup_CMSDK_CM0.s
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Uses
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None
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Comment: .text unused
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@ -337,52 +514,52 @@ Demodulated_Data_Dump_Done 0000000A
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Symbol: Demodulated_Data_Dump_Done
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Definitions
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At line 101 in file ..\src\startup_CMSDK_CM0.s
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At line 117 in file ..\src\startup_CMSDK_CM0.s
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Uses
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At line 79 in file ..\src\startup_CMSDK_CM0.s
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At line 103 in file ..\src\startup_CMSDK_CM0.s
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At line 119 in file ..\src\startup_CMSDK_CM0.s
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||||
|
||||
FM_IQ_Dump_Done 00000012
|
||||
|
||||
Symbol: FM_IQ_Dump_Done
|
||||
Definitions
|
||||
At line 110 in file ..\src\startup_CMSDK_CM0.s
|
||||
At line 126 in file ..\src\startup_CMSDK_CM0.s
|
||||
Uses
|
||||
At line 78 in file ..\src\startup_CMSDK_CM0.s
|
||||
At line 113 in file ..\src\startup_CMSDK_CM0.s
|
||||
At line 129 in file ..\src\startup_CMSDK_CM0.s
|
||||
|
||||
RSSI_Scan_Done 00000022
|
||||
KEY0_Handler 0000002A
|
||||
|
||||
Symbol: RSSI_Scan_Done
|
||||
Symbol: KEY0_Handler
|
||||
Definitions
|
||||
At line 131 in file ..\src\startup_CMSDK_CM0.s
|
||||
At line 155 in file ..\src\startup_CMSDK_CM0.s
|
||||
Uses
|
||||
At line 80 in file ..\src\startup_CMSDK_CM0.s
|
||||
At line 132 in file ..\src\startup_CMSDK_CM0.s
|
||||
At line 96 in file ..\src\startup_CMSDK_CM0.s
|
||||
At line 156 in file ..\src\startup_CMSDK_CM0.s
|
||||
|
||||
Reset_Handler 00000000
|
||||
KEY10_Handler 0000007A
|
||||
|
||||
Symbol: Reset_Handler
|
||||
Symbol: KEY10_Handler
|
||||
Definitions
|
||||
At line 89 in file ..\src\startup_CMSDK_CM0.s
|
||||
At line 235 in file ..\src\startup_CMSDK_CM0.s
|
||||
Uses
|
||||
At line 62 in file ..\src\startup_CMSDK_CM0.s
|
||||
At line 90 in file ..\src\startup_CMSDK_CM0.s
|
||||
At line 86 in file ..\src\startup_CMSDK_CM0.s
|
||||
At line 236 in file ..\src\startup_CMSDK_CM0.s
|
||||
|
||||
UART_Handler 0000001A
|
||||
KEY11_Handler 00000082
|
||||
|
||||
Symbol: UART_Handler
|
||||
Symbol: KEY11_Handler
|
||||
Definitions
|
||||
At line 122 in file ..\src\startup_CMSDK_CM0.s
|
||||
At line 243 in file ..\src\startup_CMSDK_CM0.s
|
||||
Uses
|
||||
At line 77 in file ..\src\startup_CMSDK_CM0.s
|
||||
At line 123 in file ..\src\startup_CMSDK_CM0.s
|
||||
At line 85 in file ..\src\startup_CMSDK_CM0.s
|
||||
At line 244 in file ..\src\startup_CMSDK_CM0.s
|
||||
|
||||
__user_initial_stackheap 0000002C
|
||||
KEY12_Handler 0000008A
|
||||
|
||||
Symbol: __user_initial_stackheap
|
||||
Symbol: KEY12_Handler
|
||||
Definitions
|
||||
At line 153 in file ..\src\startup_CMSDK_CM0.s
|
||||
At line 251 in file ..\src\startup_CMSDK_CM0.s
|
||||
Uses
|
||||
|
||||
|
||||
@ -390,9 +567,165 @@ Symbol: __user_initial_stackheap
|
||||
ARM Macro Assembler Page 2 Alphabetic symbol ordering
|
||||
Relocatable symbols
|
||||
|
||||
At line 151 in file ..\src\startup_CMSDK_CM0.s
|
||||
At line 84 in file ..\src\startup_CMSDK_CM0.s
|
||||
At line 252 in file ..\src\startup_CMSDK_CM0.s
|
||||
|
||||
KEY13_Handler 00000092
|
||||
|
||||
Symbol: KEY13_Handler
|
||||
Definitions
|
||||
At line 259 in file ..\src\startup_CMSDK_CM0.s
|
||||
Uses
|
||||
At line 83 in file ..\src\startup_CMSDK_CM0.s
|
||||
At line 260 in file ..\src\startup_CMSDK_CM0.s
|
||||
|
||||
KEY14_Handler 0000009A
|
||||
|
||||
Symbol: KEY14_Handler
|
||||
Definitions
|
||||
At line 267 in file ..\src\startup_CMSDK_CM0.s
|
||||
Uses
|
||||
At line 82 in file ..\src\startup_CMSDK_CM0.s
|
||||
At line 268 in file ..\src\startup_CMSDK_CM0.s
|
||||
|
||||
KEY15_Handler 000000A2
|
||||
|
||||
Symbol: KEY15_Handler
|
||||
Definitions
|
||||
At line 275 in file ..\src\startup_CMSDK_CM0.s
|
||||
Uses
|
||||
At line 81 in file ..\src\startup_CMSDK_CM0.s
|
||||
At line 276 in file ..\src\startup_CMSDK_CM0.s
|
||||
|
||||
KEY1_Handler 00000032
|
||||
|
||||
Symbol: KEY1_Handler
|
||||
Definitions
|
||||
At line 163 in file ..\src\startup_CMSDK_CM0.s
|
||||
Uses
|
||||
At line 95 in file ..\src\startup_CMSDK_CM0.s
|
||||
At line 164 in file ..\src\startup_CMSDK_CM0.s
|
||||
|
||||
KEY2_Handler 0000003A
|
||||
|
||||
Symbol: KEY2_Handler
|
||||
Definitions
|
||||
At line 171 in file ..\src\startup_CMSDK_CM0.s
|
||||
Uses
|
||||
At line 94 in file ..\src\startup_CMSDK_CM0.s
|
||||
At line 172 in file ..\src\startup_CMSDK_CM0.s
|
||||
|
||||
KEY3_Handler 00000042
|
||||
|
||||
Symbol: KEY3_Handler
|
||||
Definitions
|
||||
At line 179 in file ..\src\startup_CMSDK_CM0.s
|
||||
Uses
|
||||
At line 93 in file ..\src\startup_CMSDK_CM0.s
|
||||
At line 180 in file ..\src\startup_CMSDK_CM0.s
|
||||
|
||||
KEY4_Handler 0000004A
|
||||
|
||||
|
||||
|
||||
|
||||
ARM Macro Assembler Page 3 Alphabetic symbol ordering
|
||||
Relocatable symbols
|
||||
|
||||
Symbol: KEY4_Handler
|
||||
Definitions
|
||||
At line 187 in file ..\src\startup_CMSDK_CM0.s
|
||||
Uses
|
||||
At line 92 in file ..\src\startup_CMSDK_CM0.s
|
||||
At line 188 in file ..\src\startup_CMSDK_CM0.s
|
||||
|
||||
KEY5_Handler 00000052
|
||||
|
||||
Symbol: KEY5_Handler
|
||||
Definitions
|
||||
At line 195 in file ..\src\startup_CMSDK_CM0.s
|
||||
Uses
|
||||
At line 91 in file ..\src\startup_CMSDK_CM0.s
|
||||
At line 196 in file ..\src\startup_CMSDK_CM0.s
|
||||
|
||||
KEY6_Handler 0000005A
|
||||
|
||||
Symbol: KEY6_Handler
|
||||
Definitions
|
||||
At line 203 in file ..\src\startup_CMSDK_CM0.s
|
||||
Uses
|
||||
At line 90 in file ..\src\startup_CMSDK_CM0.s
|
||||
At line 204 in file ..\src\startup_CMSDK_CM0.s
|
||||
|
||||
KEY7_Handler 00000062
|
||||
|
||||
Symbol: KEY7_Handler
|
||||
Definitions
|
||||
At line 211 in file ..\src\startup_CMSDK_CM0.s
|
||||
Uses
|
||||
At line 89 in file ..\src\startup_CMSDK_CM0.s
|
||||
At line 212 in file ..\src\startup_CMSDK_CM0.s
|
||||
|
||||
KEY8_Handler 0000006A
|
||||
|
||||
Symbol: KEY8_Handler
|
||||
Definitions
|
||||
At line 219 in file ..\src\startup_CMSDK_CM0.s
|
||||
Uses
|
||||
At line 88 in file ..\src\startup_CMSDK_CM0.s
|
||||
At line 220 in file ..\src\startup_CMSDK_CM0.s
|
||||
|
||||
KEY9_Handler 00000072
|
||||
|
||||
Symbol: KEY9_Handler
|
||||
Definitions
|
||||
At line 227 in file ..\src\startup_CMSDK_CM0.s
|
||||
Uses
|
||||
At line 87 in file ..\src\startup_CMSDK_CM0.s
|
||||
At line 228 in file ..\src\startup_CMSDK_CM0.s
|
||||
|
||||
RSSI_Scan_Done 00000022
|
||||
|
||||
Symbol: RSSI_Scan_Done
|
||||
Definitions
|
||||
At line 147 in file ..\src\startup_CMSDK_CM0.s
|
||||
Uses
|
||||
At line 80 in file ..\src\startup_CMSDK_CM0.s
|
||||
|
||||
|
||||
|
||||
ARM Macro Assembler Page 4 Alphabetic symbol ordering
|
||||
Relocatable symbols
|
||||
|
||||
At line 148 in file ..\src\startup_CMSDK_CM0.s
|
||||
|
||||
Reset_Handler 00000000
|
||||
|
||||
Symbol: Reset_Handler
|
||||
Definitions
|
||||
At line 105 in file ..\src\startup_CMSDK_CM0.s
|
||||
Uses
|
||||
At line 62 in file ..\src\startup_CMSDK_CM0.s
|
||||
At line 106 in file ..\src\startup_CMSDK_CM0.s
|
||||
|
||||
UART_Handler 0000001A
|
||||
|
||||
Symbol: UART_Handler
|
||||
Definitions
|
||||
At line 138 in file ..\src\startup_CMSDK_CM0.s
|
||||
Uses
|
||||
At line 77 in file ..\src\startup_CMSDK_CM0.s
|
||||
At line 139 in file ..\src\startup_CMSDK_CM0.s
|
||||
|
||||
__user_initial_stackheap 000000AC
|
||||
|
||||
Symbol: __user_initial_stackheap
|
||||
Definitions
|
||||
At line 296 in file ..\src\startup_CMSDK_CM0.s
|
||||
Uses
|
||||
At line 294 in file ..\src\startup_CMSDK_CM0.s
|
||||
Comment: __user_initial_stackheap used once
|
||||
7 symbols
|
||||
23 symbols
|
||||
|
||||
|
||||
|
||||
@ -406,7 +739,7 @@ Symbol: Heap_Size
|
||||
At line 44 in file ..\src\startup_CMSDK_CM0.s
|
||||
Uses
|
||||
At line 48 in file ..\src\startup_CMSDK_CM0.s
|
||||
At line 157 in file ..\src\startup_CMSDK_CM0.s
|
||||
At line 300 in file ..\src\startup_CMSDK_CM0.s
|
||||
|
||||
Stack_Size 00000400
|
||||
|
||||
@ -415,7 +748,7 @@ Symbol: Stack_Size
|
||||
At line 33 in file ..\src\startup_CMSDK_CM0.s
|
||||
Uses
|
||||
At line 36 in file ..\src\startup_CMSDK_CM0.s
|
||||
At line 156 in file ..\src\startup_CMSDK_CM0.s
|
||||
At line 299 in file ..\src\startup_CMSDK_CM0.s
|
||||
|
||||
2 symbols
|
||||
|
||||
@ -424,54 +757,200 @@ Symbol: Stack_Size
|
||||
ARM Macro Assembler Page 1 Alphabetic symbol ordering
|
||||
External symbols
|
||||
|
||||
KEY0 00000000
|
||||
|
||||
Symbol: KEY0
|
||||
Definitions
|
||||
At line 157 in file ..\src\startup_CMSDK_CM0.s
|
||||
Uses
|
||||
At line 159 in file ..\src\startup_CMSDK_CM0.s
|
||||
Comment: KEY0 used once
|
||||
KEY1 00000000
|
||||
|
||||
Symbol: KEY1
|
||||
Definitions
|
||||
At line 165 in file ..\src\startup_CMSDK_CM0.s
|
||||
Uses
|
||||
At line 167 in file ..\src\startup_CMSDK_CM0.s
|
||||
Comment: KEY1 used once
|
||||
KEY10 00000000
|
||||
|
||||
Symbol: KEY10
|
||||
Definitions
|
||||
At line 237 in file ..\src\startup_CMSDK_CM0.s
|
||||
Uses
|
||||
At line 239 in file ..\src\startup_CMSDK_CM0.s
|
||||
Comment: KEY10 used once
|
||||
KEY11 00000000
|
||||
|
||||
Symbol: KEY11
|
||||
Definitions
|
||||
At line 245 in file ..\src\startup_CMSDK_CM0.s
|
||||
Uses
|
||||
At line 247 in file ..\src\startup_CMSDK_CM0.s
|
||||
Comment: KEY11 used once
|
||||
KEY12 00000000
|
||||
|
||||
Symbol: KEY12
|
||||
Definitions
|
||||
At line 253 in file ..\src\startup_CMSDK_CM0.s
|
||||
Uses
|
||||
At line 255 in file ..\src\startup_CMSDK_CM0.s
|
||||
Comment: KEY12 used once
|
||||
KEY13 00000000
|
||||
|
||||
Symbol: KEY13
|
||||
Definitions
|
||||
At line 261 in file ..\src\startup_CMSDK_CM0.s
|
||||
Uses
|
||||
At line 263 in file ..\src\startup_CMSDK_CM0.s
|
||||
Comment: KEY13 used once
|
||||
KEY14 00000000
|
||||
|
||||
Symbol: KEY14
|
||||
Definitions
|
||||
At line 269 in file ..\src\startup_CMSDK_CM0.s
|
||||
Uses
|
||||
At line 271 in file ..\src\startup_CMSDK_CM0.s
|
||||
Comment: KEY14 used once
|
||||
KEY15 00000000
|
||||
|
||||
Symbol: KEY15
|
||||
|
||||
|
||||
|
||||
ARM Macro Assembler Page 2 Alphabetic symbol ordering
|
||||
External symbols
|
||||
|
||||
Definitions
|
||||
At line 277 in file ..\src\startup_CMSDK_CM0.s
|
||||
Uses
|
||||
At line 279 in file ..\src\startup_CMSDK_CM0.s
|
||||
Comment: KEY15 used once
|
||||
KEY2 00000000
|
||||
|
||||
Symbol: KEY2
|
||||
Definitions
|
||||
At line 173 in file ..\src\startup_CMSDK_CM0.s
|
||||
Uses
|
||||
At line 175 in file ..\src\startup_CMSDK_CM0.s
|
||||
Comment: KEY2 used once
|
||||
KEY3 00000000
|
||||
|
||||
Symbol: KEY3
|
||||
Definitions
|
||||
At line 181 in file ..\src\startup_CMSDK_CM0.s
|
||||
Uses
|
||||
At line 183 in file ..\src\startup_CMSDK_CM0.s
|
||||
Comment: KEY3 used once
|
||||
KEY4 00000000
|
||||
|
||||
Symbol: KEY4
|
||||
Definitions
|
||||
At line 189 in file ..\src\startup_CMSDK_CM0.s
|
||||
Uses
|
||||
At line 191 in file ..\src\startup_CMSDK_CM0.s
|
||||
Comment: KEY4 used once
|
||||
KEY5 00000000
|
||||
|
||||
Symbol: KEY5
|
||||
Definitions
|
||||
At line 197 in file ..\src\startup_CMSDK_CM0.s
|
||||
Uses
|
||||
At line 199 in file ..\src\startup_CMSDK_CM0.s
|
||||
Comment: KEY5 used once
|
||||
KEY6 00000000
|
||||
|
||||
Symbol: KEY6
|
||||
Definitions
|
||||
At line 205 in file ..\src\startup_CMSDK_CM0.s
|
||||
Uses
|
||||
At line 207 in file ..\src\startup_CMSDK_CM0.s
|
||||
Comment: KEY6 used once
|
||||
KEY7 00000000
|
||||
|
||||
Symbol: KEY7
|
||||
Definitions
|
||||
At line 213 in file ..\src\startup_CMSDK_CM0.s
|
||||
Uses
|
||||
At line 215 in file ..\src\startup_CMSDK_CM0.s
|
||||
Comment: KEY7 used once
|
||||
KEY8 00000000
|
||||
|
||||
Symbol: KEY8
|
||||
Definitions
|
||||
At line 221 in file ..\src\startup_CMSDK_CM0.s
|
||||
Uses
|
||||
|
||||
|
||||
|
||||
ARM Macro Assembler Page 3 Alphabetic symbol ordering
|
||||
External symbols
|
||||
|
||||
At line 223 in file ..\src\startup_CMSDK_CM0.s
|
||||
Comment: KEY8 used once
|
||||
KEY9 00000000
|
||||
|
||||
Symbol: KEY9
|
||||
Definitions
|
||||
At line 229 in file ..\src\startup_CMSDK_CM0.s
|
||||
Uses
|
||||
At line 231 in file ..\src\startup_CMSDK_CM0.s
|
||||
Comment: KEY9 used once
|
||||
RSSIScanHandler 00000000
|
||||
|
||||
Symbol: RSSIScanHandler
|
||||
Definitions
|
||||
At line 133 in file ..\src\startup_CMSDK_CM0.s
|
||||
At line 149 in file ..\src\startup_CMSDK_CM0.s
|
||||
Uses
|
||||
At line 135 in file ..\src\startup_CMSDK_CM0.s
|
||||
At line 151 in file ..\src\startup_CMSDK_CM0.s
|
||||
Comment: RSSIScanHandler used once
|
||||
UARTFM_Demodulated_Data_Dump_Done_Handler 00000000
|
||||
|
||||
Symbol: UARTFM_Demodulated_Data_Dump_Done_Handler
|
||||
Definitions
|
||||
At line 104 in file ..\src\startup_CMSDK_CM0.s
|
||||
At line 120 in file ..\src\startup_CMSDK_CM0.s
|
||||
Uses
|
||||
At line 106 in file ..\src\startup_CMSDK_CM0.s
|
||||
At line 122 in file ..\src\startup_CMSDK_CM0.s
|
||||
Comment: UARTFM_Demodulated_Data_Dump_Done_Handler used once
|
||||
UARTFM_IQ_Dump_Done_Handler 00000000
|
||||
|
||||
Symbol: UARTFM_IQ_Dump_Done_Handler
|
||||
Definitions
|
||||
At line 114 in file ..\src\startup_CMSDK_CM0.s
|
||||
At line 130 in file ..\src\startup_CMSDK_CM0.s
|
||||
Uses
|
||||
At line 116 in file ..\src\startup_CMSDK_CM0.s
|
||||
At line 132 in file ..\src\startup_CMSDK_CM0.s
|
||||
Comment: UARTFM_IQ_Dump_Done_Handler used once
|
||||
UARTHandle 00000000
|
||||
|
||||
Symbol: UARTHandle
|
||||
Definitions
|
||||
At line 124 in file ..\src\startup_CMSDK_CM0.s
|
||||
At line 140 in file ..\src\startup_CMSDK_CM0.s
|
||||
Uses
|
||||
At line 126 in file ..\src\startup_CMSDK_CM0.s
|
||||
At line 142 in file ..\src\startup_CMSDK_CM0.s
|
||||
Comment: UARTHandle used once
|
||||
__main 00000000
|
||||
|
||||
Symbol: __main
|
||||
Definitions
|
||||
At line 92 in file ..\src\startup_CMSDK_CM0.s
|
||||
At line 108 in file ..\src\startup_CMSDK_CM0.s
|
||||
Uses
|
||||
At line 93 in file ..\src\startup_CMSDK_CM0.s
|
||||
At line 96 in file ..\src\startup_CMSDK_CM0.s
|
||||
At line 109 in file ..\src\startup_CMSDK_CM0.s
|
||||
At line 112 in file ..\src\startup_CMSDK_CM0.s
|
||||
|
||||
__use_two_region_memory 00000000
|
||||
|
||||
Symbol: __use_two_region_memory
|
||||
Definitions
|
||||
At line 150 in file ..\src\startup_CMSDK_CM0.s
|
||||
At line 293 in file ..\src\startup_CMSDK_CM0.s
|
||||
Uses
|
||||
None
|
||||
Comment: __use_two_region_memory unused
|
||||
6 symbols
|
||||
361 symbols in table
|
||||
|
||||
|
||||
|
||||
ARM Macro Assembler Page 4 Alphabetic symbol ordering
|
||||
External symbols
|
||||
|
||||
22 symbols
|
||||
393 symbols in table
|
||||
|
||||
BIN
keil/MMC.axf
BIN
keil/MMC.axf
Binary file not shown.
@ -22,43 +22,29 @@ Dialog DLL: TARMCM1.DLL V1.14.4.0
|
||||
|
||||
<h2>Project:</h2>
|
||||
D:\Documents\MMC\keil\MMC.uvprojx
|
||||
Project File Date: 06/25/2022
|
||||
Project File Date: 06/29/2022
|
||||
|
||||
<h2>Output:</h2>
|
||||
*** Using Compiler 'V5.06 update 7 (build 960)', folder: 'D:\Keil_v5\ARM\ARMCC\Bin'
|
||||
Rebuild target 'Target 1'
|
||||
assembling startup_CMSDK_CM0.s...
|
||||
compiling main.c...
|
||||
..\src\code_def.h(72): warning: #1-D: last line of file ends without a newline
|
||||
void RSSI_scan_cmd(void);
|
||||
..\src\main.c(11): warning: #177-D: variable "string" was declared but never referenced
|
||||
char string[32] = {0};
|
||||
..\src\main.c(13): warning: #177-D: variable "MSI_SPI_Data" was declared but never referenced
|
||||
unsigned int MSI_SPI_Data= 0;
|
||||
..\src\main.c(14): warning: #177-D: variable "ChannelControlDisplay" was declared but never referenced
|
||||
ChannelControlType ChannelControlDisplay;
|
||||
..\src\main.c: 4 warnings, 0 errors
|
||||
compiling auxiliary.c...
|
||||
..\src\code_def.h(72): warning: #1-D: last line of file ends without a newline
|
||||
void RSSI_scan_cmd(void);
|
||||
..\src\auxiliary.c(9): warning: #550-D: variable "isNegative" was set but never used
|
||||
int isNegative = 0;
|
||||
..\src\auxiliary.c: 2 warnings, 0 errors
|
||||
compiling code_def.c...
|
||||
..\src\code_def.h(72): warning: #1-D: last line of file ends without a newline
|
||||
void RSSI_scan_cmd(void);
|
||||
..\src\code_def.c: 1 warning, 0 errors
|
||||
..\src\auxiliary.c: 1 warning, 0 errors
|
||||
compiling channelSelection_control.c...
|
||||
..\src\code_def.h(72): warning: #1-D: last line of file ends without a newline
|
||||
void RSSI_scan_cmd(void);
|
||||
..\src\channelSelection_control.c: 1 warning, 0 errors
|
||||
compiling code_def.c...
|
||||
..\src\code_def.c(228): warning: #177-D: variable "j" was declared but never referenced
|
||||
int j;
|
||||
..\src\code_def.c: 1 warning, 0 errors
|
||||
linking...
|
||||
.\MMC.axf: Warning: L6305W: Image does not have an entry point. (Not specified or not set due to multiple choices.)
|
||||
Program Size: Code=10492 RO-data=176 RW-data=40 ZI-data=10664
|
||||
Program Size: Code=12384 RO-data=240 RW-data=40 ZI-data=10920
|
||||
Finished: 0 information, 1 warning and 0 error messages.
|
||||
After Build - User command #1: fromelf -cvf .\MMC.axf --vhx --32x1 -o MMC.hex
|
||||
After Build - User command #2: fromelf -cvf .\MMC.axf -o MMC.txt
|
||||
".\MMC.axf" - 0 Error(s), 9 Warning(s).
|
||||
".\MMC.axf" - 0 Error(s), 3 Warning(s).
|
||||
|
||||
<h2>Software Packages used:</h2>
|
||||
|
||||
|
||||
2663
keil/MMC.hex
2663
keil/MMC.hex
File diff suppressed because it is too large
Load Diff
1110
keil/MMC.htm
1110
keil/MMC.htm
File diff suppressed because it is too large
Load Diff
9625
keil/MMC.txt
9625
keil/MMC.txt
File diff suppressed because it is too large
Load Diff
File diff suppressed because one or more lines are too long
@ -173,12 +173,12 @@
|
||||
<Ww>
|
||||
<count>4</count>
|
||||
<WinNumber>1</WinNumber>
|
||||
<ItemText>i </ItemText>
|
||||
<ItemText>rssilist[rssi_index].RSSI</ItemText>
|
||||
</Ww>
|
||||
<Ww>
|
||||
<count>5</count>
|
||||
<WinNumber>1</WinNumber>
|
||||
<ItemText>rssilist[rssi_index].RSSI</ItemText>
|
||||
<ItemText>channelcontrollist</ItemText>
|
||||
</Ww>
|
||||
</WatchWindow1>
|
||||
<Tracepoint>
|
||||
|
||||
@ -1,21 +1,21 @@
|
||||
Dependencies for Project 'MMC', Target 'Target 1': (DO NOT MODIFY !)
|
||||
CompilerVersion: 5060960::V5.06 update 7 (build 960)::.\ARMCC
|
||||
F (..\src\auxiliary.c)(0x6288D9F3)(-c --cpu Cortex-M0 -D__EVAL -g -O0 --apcs=interwork --split_sections
-IC:\Users\JefferyLi\AppData\Local\Arm\Packs\Keil\V2M-MPS2_CMx_BSP\1.8.0\Device\CMSDK_CM0\Include
-D__UVISION_VERSION="536" -DCMSDK_CM0
-o .\auxiliary.o --omf_browse .\auxiliary.crf --depend .\auxiliary.d)
|
||||
I (..\src\code_def.h)(0x62B7A918)
|
||||
I (..\src\code_def.h)(0x62BB11B0)
|
||||
I (D:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x6025237E)
|
||||
I (D:\Keil_v5\ARM\ARMCC\include\string.h)(0x6025237E)
|
||||
F (..\src\code_def.c)(0x62B7F1D8)(-c --cpu Cortex-M0 -D__EVAL -g -O0 --apcs=interwork --split_sections
-IC:\Users\JefferyLi\AppData\Local\Arm\Packs\Keil\V2M-MPS2_CMx_BSP\1.8.0\Device\CMSDK_CM0\Include
-D__UVISION_VERSION="536" -DCMSDK_CM0
-o .\code_def.o --omf_browse .\code_def.crf --depend .\code_def.d)
|
||||
I (..\src\code_def.h)(0x62B7A918)
|
||||
F (..\src\code_def.c)(0x62BBD34E)(-c --cpu Cortex-M0 -D__EVAL -g -O0 --apcs=interwork --split_sections
-IC:\Users\JefferyLi\AppData\Local\Arm\Packs\Keil\V2M-MPS2_CMx_BSP\1.8.0\Device\CMSDK_CM0\Include
-D__UVISION_VERSION="536" -DCMSDK_CM0
-o .\code_def.o --omf_browse .\code_def.crf --depend .\code_def.d)
|
||||
I (..\src\code_def.h)(0x62BB11B0)
|
||||
I (D:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x6025237E)
|
||||
I (D:\Keil_v5\ARM\ARMCC\include\string.h)(0x6025237E)
|
||||
I (D:\Keil_v5\ARM\ARMCC\include\math.h)(0x60252378)
|
||||
F (..\src\code_def.h)(0x62B7A918)()
|
||||
F (..\src\main.c)(0x62B7DAD7)(-c --cpu Cortex-M0 -D__EVAL -g -O0 --apcs=interwork --split_sections
-IC:\Users\JefferyLi\AppData\Local\Arm\Packs\Keil\V2M-MPS2_CMx_BSP\1.8.0\Device\CMSDK_CM0\Include
-D__UVISION_VERSION="536" -DCMSDK_CM0
-o .\main.o --omf_browse .\main.crf --depend .\main.d)
|
||||
I (..\src\code_def.h)(0x62B7A918)
|
||||
F (..\src\code_def.h)(0x62BB11B0)()
|
||||
F (..\src\main.c)(0x62B85C66)(-c --cpu Cortex-M0 -D__EVAL -g -O0 --apcs=interwork --split_sections
-IC:\Users\JefferyLi\AppData\Local\Arm\Packs\Keil\V2M-MPS2_CMx_BSP\1.8.0\Device\CMSDK_CM0\Include
-D__UVISION_VERSION="536" -DCMSDK_CM0
-o .\main.o --omf_browse .\main.crf --depend .\main.d)
|
||||
I (..\src\code_def.h)(0x62BB11B0)
|
||||
I (D:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x6025237E)
|
||||
I (D:\Keil_v5\ARM\ARMCC\include\string.h)(0x6025237E)
|
||||
F (..\src\startup_CMSDK_CM0.s)(0x62B69773)(--cpu Cortex-M0 --pd "__EVAL SETA 1" -g --apcs=interwork
-IC:\Users\JefferyLi\AppData\Local\Arm\Packs\Keil\V2M-MPS2_CMx_BSP\1.8.0\Device\CMSDK_CM0\Include
--pd "__UVISION_VERSION SETA 536" --pd "CMSDK_CM0 SETA 1"
--list .\listings\startup_cmsdk_cm0.lst --xref -o .\startup_cmsdk_cm0.o --depend .\startup_cmsdk_cm0.d)
|
||||
F (..\src\channelSelection_control.c)(0x62B7014F)(-c --cpu Cortex-M0 -D__EVAL -g -O0 --apcs=interwork --split_sections
-IC:\Users\JefferyLi\AppData\Local\Arm\Packs\Keil\V2M-MPS2_CMx_BSP\1.8.0\Device\CMSDK_CM0\Include
-D__UVISION_VERSION="536" -DCMSDK_CM0
-o .\channelselection_control.o --omf_browse .\channelselection_control.crf --depend .\channelselection_control.d)
|
||||
I (..\src\code_def.h)(0x62B7A918)
|
||||
F (..\src\startup_CMSDK_CM0.s)(0x62B85B7A)(--cpu Cortex-M0 --pd "__EVAL SETA 1" -g --apcs=interwork
-IC:\Users\JefferyLi\AppData\Local\Arm\Packs\Keil\V2M-MPS2_CMx_BSP\1.8.0\Device\CMSDK_CM0\Include
--pd "__UVISION_VERSION SETA 536" --pd "CMSDK_CM0 SETA 1"
--list .\listings\startup_cmsdk_cm0.lst --xref -o .\startup_cmsdk_cm0.o --depend .\startup_cmsdk_cm0.d)
|
||||
F (..\src\channelSelection_control.c)(0x62BBB5B7)(-c --cpu Cortex-M0 -D__EVAL -g -O0 --apcs=interwork --split_sections
-IC:\Users\JefferyLi\AppData\Local\Arm\Packs\Keil\V2M-MPS2_CMx_BSP\1.8.0\Device\CMSDK_CM0\Include
-D__UVISION_VERSION="536" -DCMSDK_CM0
-o .\channelselection_control.o --omf_browse .\channelselection_control.crf --depend .\channelselection_control.d)
|
||||
I (..\src\code_def.h)(0x62BB11B0)
|
||||
I (D:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x6025237E)
|
||||
I (D:\Keil_v5\ARM\ARMCC\include\string.h)(0x6025237E)
|
||||
|
||||
16
keil/MMC_sct.Bak
Normal file
16
keil/MMC_sct.Bak
Normal file
@ -0,0 +1,16 @@
|
||||
; *************************************************************
|
||||
; *** Scatter-Loading Description File generated by uVision ***
|
||||
; *************************************************************
|
||||
|
||||
LR_IROM1 0x00000000 0x00100000 { ; load region size_region
|
||||
ER_IROM1 0x00000000 0x00100000 { ; load address = execution address
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
.ANY (+XO)
|
||||
}
|
||||
RW_IRAM1 0x20000000 0x00100000 { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
}
|
||||
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
BIN
keil/main.crf
BIN
keil/main.crf
Binary file not shown.
@ -2,7 +2,7 @@
|
||||
<Project Version="1" Path="D:/Documents/MMC/project">
|
||||
<Project_Created_Time>2022-06-25 10:35:14</Project_Created_Time>
|
||||
<TD_Version>5.0.43066</TD_Version>
|
||||
<UCode>00011001</UCode>
|
||||
<UCode>11111100</UCode>
|
||||
<Name>MMC</Name>
|
||||
<HardWare>
|
||||
<Family>EG4</Family>
|
||||
@ -226,6 +226,14 @@
|
||||
<Attr Name="CompileOrder" Val="29"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="../rtl/peripherals/KeyScan.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedInSyn" Val="true"/>
|
||||
<Attr Name="UsedInP&R" Val="true"/>
|
||||
<Attr Name="BelongTo" Val="design_1"/>
|
||||
<Attr Name="CompileOrder" Val="30"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
</Verilog>
|
||||
<Header>
|
||||
<File Path="../rtl/topmodule/header.vh">
|
||||
@ -291,7 +299,7 @@
|
||||
<Configurations>
|
||||
</Configurations>
|
||||
<Project_Settings>
|
||||
<Step_Last_Change>2022-06-26 14:36:01.445</Step_Last_Change>
|
||||
<Step_Last_Change>2022-06-29 12:53:13.536</Step_Last_Change>
|
||||
<Current_Step>60</Current_Step>
|
||||
<Step_Status>true</Step_Status>
|
||||
</Project_Settings>
|
||||
|
||||
BIN
project/MMC.bit
BIN
project/MMC.bit
Binary file not shown.
@ -2,22 +2,22 @@ standard
|
||||
***Report Model: CortexM0_SoC***
|
||||
|
||||
IO Statistics
|
||||
#IO 31
|
||||
#input 4
|
||||
#output 26
|
||||
#IO 39
|
||||
#input 8
|
||||
#output 30
|
||||
#inout 1
|
||||
|
||||
LUT Statistics
|
||||
#Total_luts 9608
|
||||
#lut4 7075
|
||||
#lut5 1631
|
||||
#Total_luts 9828
|
||||
#lut4 7291
|
||||
#lut5 1581
|
||||
#lut6 0
|
||||
#lut5_mx41 0
|
||||
#lut4_alu1b 902
|
||||
#lut4_alu1b 956
|
||||
|
||||
Utilization Statistics
|
||||
#lut 9608 out of 19600 49.02%
|
||||
#reg 1921 out of 19600 9.80%
|
||||
#lut 9828 out of 19600 50.14%
|
||||
#reg 2074 out of 19600 10.58%
|
||||
#le 0
|
||||
#dsp 26 out of 29 89.66%
|
||||
#bram 32 out of 64 50.00%
|
||||
@ -26,7 +26,7 @@ Utilization Statistics
|
||||
#bram32k 0 out of 16 0.00%
|
||||
#dram 1040
|
||||
#adc 1 out of 1 100.00%
|
||||
#pad 31 out of 186 16.67%
|
||||
#pad 39 out of 186 20.97%
|
||||
#ireg 0
|
||||
#oreg 0
|
||||
#treg 0
|
||||
@ -36,9 +36,9 @@ Report Hierarchy Area:
|
||||
+------------------------------------------------------------------------------+
|
||||
|Instance |Module |lut |ripple |seq |bram |dsp |
|
||||
+------------------------------------------------------------------------------+
|
||||
|top |CortexM0_SoC |8706 |902 |1921 |32 |26 |
|
||||
|top |CortexM0_SoC |8872 |956 |2074 |32 |26 |
|
||||
| FM_Display |FM_Display |180 |90 |81 |0 |0 |
|
||||
| FM_HW |FM_HW |3473 |595 |391 |0 |23 |
|
||||
| FM_Demodulation |FM_Demodulation |12 |422 |268 |0 |22 |
|
||||
| u_logic |cortexm0ds_logic |4719 |173 |1301 |0 |3 |
|
||||
| u_logic |cortexm0ds_logic |4791 |173 |1317 |0 |3 |
|
||||
+------------------------------------------------------------------------------+
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<All_Bram_Infos>
|
||||
<Ucode>00011001</Ucode>
|
||||
<Ucode>11111100</Ucode>
|
||||
<AL_PHY_BRAM>
|
||||
<INST_1>
|
||||
<rid>0X0004</rid>
|
||||
@ -1002,11 +1002,11 @@
|
||||
<is_debuggable>y</is_debuggable>
|
||||
<is_initialize>n</is_initialize>
|
||||
<model_type>AL_PHY_BRAM32K</model_type>
|
||||
<name>auto_chipwatcher_0_logicbram_4096x53_sub_000000_000</name>
|
||||
<name>auto_chipwatcher_0_logicbram_4096x48_sub_000000_000</name>
|
||||
<width_a>8</width_a>
|
||||
<width_b>8</width_b>
|
||||
<logic_name>auto_chipwatcher_0_logicbram</logic_name>
|
||||
<logic_width>53</logic_width>
|
||||
<logic_width>48</logic_width>
|
||||
<logic_depth>4096</logic_depth>
|
||||
<sub_bid_info>
|
||||
<address_offset>0</address_offset>
|
||||
@ -1014,7 +1014,7 @@
|
||||
<depth>4096</depth>
|
||||
<width>8</width>
|
||||
<num_section>1</num_section>
|
||||
<section_size>53</section_size>
|
||||
<section_size>48</section_size>
|
||||
<width_per_section>8</width_per_section>
|
||||
<bytes_in_per_section>1</bytes_in_per_section>
|
||||
<working_mode>
|
||||
@ -1033,11 +1033,11 @@
|
||||
<is_debuggable>y</is_debuggable>
|
||||
<is_initialize>n</is_initialize>
|
||||
<model_type>AL_PHY_BRAM32K</model_type>
|
||||
<name>auto_chipwatcher_0_logicbram_4096x53_sub_000000_008</name>
|
||||
<name>auto_chipwatcher_0_logicbram_4096x48_sub_000000_008</name>
|
||||
<width_a>8</width_a>
|
||||
<width_b>8</width_b>
|
||||
<logic_name>auto_chipwatcher_0_logicbram</logic_name>
|
||||
<logic_width>53</logic_width>
|
||||
<logic_width>48</logic_width>
|
||||
<logic_depth>4096</logic_depth>
|
||||
<sub_bid_info>
|
||||
<address_offset>0</address_offset>
|
||||
@ -1045,7 +1045,7 @@
|
||||
<depth>4096</depth>
|
||||
<width>8</width>
|
||||
<num_section>1</num_section>
|
||||
<section_size>53</section_size>
|
||||
<section_size>48</section_size>
|
||||
<width_per_section>8</width_per_section>
|
||||
<bytes_in_per_section>1</bytes_in_per_section>
|
||||
<working_mode>
|
||||
@ -1064,11 +1064,11 @@
|
||||
<is_debuggable>y</is_debuggable>
|
||||
<is_initialize>n</is_initialize>
|
||||
<model_type>AL_PHY_BRAM32K</model_type>
|
||||
<name>auto_chipwatcher_0_logicbram_4096x53_sub_000000_016</name>
|
||||
<name>auto_chipwatcher_0_logicbram_4096x48_sub_000000_016</name>
|
||||
<width_a>8</width_a>
|
||||
<width_b>8</width_b>
|
||||
<logic_name>auto_chipwatcher_0_logicbram</logic_name>
|
||||
<logic_width>53</logic_width>
|
||||
<logic_width>48</logic_width>
|
||||
<logic_depth>4096</logic_depth>
|
||||
<sub_bid_info>
|
||||
<address_offset>0</address_offset>
|
||||
@ -1076,7 +1076,7 @@
|
||||
<depth>4096</depth>
|
||||
<width>8</width>
|
||||
<num_section>1</num_section>
|
||||
<section_size>53</section_size>
|
||||
<section_size>48</section_size>
|
||||
<width_per_section>8</width_per_section>
|
||||
<bytes_in_per_section>1</bytes_in_per_section>
|
||||
<working_mode>
|
||||
@ -1095,11 +1095,11 @@
|
||||
<is_debuggable>y</is_debuggable>
|
||||
<is_initialize>n</is_initialize>
|
||||
<model_type>AL_PHY_BRAM32K</model_type>
|
||||
<name>auto_chipwatcher_0_logicbram_4096x53_sub_000000_024</name>
|
||||
<name>auto_chipwatcher_0_logicbram_4096x48_sub_000000_024</name>
|
||||
<width_a>8</width_a>
|
||||
<width_b>8</width_b>
|
||||
<logic_name>auto_chipwatcher_0_logicbram</logic_name>
|
||||
<logic_width>53</logic_width>
|
||||
<logic_width>48</logic_width>
|
||||
<logic_depth>4096</logic_depth>
|
||||
<sub_bid_info>
|
||||
<address_offset>0</address_offset>
|
||||
@ -1107,7 +1107,7 @@
|
||||
<depth>4096</depth>
|
||||
<width>8</width>
|
||||
<num_section>1</num_section>
|
||||
<section_size>53</section_size>
|
||||
<section_size>48</section_size>
|
||||
<width_per_section>8</width_per_section>
|
||||
<bytes_in_per_section>1</bytes_in_per_section>
|
||||
<working_mode>
|
||||
@ -1126,11 +1126,11 @@
|
||||
<is_debuggable>y</is_debuggable>
|
||||
<is_initialize>n</is_initialize>
|
||||
<model_type>AL_PHY_BRAM32K</model_type>
|
||||
<name>auto_chipwatcher_0_logicbram_4096x53_sub_000000_032</name>
|
||||
<name>auto_chipwatcher_0_logicbram_4096x48_sub_000000_032</name>
|
||||
<width_a>8</width_a>
|
||||
<width_b>8</width_b>
|
||||
<logic_name>auto_chipwatcher_0_logicbram</logic_name>
|
||||
<logic_width>53</logic_width>
|
||||
<logic_width>48</logic_width>
|
||||
<logic_depth>4096</logic_depth>
|
||||
<sub_bid_info>
|
||||
<address_offset>0</address_offset>
|
||||
@ -1138,7 +1138,7 @@
|
||||
<depth>4096</depth>
|
||||
<width>8</width>
|
||||
<num_section>1</num_section>
|
||||
<section_size>53</section_size>
|
||||
<section_size>48</section_size>
|
||||
<width_per_section>8</width_per_section>
|
||||
<bytes_in_per_section>1</bytes_in_per_section>
|
||||
<working_mode>
|
||||
@ -1157,11 +1157,11 @@
|
||||
<is_debuggable>y</is_debuggable>
|
||||
<is_initialize>n</is_initialize>
|
||||
<model_type>AL_PHY_BRAM32K</model_type>
|
||||
<name>auto_chipwatcher_0_logicbram_4096x53_sub_000000_040</name>
|
||||
<name>auto_chipwatcher_0_logicbram_4096x48_sub_000000_040</name>
|
||||
<width_a>8</width_a>
|
||||
<width_b>8</width_b>
|
||||
<logic_name>auto_chipwatcher_0_logicbram</logic_name>
|
||||
<logic_width>53</logic_width>
|
||||
<logic_width>48</logic_width>
|
||||
<logic_depth>4096</logic_depth>
|
||||
<sub_bid_info>
|
||||
<address_offset>0</address_offset>
|
||||
@ -1169,7 +1169,7 @@
|
||||
<depth>4096</depth>
|
||||
<width>8</width>
|
||||
<num_section>1</num_section>
|
||||
<section_size>53</section_size>
|
||||
<section_size>48</section_size>
|
||||
<width_per_section>8</width_per_section>
|
||||
<bytes_in_per_section>1</bytes_in_per_section>
|
||||
<working_mode>
|
||||
@ -1182,36 +1182,5 @@
|
||||
</working_mode>
|
||||
</sub_bid_info>
|
||||
</INST_6>
|
||||
<INST_7>
|
||||
<rid>0X003C</rid>
|
||||
<wid>0X003C</wid>
|
||||
<is_debuggable>y</is_debuggable>
|
||||
<is_initialize>n</is_initialize>
|
||||
<model_type>AL_PHY_BRAM32K</model_type>
|
||||
<name>auto_chipwatcher_0_logicbram_4096x53_sub_000000_048</name>
|
||||
<width_a>8</width_a>
|
||||
<width_b>8</width_b>
|
||||
<logic_name>auto_chipwatcher_0_logicbram</logic_name>
|
||||
<logic_width>53</logic_width>
|
||||
<logic_depth>4096</logic_depth>
|
||||
<sub_bid_info>
|
||||
<address_offset>0</address_offset>
|
||||
<data_offset>48</data_offset>
|
||||
<depth>4096</depth>
|
||||
<width>5</width>
|
||||
<num_section>1</num_section>
|
||||
<section_size>53</section_size>
|
||||
<width_per_section>5</width_per_section>
|
||||
<bytes_in_per_section>1</bytes_in_per_section>
|
||||
<working_mode>
|
||||
<address_step>1</address_step>
|
||||
<depth>4096</depth>
|
||||
<mode_type>113</mode_type>
|
||||
<width>8</width>
|
||||
<num_byte>1</num_byte>
|
||||
<ecc>0</ecc>
|
||||
</working_mode>
|
||||
</sub_bid_info>
|
||||
</INST_7>
|
||||
</AL_PHY_BRAM32K>
|
||||
</All_Bram_Infos>
|
||||
|
||||
@ -2,30 +2,30 @@ standard
|
||||
***Report Model: CortexM0_SoC***
|
||||
|
||||
IO Statistics
|
||||
#IO 31
|
||||
#input 4
|
||||
#output 26
|
||||
#IO 39
|
||||
#input 8
|
||||
#output 30
|
||||
#inout 1
|
||||
|
||||
Utilization Statistics
|
||||
#lut 17306 out of 19600 88.30%
|
||||
#reg 2390 out of 19600 12.19%
|
||||
#le 17629
|
||||
#lut only 15239 out of 17629 86.44%
|
||||
#reg only 323 out of 17629 1.83%
|
||||
#lut® 2067 out of 17629 11.72%
|
||||
#lut 17402 out of 19600 88.79%
|
||||
#reg 2517 out of 19600 12.84%
|
||||
#le 17610
|
||||
#lut only 15093 out of 17610 85.71%
|
||||
#reg only 208 out of 17610 1.18%
|
||||
#lut® 2309 out of 17610 13.11%
|
||||
#dsp 26 out of 29 89.66%
|
||||
#bram 32 out of 64 50.00%
|
||||
#bram9k 32
|
||||
#fifo9k 0
|
||||
#bram32k 7 out of 16 43.75%
|
||||
#bram32k 6 out of 16 37.50%
|
||||
#adc 1 out of 1 100.00%
|
||||
#pad 31 out of 186 16.67%
|
||||
#pad 39 out of 186 20.97%
|
||||
#ireg 0
|
||||
#oreg 0
|
||||
#treg 0
|
||||
#pll 2 out of 4 50.00%
|
||||
#gclk 13 out of 16 81.25%
|
||||
#gclk 14 out of 16 87.50%
|
||||
|
||||
|
||||
Detailed IO Report
|
||||
@ -35,6 +35,10 @@ Detailed IO Report
|
||||
RXD INPUT F12 LVCMOS33 N/A PULLUP NONE
|
||||
SWCLK INPUT R2 LVCMOS33 N/A PULLUP NONE
|
||||
clk INPUT R7 LVCMOS33 N/A PULLUP NONE
|
||||
col[3] INPUT F10 LVTTL33 N/A PULLUP NONE
|
||||
col[2] INPUT C11 LVTTL33 N/A PULLUP NONE
|
||||
col[1] INPUT D11 LVTTL33 N/A PULLUP NONE
|
||||
col[0] INPUT E11 LVTTL33 N/A PULLUP NONE
|
||||
LED[7] OUTPUT F16 LVCMOS33 8 NONE NONE
|
||||
LED[6] OUTPUT E16 LVCMOS33 8 NONE NONE
|
||||
LED[5] OUTPUT E13 LVCMOS33 8 NONE NONE
|
||||
@ -49,6 +53,10 @@ Detailed IO Report
|
||||
MSI_SDATA OUTPUT N9 LVCMOS33 8 NONE NONE
|
||||
TXD OUTPUT D12 LVCMOS33 8 NONE NONE
|
||||
audio_pwm OUTPUT N8 LVCMOS33 8 NONE NONE
|
||||
row[3] OUTPUT D9 LVTTL33 8 NONE NONE
|
||||
row[2] OUTPUT F9 LVTTL33 8 NONE NONE
|
||||
row[1] OUTPUT C10 LVTTL33 8 NONE NONE
|
||||
row[0] OUTPUT E10 LVTTL33 8 NONE NONE
|
||||
seg[7] OUTPUT C8 LVCMOS33 8 NONE NONE
|
||||
seg[6] OUTPUT A8 LVCMOS33 8 NONE NONE
|
||||
seg[5] OUTPUT B5 LVCMOS33 8 NONE NONE
|
||||
@ -67,20 +75,20 @@ Report Hierarchy Area:
|
||||
+----------------------------------------------------------------------+
|
||||
|Instance |Module |le |lut |ripple |seq |bram |dsp |
|
||||
+----------------------------------------------------------------------+
|
||||
|top |CortexM0_SoC |17629 |16853 |453 |2390 |39 |26 |
|
||||
|top |CortexM0_SoC |17610 |16929 |473 |2517 |38 |26 |
|
||||
+----------------------------------------------------------------------+
|
||||
|
||||
|
||||
DataNet Average Fanout:
|
||||
|
||||
Index Fanout Nets
|
||||
#1 1 15409
|
||||
#2 2 10176
|
||||
#3 3 643
|
||||
#4 4 487
|
||||
#5 5-10 684
|
||||
#6 11-50 472
|
||||
#7 51-100 39
|
||||
#1 1 15657
|
||||
#2 2 10209
|
||||
#3 3 657
|
||||
#4 4 524
|
||||
#5 5-10 653
|
||||
#6 11-50 473
|
||||
#7 51-100 36
|
||||
#8 101-500 9
|
||||
#9 >500 18
|
||||
Average 3.11
|
||||
Average 3.09
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,368 +1,407 @@
|
||||
eagle_s20
|
||||
12 22 609 18220 1000000000 9 0
|
||||
-10.879 0.249 CortexM0_SoC eagle_s20 BG256 Detail 8 1
|
||||
12 22 687 18594 896242330 9 0
|
||||
-13.826 0.304 CortexM0_SoC eagle_s20 BG256 Detail 8 1
|
||||
clock: DeriveClock
|
||||
12 1000000000 18220 4
|
||||
12 896242330 18594 4
|
||||
Setup check
|
||||
22 3
|
||||
Endpoint: FM_HW/FM_Dump_Data_IQ/reg0_b5|FM_HW/FM_Dump_Data_IQ/reg0_b3
|
||||
22 -10.879000 40816291 3
|
||||
Timing path: u_logic/_al_u2680|u_logic/Vzupw6_reg.clk->FM_HW/FM_Dump_Data_IQ/reg0_b5|FM_HW/FM_Dump_Data_IQ/reg0_b3
|
||||
u_logic/_al_u2680|u_logic/Vzupw6_reg.clk
|
||||
FM_HW/FM_Dump_Data_IQ/reg0_b5|FM_HW/FM_Dump_Data_IQ/reg0_b3
|
||||
24 -10.879000 19.884000 30.763000 20 20
|
||||
u_logic/Vzupw6 u_logic/_al_u4224|u_logic/_al_u121.c[0]
|
||||
u_logic/Vo3ju6_lutinv u_logic/_al_u1992|u_logic/_al_u2497.a[0]
|
||||
u_logic/_al_u2497_o u_logic/_al_u2340|u_logic/_al_u2499.b[0]
|
||||
u_logic/_al_u2499_o u_logic/_al_u2508|u_logic/_al_u1569.a[1]
|
||||
u_logic/_al_u2508_o u_logic/_al_u2509|u_logic/_al_u4626.d[1]
|
||||
u_logic/_al_u2509_o u_logic/_al_u2510|u_logic/W8hbx6_reg.d[1]
|
||||
u_logic/_al_u2510_o u_logic/_al_u2587|u_logic/L6lax6_reg.d[1]
|
||||
u_logic/_al_u2587_o u_logic/_al_u2588|u_logic/T5yax6_reg.b[1]
|
||||
u_logic/R0ghu6 u_logic/add2/ucin_al_u4737.b[0]
|
||||
u_logic/N5fpw6[3] u_logic/_al_u2550|u_logic/_al_u2560.d[0]
|
||||
u_logic/_al_u2560_o u_logic/_al_u2561|u_logic/_al_u2551.b[1]
|
||||
u_logic/_al_u2561_o u_logic/_al_u4281|RAMDATA_Interface/reg0_b2.b[0]
|
||||
HADDR[4] FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_r79_c1_m0.c[1]
|
||||
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_i79_005 FM_HW/_al_u2796|FM_HW/_al_u3251.b[1]
|
||||
FM_HW/_al_u2796_o FM_HW/_al_u2606|FM_HW/_al_u2797.c[0]
|
||||
FM_HW/_al_u2797_o FM_HW/_al_u2798.c[1]
|
||||
FM_HW/_al_u2798_o FM_HW/_al_u3903|FM_HW/_al_u2801.a[0]
|
||||
FM_HW/_al_u2801_o FM_HW/_al_u1343|FM_HW/_al_u2813.b[0]
|
||||
FM_HW/_al_u2813_o FM_HW/FM_Demodulation/reg5_b113.b[0]
|
||||
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_mux_b5/B7_0 FM_HW/FM_Dump_Data_IQ/reg0_b5|FM_HW/FM_Dump_Data_IQ/reg0_b3.a[1]
|
||||
Endpoint: FM_HW/FM_Dump_Data_IQ/reg0_b1|FM_HW/FM_Dump_Data_IQ/reg0_b4
|
||||
22 -13.826000 48997858 3
|
||||
Timing path: u_logic/P5vpw6_reg.clk->FM_HW/FM_Dump_Data_IQ/reg0_b1|FM_HW/FM_Dump_Data_IQ/reg0_b4
|
||||
u_logic/P5vpw6_reg.clk
|
||||
FM_HW/FM_Dump_Data_IQ/reg0_b1|FM_HW/FM_Dump_Data_IQ/reg0_b4
|
||||
24 -13.826000 19.884000 33.710000 24 24
|
||||
u_logic/P5vpw6 cw_top/wrapper_cwc_top/trigger_inst/HAS_BUS_DETECTOR$BUS_DETECTOR[0]$bus_detector_inst1/reg0_b7|cw_top/wrapper_cwc_top/trigger_inst/HAS_BUS_DETECTOR$BUS_DETECTOR[0]$bus_detector_inst1/reg0_b6.b[0]
|
||||
u_logic/Llaow6_lutinv u_logic/_al_u1671|u_logic/_al_u2549.a[0]
|
||||
u_logic/_al_u2549_o u_logic/_al_u2551|u_logic/Fpnpw6_reg.a[1]
|
||||
u_logic/_al_u2551_o u_logic/_al_u2552.a[1]
|
||||
u_logic/_al_u2552_o u_logic/_al_u2556|u_logic/_al_u1730.a[1]
|
||||
u_logic/_al_u2556_o u_logic/_al_u2563|u_logic/_al_u159.a[1]
|
||||
u_logic/_al_u2563_o u_logic/_al_u2564|u_logic/_al_u4431.d[1]
|
||||
u_logic/_al_u2564_o u_logic/_al_u2565|u_logic/_al_u2892.d[1]
|
||||
u_logic/_al_u2565_o u_logic/_al_u2566|u_logic/_al_u2882.d[1]
|
||||
u_logic/_al_u2566_o u_logic/_al_u2641|u_logic/_al_u2759.d[1]
|
||||
u_logic/Vtzhu6 u_logic/_al_u2643.d[0]
|
||||
u_logic/R0ghu6 u_logic/add2/ucin_al_u4809.b[0]
|
||||
u_logic/add2/c3 u_logic/add2/u3_al_u4810.fci
|
||||
u_logic/N5fpw6[4] u_logic/_al_u4753|u_logic/_al_u2604.c[0]
|
||||
u_logic/_al_u2604_o u_logic/_al_u2605|u_logic/Ibqpw6_reg.d[1]
|
||||
u_logic/_al_u2605_o u_logic/_al_u3990|RAMDATA_Interface/reg0_b3.b[0]
|
||||
HADDR[5] FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_r478_c1_m0.d[0]
|
||||
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_i478_004 FM_HW/_al_u3089|FM_HW/_al_u3091.b[0]
|
||||
FM_HW/_al_u3091_o FM_HW/_al_u3090|FM_HW/_al_u3092.c[0]
|
||||
FM_HW/_al_u3092_o FM_HW/_al_u2670|FM_HW/_al_u3093.b[0]
|
||||
FM_HW/_al_u3093_o FM_HW/_al_u1562|FM_HW/_al_u3094.c[0]
|
||||
FM_HW/_al_u3094_o FM_HW/_al_u3115.a[1]
|
||||
FM_HW/_al_u3115_o FM_HW/_al_u1583|FM_HW/FM_Demodulation/reg5_b57.a[0]
|
||||
FM_HW/_al_u3159_o FM_HW/FM_Dump_Data_IQ/reg0_b1|FM_HW/FM_Dump_Data_IQ/reg0_b4.a[0]
|
||||
|
||||
Timing path: u_logic/_al_u2680|u_logic/Vzupw6_reg.clk->FM_HW/FM_Dump_Data_IQ/reg0_b5|FM_HW/FM_Dump_Data_IQ/reg0_b3
|
||||
u_logic/_al_u2680|u_logic/Vzupw6_reg.clk
|
||||
FM_HW/FM_Dump_Data_IQ/reg0_b5|FM_HW/FM_Dump_Data_IQ/reg0_b3
|
||||
89 -10.879000 19.884000 30.763000 20 20
|
||||
u_logic/Vzupw6 u_logic/_al_u4224|u_logic/_al_u121.c[0]
|
||||
u_logic/Vo3ju6_lutinv u_logic/_al_u1992|u_logic/_al_u2497.a[0]
|
||||
u_logic/_al_u2497_o u_logic/_al_u2340|u_logic/_al_u2499.b[0]
|
||||
u_logic/_al_u2499_o u_logic/_al_u2508|u_logic/_al_u1569.a[1]
|
||||
u_logic/_al_u2508_o u_logic/_al_u2509|u_logic/_al_u4626.d[1]
|
||||
u_logic/_al_u2509_o u_logic/_al_u2510|u_logic/W8hbx6_reg.d[1]
|
||||
u_logic/_al_u2510_o u_logic/_al_u2587|u_logic/L6lax6_reg.d[1]
|
||||
u_logic/_al_u2587_o u_logic/_al_u2588|u_logic/T5yax6_reg.b[1]
|
||||
u_logic/R0ghu6 u_logic/add2/ucin_al_u4737.b[0]
|
||||
u_logic/N5fpw6[3] u_logic/_al_u2550|u_logic/_al_u2560.d[0]
|
||||
u_logic/_al_u2560_o u_logic/_al_u2561|u_logic/_al_u2551.b[1]
|
||||
u_logic/_al_u2561_o u_logic/_al_u4281|RAMDATA_Interface/reg0_b2.b[0]
|
||||
HADDR[4] FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_r79_c1_m0.c[1]
|
||||
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_i79_005 FM_HW/_al_u2796|FM_HW/_al_u3251.b[1]
|
||||
FM_HW/_al_u2796_o FM_HW/_al_u2606|FM_HW/_al_u2797.c[0]
|
||||
FM_HW/_al_u2797_o FM_HW/_al_u2798.c[0]
|
||||
FM_HW/_al_u2798_o FM_HW/_al_u3903|FM_HW/_al_u2801.a[0]
|
||||
FM_HW/_al_u2801_o FM_HW/_al_u1343|FM_HW/_al_u2813.b[0]
|
||||
FM_HW/_al_u2813_o FM_HW/FM_Demodulation/reg5_b113.b[0]
|
||||
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_mux_b5/B7_0 FM_HW/FM_Dump_Data_IQ/reg0_b5|FM_HW/FM_Dump_Data_IQ/reg0_b3.a[1]
|
||||
Timing path: u_logic/P5vpw6_reg.clk->FM_HW/FM_Dump_Data_IQ/reg0_b1|FM_HW/FM_Dump_Data_IQ/reg0_b4
|
||||
u_logic/P5vpw6_reg.clk
|
||||
FM_HW/FM_Dump_Data_IQ/reg0_b1|FM_HW/FM_Dump_Data_IQ/reg0_b4
|
||||
97 -13.826000 19.884000 33.710000 24 24
|
||||
u_logic/P5vpw6 cw_top/wrapper_cwc_top/trigger_inst/HAS_BUS_DETECTOR$BUS_DETECTOR[0]$bus_detector_inst1/reg0_b7|cw_top/wrapper_cwc_top/trigger_inst/HAS_BUS_DETECTOR$BUS_DETECTOR[0]$bus_detector_inst1/reg0_b6.b[0]
|
||||
u_logic/Llaow6_lutinv u_logic/_al_u1671|u_logic/_al_u2549.a[0]
|
||||
u_logic/_al_u2549_o u_logic/_al_u2551|u_logic/Fpnpw6_reg.a[1]
|
||||
u_logic/_al_u2551_o u_logic/_al_u2552.a[0]
|
||||
u_logic/_al_u2552_o u_logic/_al_u2556|u_logic/_al_u1730.a[1]
|
||||
u_logic/_al_u2556_o u_logic/_al_u2563|u_logic/_al_u159.a[1]
|
||||
u_logic/_al_u2563_o u_logic/_al_u2564|u_logic/_al_u4431.d[1]
|
||||
u_logic/_al_u2564_o u_logic/_al_u2565|u_logic/_al_u2892.d[1]
|
||||
u_logic/_al_u2565_o u_logic/_al_u2566|u_logic/_al_u2882.d[1]
|
||||
u_logic/_al_u2566_o u_logic/_al_u2641|u_logic/_al_u2759.d[1]
|
||||
u_logic/Vtzhu6 u_logic/_al_u2643.d[0]
|
||||
u_logic/R0ghu6 u_logic/add2/ucin_al_u4809.b[0]
|
||||
u_logic/add2/c3 u_logic/add2/u3_al_u4810.fci
|
||||
u_logic/N5fpw6[4] u_logic/_al_u4753|u_logic/_al_u2604.c[0]
|
||||
u_logic/_al_u2604_o u_logic/_al_u2605|u_logic/Ibqpw6_reg.d[1]
|
||||
u_logic/_al_u2605_o u_logic/_al_u3990|RAMDATA_Interface/reg0_b3.b[0]
|
||||
HADDR[5] FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_r478_c1_m0.d[0]
|
||||
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_i478_004 FM_HW/_al_u3089|FM_HW/_al_u3091.b[0]
|
||||
FM_HW/_al_u3091_o FM_HW/_al_u3090|FM_HW/_al_u3092.c[0]
|
||||
FM_HW/_al_u3092_o FM_HW/_al_u2670|FM_HW/_al_u3093.b[0]
|
||||
FM_HW/_al_u3093_o FM_HW/_al_u1562|FM_HW/_al_u3094.c[0]
|
||||
FM_HW/_al_u3094_o FM_HW/_al_u3115.a[1]
|
||||
FM_HW/_al_u3115_o FM_HW/_al_u1583|FM_HW/FM_Demodulation/reg5_b57.a[0]
|
||||
FM_HW/_al_u3159_o FM_HW/FM_Dump_Data_IQ/reg0_b1|FM_HW/FM_Dump_Data_IQ/reg0_b4.a[0]
|
||||
|
||||
Timing path: u_logic/_al_u2662|u_logic/Ufopw6_reg.clk->FM_HW/FM_Dump_Data_IQ/reg0_b5|FM_HW/FM_Dump_Data_IQ/reg0_b3
|
||||
u_logic/_al_u2662|u_logic/Ufopw6_reg.clk
|
||||
FM_HW/FM_Dump_Data_IQ/reg0_b5|FM_HW/FM_Dump_Data_IQ/reg0_b3
|
||||
154 -10.864000 19.884000 30.748000 20 20
|
||||
u_logic/Ufopw6 u_logic/_al_u4224|u_logic/_al_u121.d[0]
|
||||
u_logic/Vo3ju6_lutinv u_logic/_al_u1992|u_logic/_al_u2497.a[0]
|
||||
u_logic/_al_u2497_o u_logic/_al_u2340|u_logic/_al_u2499.b[0]
|
||||
u_logic/_al_u2499_o u_logic/_al_u2508|u_logic/_al_u1569.a[1]
|
||||
u_logic/_al_u2508_o u_logic/_al_u2509|u_logic/_al_u4626.d[1]
|
||||
u_logic/_al_u2509_o u_logic/_al_u2510|u_logic/W8hbx6_reg.d[1]
|
||||
u_logic/_al_u2510_o u_logic/_al_u2587|u_logic/L6lax6_reg.d[1]
|
||||
u_logic/_al_u2587_o u_logic/_al_u2588|u_logic/T5yax6_reg.b[1]
|
||||
u_logic/R0ghu6 u_logic/add2/ucin_al_u4737.b[0]
|
||||
u_logic/N5fpw6[3] u_logic/_al_u2550|u_logic/_al_u2560.d[0]
|
||||
u_logic/_al_u2560_o u_logic/_al_u2561|u_logic/_al_u2551.b[1]
|
||||
u_logic/_al_u2561_o u_logic/_al_u4281|RAMDATA_Interface/reg0_b2.b[0]
|
||||
HADDR[4] FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_r79_c1_m0.c[1]
|
||||
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_i79_005 FM_HW/_al_u2796|FM_HW/_al_u3251.b[1]
|
||||
FM_HW/_al_u2796_o FM_HW/_al_u2606|FM_HW/_al_u2797.c[0]
|
||||
FM_HW/_al_u2797_o FM_HW/_al_u2798.c[1]
|
||||
FM_HW/_al_u2798_o FM_HW/_al_u3903|FM_HW/_al_u2801.a[0]
|
||||
FM_HW/_al_u2801_o FM_HW/_al_u1343|FM_HW/_al_u2813.b[0]
|
||||
FM_HW/_al_u2813_o FM_HW/FM_Demodulation/reg5_b113.b[0]
|
||||
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_mux_b5/B7_0 FM_HW/FM_Dump_Data_IQ/reg0_b5|FM_HW/FM_Dump_Data_IQ/reg0_b3.a[1]
|
||||
Timing path: u_logic/P5vpw6_reg.clk->FM_HW/FM_Dump_Data_IQ/reg0_b1|FM_HW/FM_Dump_Data_IQ/reg0_b4
|
||||
u_logic/P5vpw6_reg.clk
|
||||
FM_HW/FM_Dump_Data_IQ/reg0_b1|FM_HW/FM_Dump_Data_IQ/reg0_b4
|
||||
170 -13.826000 19.884000 33.710000 24 24
|
||||
u_logic/P5vpw6 cw_top/wrapper_cwc_top/trigger_inst/HAS_BUS_DETECTOR$BUS_DETECTOR[0]$bus_detector_inst1/reg0_b7|cw_top/wrapper_cwc_top/trigger_inst/HAS_BUS_DETECTOR$BUS_DETECTOR[0]$bus_detector_inst1/reg0_b6.b[0]
|
||||
u_logic/Llaow6_lutinv u_logic/_al_u1671|u_logic/_al_u2549.a[0]
|
||||
u_logic/_al_u2549_o u_logic/_al_u2551|u_logic/Fpnpw6_reg.a[1]
|
||||
u_logic/_al_u2551_o u_logic/_al_u2552.a[1]
|
||||
u_logic/_al_u2552_o u_logic/_al_u2556|u_logic/_al_u1730.a[1]
|
||||
u_logic/_al_u2556_o u_logic/_al_u2563|u_logic/_al_u159.a[1]
|
||||
u_logic/_al_u2563_o u_logic/_al_u2564|u_logic/_al_u4431.d[1]
|
||||
u_logic/_al_u2564_o u_logic/_al_u2565|u_logic/_al_u2892.d[1]
|
||||
u_logic/_al_u2565_o u_logic/_al_u2566|u_logic/_al_u2882.d[1]
|
||||
u_logic/_al_u2566_o u_logic/_al_u2641|u_logic/_al_u2759.d[1]
|
||||
u_logic/Vtzhu6 u_logic/_al_u2643.d[0]
|
||||
u_logic/R0ghu6 u_logic/add2/ucin_al_u4809.b[0]
|
||||
u_logic/add2/c3 u_logic/add2/u3_al_u4810.fci
|
||||
u_logic/N5fpw6[4] u_logic/_al_u4753|u_logic/_al_u2604.c[0]
|
||||
u_logic/_al_u2604_o u_logic/_al_u2605|u_logic/Ibqpw6_reg.d[1]
|
||||
u_logic/_al_u2605_o u_logic/_al_u3990|RAMDATA_Interface/reg0_b3.b[0]
|
||||
HADDR[5] FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_r478_c1_m0.d[0]
|
||||
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_i478_004 FM_HW/_al_u3089|FM_HW/_al_u3091.b[0]
|
||||
FM_HW/_al_u3091_o FM_HW/_al_u3090|FM_HW/_al_u3092.c[0]
|
||||
FM_HW/_al_u3092_o FM_HW/_al_u2670|FM_HW/_al_u3093.b[0]
|
||||
FM_HW/_al_u3093_o FM_HW/_al_u1562|FM_HW/_al_u3094.c[0]
|
||||
FM_HW/_al_u3094_o FM_HW/_al_u3115.a[0]
|
||||
FM_HW/_al_u3115_o FM_HW/_al_u1583|FM_HW/FM_Demodulation/reg5_b57.a[0]
|
||||
FM_HW/_al_u3159_o FM_HW/FM_Dump_Data_IQ/reg0_b1|FM_HW/FM_Dump_Data_IQ/reg0_b4.a[0]
|
||||
|
||||
|
||||
Endpoint: FM_HW/_al_u3093|FM_HW/FM_Dump_Data_IQ/reg0_b4
|
||||
219 -10.773000 47643106 3
|
||||
Timing path: u_logic/_al_u2680|u_logic/Vzupw6_reg.clk->FM_HW/_al_u3093|FM_HW/FM_Dump_Data_IQ/reg0_b4
|
||||
u_logic/_al_u2680|u_logic/Vzupw6_reg.clk
|
||||
FM_HW/_al_u3093|FM_HW/FM_Dump_Data_IQ/reg0_b4
|
||||
221 -10.773000 19.884000 30.657000 20 20
|
||||
u_logic/Vzupw6 u_logic/_al_u4224|u_logic/_al_u121.c[0]
|
||||
u_logic/Vo3ju6_lutinv u_logic/_al_u1992|u_logic/_al_u2497.a[0]
|
||||
u_logic/_al_u2497_o u_logic/_al_u2340|u_logic/_al_u2499.b[0]
|
||||
u_logic/_al_u2499_o u_logic/_al_u2508|u_logic/_al_u1569.a[1]
|
||||
u_logic/_al_u2508_o u_logic/_al_u2509|u_logic/_al_u4626.d[1]
|
||||
u_logic/_al_u2509_o u_logic/_al_u2510|u_logic/W8hbx6_reg.d[1]
|
||||
u_logic/_al_u2510_o u_logic/_al_u2587|u_logic/L6lax6_reg.d[1]
|
||||
u_logic/_al_u2587_o u_logic/_al_u2588|u_logic/T5yax6_reg.b[1]
|
||||
u_logic/R0ghu6 u_logic/add2/ucin_al_u4737.b[0]
|
||||
u_logic/N5fpw6[3] u_logic/_al_u2550|u_logic/_al_u2560.d[0]
|
||||
u_logic/_al_u2560_o u_logic/_al_u2561|u_logic/_al_u2551.b[1]
|
||||
u_logic/_al_u2561_o u_logic/_al_u4281|RAMDATA_Interface/reg0_b2.b[0]
|
||||
HADDR[4] FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_r79_c1_m0.c[0]
|
||||
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_i79_004 FM_HW/_al_u2796|FM_HW/_al_u3251.b[0]
|
||||
FM_HW/_al_u3251_o FM_HW/_al_u2795|FM_HW/_al_u3252.c[0]
|
||||
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_mux_b4/B1_19 FM_HW/_al_u1320|FM_HW/_al_u3255.a[0]
|
||||
FM_HW/_al_u3255_o FM_HW/_al_u3256|FM_HW/_al_u2777.b[1]
|
||||
FM_HW/_al_u3256_o FM_HW/_al_u3267.a[1]
|
||||
FM_HW/_al_u3267_o FM_HW/_al_u2184|FM_HW/_al_u3332.a[0]
|
||||
FM_HW/_al_u3332_o FM_HW/_al_u3093|FM_HW/FM_Dump_Data_IQ/reg0_b4.c[0]
|
||||
Endpoint: FM_HW/_al_u3650|FM_HW/FM_Dump_Data_IQ/reg0_b7
|
||||
243 -13.737000 33724860 3
|
||||
Timing path: u_logic/P5vpw6_reg.clk->FM_HW/_al_u3650|FM_HW/FM_Dump_Data_IQ/reg0_b7
|
||||
u_logic/P5vpw6_reg.clk
|
||||
FM_HW/_al_u3650|FM_HW/FM_Dump_Data_IQ/reg0_b7
|
||||
245 -13.737000 19.884000 33.621000 24 24
|
||||
u_logic/P5vpw6 cw_top/wrapper_cwc_top/trigger_inst/HAS_BUS_DETECTOR$BUS_DETECTOR[0]$bus_detector_inst1/reg0_b7|cw_top/wrapper_cwc_top/trigger_inst/HAS_BUS_DETECTOR$BUS_DETECTOR[0]$bus_detector_inst1/reg0_b6.b[0]
|
||||
u_logic/Llaow6_lutinv u_logic/_al_u1671|u_logic/_al_u2549.a[0]
|
||||
u_logic/_al_u2549_o u_logic/_al_u2551|u_logic/Fpnpw6_reg.a[1]
|
||||
u_logic/_al_u2551_o u_logic/_al_u2552.a[1]
|
||||
u_logic/_al_u2552_o u_logic/_al_u2556|u_logic/_al_u1730.a[1]
|
||||
u_logic/_al_u2556_o u_logic/_al_u2563|u_logic/_al_u159.a[1]
|
||||
u_logic/_al_u2563_o u_logic/_al_u2564|u_logic/_al_u4431.d[1]
|
||||
u_logic/_al_u2564_o u_logic/_al_u2565|u_logic/_al_u2892.d[1]
|
||||
u_logic/_al_u2565_o u_logic/_al_u2566|u_logic/_al_u2882.d[1]
|
||||
u_logic/_al_u2566_o u_logic/_al_u2641|u_logic/_al_u2759.d[1]
|
||||
u_logic/Vtzhu6 u_logic/_al_u2643.d[0]
|
||||
u_logic/R0ghu6 u_logic/add2/ucin_al_u4809.b[0]
|
||||
u_logic/add2/c3 u_logic/add2/u3_al_u4810.fci
|
||||
u_logic/N5fpw6[4] u_logic/_al_u4753|u_logic/_al_u2604.c[0]
|
||||
u_logic/_al_u2604_o u_logic/_al_u2605|u_logic/Ibqpw6_reg.d[1]
|
||||
u_logic/_al_u2605_o u_logic/_al_u3990|RAMDATA_Interface/reg0_b3.b[0]
|
||||
HADDR[5] FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_r399_c1_m1.d[1]
|
||||
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_i399_007 FM_HW/_al_u2331|FM_HW/_al_u2330.b[0]
|
||||
FM_HW/_al_u2330_o FM_HW/_al_u2331|FM_HW/_al_u2330.c[1]
|
||||
FM_HW/_al_u2331_o FM_HW/FM_Demodulation/reg5_b19|FM_HW/FM_Demodulation/reg5_b18.b[1]
|
||||
FM_HW/_al_u2334_o FM_HW/_al_u2338.b[1]
|
||||
FM_HW/_al_u2338_o FM_HW/FM_Demodulation/reg5_b53|FM_HW/FM_Demodulation/reg5_b59.b[1]
|
||||
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_mux_b7/B6_3 FM_HW/_al_u2380|FM_HW/_al_u850.b[1]
|
||||
FM_HW/_al_u2380_o FM_HW/_al_u3650|FM_HW/FM_Dump_Data_IQ/reg0_b7.c[0]
|
||||
|
||||
Timing path: u_logic/_al_u2680|u_logic/Vzupw6_reg.clk->FM_HW/_al_u3093|FM_HW/FM_Dump_Data_IQ/reg0_b4
|
||||
u_logic/_al_u2680|u_logic/Vzupw6_reg.clk
|
||||
FM_HW/_al_u3093|FM_HW/FM_Dump_Data_IQ/reg0_b4
|
||||
286 -10.773000 19.884000 30.657000 20 20
|
||||
u_logic/Vzupw6 u_logic/_al_u4224|u_logic/_al_u121.c[0]
|
||||
u_logic/Vo3ju6_lutinv u_logic/_al_u1992|u_logic/_al_u2497.a[0]
|
||||
u_logic/_al_u2497_o u_logic/_al_u2340|u_logic/_al_u2499.b[0]
|
||||
u_logic/_al_u2499_o u_logic/_al_u2508|u_logic/_al_u1569.a[1]
|
||||
u_logic/_al_u2508_o u_logic/_al_u2509|u_logic/_al_u4626.d[1]
|
||||
u_logic/_al_u2509_o u_logic/_al_u2510|u_logic/W8hbx6_reg.d[1]
|
||||
u_logic/_al_u2510_o u_logic/_al_u2587|u_logic/L6lax6_reg.d[1]
|
||||
u_logic/_al_u2587_o u_logic/_al_u2588|u_logic/T5yax6_reg.b[1]
|
||||
u_logic/R0ghu6 u_logic/add2/ucin_al_u4737.b[0]
|
||||
u_logic/N5fpw6[3] u_logic/_al_u2550|u_logic/_al_u2560.d[0]
|
||||
u_logic/_al_u2560_o u_logic/_al_u2561|u_logic/_al_u2551.b[1]
|
||||
u_logic/_al_u2561_o u_logic/_al_u4281|RAMDATA_Interface/reg0_b2.b[0]
|
||||
HADDR[4] FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_r79_c1_m0.c[0]
|
||||
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_i79_004 FM_HW/_al_u2796|FM_HW/_al_u3251.b[0]
|
||||
FM_HW/_al_u3251_o FM_HW/_al_u2795|FM_HW/_al_u3252.c[0]
|
||||
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_mux_b4/B1_19 FM_HW/_al_u1320|FM_HW/_al_u3255.a[0]
|
||||
FM_HW/_al_u3255_o FM_HW/_al_u3256|FM_HW/_al_u2777.b[1]
|
||||
FM_HW/_al_u3256_o FM_HW/_al_u3267.a[0]
|
||||
FM_HW/_al_u3267_o FM_HW/_al_u2184|FM_HW/_al_u3332.a[0]
|
||||
FM_HW/_al_u3332_o FM_HW/_al_u3093|FM_HW/FM_Dump_Data_IQ/reg0_b4.c[0]
|
||||
Timing path: u_logic/P5vpw6_reg.clk->FM_HW/_al_u3650|FM_HW/FM_Dump_Data_IQ/reg0_b7
|
||||
u_logic/P5vpw6_reg.clk
|
||||
FM_HW/_al_u3650|FM_HW/FM_Dump_Data_IQ/reg0_b7
|
||||
318 -13.737000 19.884000 33.621000 24 24
|
||||
u_logic/P5vpw6 cw_top/wrapper_cwc_top/trigger_inst/HAS_BUS_DETECTOR$BUS_DETECTOR[0]$bus_detector_inst1/reg0_b7|cw_top/wrapper_cwc_top/trigger_inst/HAS_BUS_DETECTOR$BUS_DETECTOR[0]$bus_detector_inst1/reg0_b6.b[0]
|
||||
u_logic/Llaow6_lutinv u_logic/_al_u1671|u_logic/_al_u2549.a[0]
|
||||
u_logic/_al_u2549_o u_logic/_al_u2551|u_logic/Fpnpw6_reg.a[1]
|
||||
u_logic/_al_u2551_o u_logic/_al_u2552.a[0]
|
||||
u_logic/_al_u2552_o u_logic/_al_u2556|u_logic/_al_u1730.a[1]
|
||||
u_logic/_al_u2556_o u_logic/_al_u2563|u_logic/_al_u159.a[1]
|
||||
u_logic/_al_u2563_o u_logic/_al_u2564|u_logic/_al_u4431.d[1]
|
||||
u_logic/_al_u2564_o u_logic/_al_u2565|u_logic/_al_u2892.d[1]
|
||||
u_logic/_al_u2565_o u_logic/_al_u2566|u_logic/_al_u2882.d[1]
|
||||
u_logic/_al_u2566_o u_logic/_al_u2641|u_logic/_al_u2759.d[1]
|
||||
u_logic/Vtzhu6 u_logic/_al_u2643.d[0]
|
||||
u_logic/R0ghu6 u_logic/add2/ucin_al_u4809.b[0]
|
||||
u_logic/add2/c3 u_logic/add2/u3_al_u4810.fci
|
||||
u_logic/N5fpw6[4] u_logic/_al_u4753|u_logic/_al_u2604.c[0]
|
||||
u_logic/_al_u2604_o u_logic/_al_u2605|u_logic/Ibqpw6_reg.d[1]
|
||||
u_logic/_al_u2605_o u_logic/_al_u3990|RAMDATA_Interface/reg0_b3.b[0]
|
||||
HADDR[5] FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_r399_c1_m1.d[1]
|
||||
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_i399_007 FM_HW/_al_u2331|FM_HW/_al_u2330.b[0]
|
||||
FM_HW/_al_u2330_o FM_HW/_al_u2331|FM_HW/_al_u2330.c[1]
|
||||
FM_HW/_al_u2331_o FM_HW/FM_Demodulation/reg5_b19|FM_HW/FM_Demodulation/reg5_b18.b[1]
|
||||
FM_HW/_al_u2334_o FM_HW/_al_u2338.b[1]
|
||||
FM_HW/_al_u2338_o FM_HW/FM_Demodulation/reg5_b53|FM_HW/FM_Demodulation/reg5_b59.b[1]
|
||||
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_mux_b7/B6_3 FM_HW/_al_u2380|FM_HW/_al_u850.b[1]
|
||||
FM_HW/_al_u2380_o FM_HW/_al_u3650|FM_HW/FM_Dump_Data_IQ/reg0_b7.c[0]
|
||||
|
||||
Timing path: u_logic/_al_u2662|u_logic/Ufopw6_reg.clk->FM_HW/_al_u3093|FM_HW/FM_Dump_Data_IQ/reg0_b4
|
||||
u_logic/_al_u2662|u_logic/Ufopw6_reg.clk
|
||||
FM_HW/_al_u3093|FM_HW/FM_Dump_Data_IQ/reg0_b4
|
||||
351 -10.758000 19.884000 30.642000 20 20
|
||||
u_logic/Ufopw6 u_logic/_al_u4224|u_logic/_al_u121.d[0]
|
||||
u_logic/Vo3ju6_lutinv u_logic/_al_u1992|u_logic/_al_u2497.a[0]
|
||||
u_logic/_al_u2497_o u_logic/_al_u2340|u_logic/_al_u2499.b[0]
|
||||
u_logic/_al_u2499_o u_logic/_al_u2508|u_logic/_al_u1569.a[1]
|
||||
u_logic/_al_u2508_o u_logic/_al_u2509|u_logic/_al_u4626.d[1]
|
||||
u_logic/_al_u2509_o u_logic/_al_u2510|u_logic/W8hbx6_reg.d[1]
|
||||
u_logic/_al_u2510_o u_logic/_al_u2587|u_logic/L6lax6_reg.d[1]
|
||||
u_logic/_al_u2587_o u_logic/_al_u2588|u_logic/T5yax6_reg.b[1]
|
||||
u_logic/R0ghu6 u_logic/add2/ucin_al_u4737.b[0]
|
||||
u_logic/N5fpw6[3] u_logic/_al_u2550|u_logic/_al_u2560.d[0]
|
||||
u_logic/_al_u2560_o u_logic/_al_u2561|u_logic/_al_u2551.b[1]
|
||||
u_logic/_al_u2561_o u_logic/_al_u4281|RAMDATA_Interface/reg0_b2.b[0]
|
||||
HADDR[4] FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_r79_c1_m0.c[0]
|
||||
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_i79_004 FM_HW/_al_u2796|FM_HW/_al_u3251.b[0]
|
||||
FM_HW/_al_u3251_o FM_HW/_al_u2795|FM_HW/_al_u3252.c[0]
|
||||
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_mux_b4/B1_19 FM_HW/_al_u1320|FM_HW/_al_u3255.a[0]
|
||||
FM_HW/_al_u3255_o FM_HW/_al_u3256|FM_HW/_al_u2777.b[1]
|
||||
FM_HW/_al_u3256_o FM_HW/_al_u3267.a[1]
|
||||
FM_HW/_al_u3267_o FM_HW/_al_u2184|FM_HW/_al_u3332.a[0]
|
||||
FM_HW/_al_u3332_o FM_HW/_al_u3093|FM_HW/FM_Dump_Data_IQ/reg0_b4.c[0]
|
||||
Timing path: u_logic/P5vpw6_reg.clk->FM_HW/_al_u3650|FM_HW/FM_Dump_Data_IQ/reg0_b7
|
||||
u_logic/P5vpw6_reg.clk
|
||||
FM_HW/_al_u3650|FM_HW/FM_Dump_Data_IQ/reg0_b7
|
||||
391 -13.737000 19.884000 33.621000 24 24
|
||||
u_logic/P5vpw6 cw_top/wrapper_cwc_top/trigger_inst/HAS_BUS_DETECTOR$BUS_DETECTOR[0]$bus_detector_inst1/reg0_b7|cw_top/wrapper_cwc_top/trigger_inst/HAS_BUS_DETECTOR$BUS_DETECTOR[0]$bus_detector_inst1/reg0_b6.b[0]
|
||||
u_logic/Llaow6_lutinv u_logic/_al_u1671|u_logic/_al_u2549.a[0]
|
||||
u_logic/_al_u2549_o u_logic/_al_u2551|u_logic/Fpnpw6_reg.a[1]
|
||||
u_logic/_al_u2551_o u_logic/_al_u2552.a[1]
|
||||
u_logic/_al_u2552_o u_logic/_al_u2556|u_logic/_al_u1730.a[1]
|
||||
u_logic/_al_u2556_o u_logic/_al_u2563|u_logic/_al_u159.a[1]
|
||||
u_logic/_al_u2563_o u_logic/_al_u2564|u_logic/_al_u4431.d[1]
|
||||
u_logic/_al_u2564_o u_logic/_al_u2565|u_logic/_al_u2892.d[1]
|
||||
u_logic/_al_u2565_o u_logic/_al_u2566|u_logic/_al_u2882.d[1]
|
||||
u_logic/_al_u2566_o u_logic/_al_u2641|u_logic/_al_u2759.d[1]
|
||||
u_logic/Vtzhu6 u_logic/_al_u2643.d[0]
|
||||
u_logic/R0ghu6 u_logic/add2/ucin_al_u4809.b[0]
|
||||
u_logic/add2/c3 u_logic/add2/u3_al_u4810.fci
|
||||
u_logic/N5fpw6[4] u_logic/_al_u4753|u_logic/_al_u2604.c[0]
|
||||
u_logic/_al_u2604_o u_logic/_al_u2605|u_logic/Ibqpw6_reg.d[1]
|
||||
u_logic/_al_u2605_o u_logic/_al_u3990|RAMDATA_Interface/reg0_b3.b[0]
|
||||
HADDR[5] FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_r399_c1_m1.d[1]
|
||||
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_i399_007 FM_HW/_al_u2331|FM_HW/_al_u2330.b[0]
|
||||
FM_HW/_al_u2330_o FM_HW/_al_u2331|FM_HW/_al_u2330.c[1]
|
||||
FM_HW/_al_u2331_o FM_HW/FM_Demodulation/reg5_b19|FM_HW/FM_Demodulation/reg5_b18.b[1]
|
||||
FM_HW/_al_u2334_o FM_HW/_al_u2338.b[0]
|
||||
FM_HW/_al_u2338_o FM_HW/FM_Demodulation/reg5_b53|FM_HW/FM_Demodulation/reg5_b59.b[1]
|
||||
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_mux_b7/B6_3 FM_HW/_al_u2380|FM_HW/_al_u850.b[1]
|
||||
FM_HW/_al_u2380_o FM_HW/_al_u3650|FM_HW/FM_Dump_Data_IQ/reg0_b7.c[0]
|
||||
|
||||
|
||||
Endpoint: FM_HW/_al_u1257|FM_HW/FM_Dump_Data_IQ/reg0_b2
|
||||
416 -10.589000 31524130 3
|
||||
Timing path: u_logic/_al_u2680|u_logic/Vzupw6_reg.clk->FM_HW/_al_u1257|FM_HW/FM_Dump_Data_IQ/reg0_b2
|
||||
u_logic/_al_u2680|u_logic/Vzupw6_reg.clk
|
||||
FM_HW/_al_u1257|FM_HW/FM_Dump_Data_IQ/reg0_b2
|
||||
418 -10.589000 19.884000 30.473000 19 19
|
||||
u_logic/Vzupw6 u_logic/_al_u4224|u_logic/_al_u121.c[0]
|
||||
u_logic/Vo3ju6_lutinv u_logic/_al_u1992|u_logic/_al_u2497.a[0]
|
||||
u_logic/_al_u2497_o u_logic/_al_u2340|u_logic/_al_u2499.b[0]
|
||||
u_logic/_al_u2499_o u_logic/_al_u2508|u_logic/_al_u1569.a[1]
|
||||
u_logic/_al_u2508_o u_logic/_al_u2509|u_logic/_al_u4626.d[1]
|
||||
u_logic/_al_u2509_o u_logic/_al_u2510|u_logic/W8hbx6_reg.d[1]
|
||||
u_logic/_al_u2510_o u_logic/_al_u2587|u_logic/L6lax6_reg.d[1]
|
||||
u_logic/_al_u2587_o u_logic/_al_u2588|u_logic/T5yax6_reg.b[1]
|
||||
u_logic/R0ghu6 u_logic/add2/ucin_al_u4737.b[0]
|
||||
u_logic/N5fpw6[3] u_logic/_al_u2550|u_logic/_al_u2560.d[0]
|
||||
u_logic/_al_u2560_o u_logic/_al_u2561|u_logic/_al_u2551.b[1]
|
||||
u_logic/_al_u2561_o u_logic/_al_u4281|RAMDATA_Interface/reg0_b2.b[0]
|
||||
HADDR[4] FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_r65_c0_m1.c[0]
|
||||
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_i65_002 FM_HW/_al_u1318|FM_HW/_al_u1743.b[1]
|
||||
FM_HW/_al_u1318_o FM_HW/_al_u1746|FM_HW/_al_u1319.b[0]
|
||||
FM_HW/_al_u1319_o FM_HW/_al_u1320|FM_HW/_al_u3255.c[1]
|
||||
FM_HW/_al_u1320_o FM_HW/_al_u1321|FM_HW/_al_u3874.b[1]
|
||||
FM_HW/_al_u1321_o FM_HW/_al_u1344.b[1]
|
||||
FM_HW/_al_u1344_o FM_HW/_al_u1257|FM_HW/FM_Dump_Data_IQ/reg0_b2.c[0]
|
||||
Endpoint: FM_HW/_al_u3584|FM_HW/FM_Dump_Data_IQ/reg0_b5
|
||||
464 -13.686000 37671203 3
|
||||
Timing path: u_logic/P5vpw6_reg.clk->FM_HW/_al_u3584|FM_HW/FM_Dump_Data_IQ/reg0_b5
|
||||
u_logic/P5vpw6_reg.clk
|
||||
FM_HW/_al_u3584|FM_HW/FM_Dump_Data_IQ/reg0_b5
|
||||
466 -13.686000 19.884000 33.570000 24 24
|
||||
u_logic/P5vpw6 cw_top/wrapper_cwc_top/trigger_inst/HAS_BUS_DETECTOR$BUS_DETECTOR[0]$bus_detector_inst1/reg0_b7|cw_top/wrapper_cwc_top/trigger_inst/HAS_BUS_DETECTOR$BUS_DETECTOR[0]$bus_detector_inst1/reg0_b6.b[0]
|
||||
u_logic/Llaow6_lutinv u_logic/_al_u1671|u_logic/_al_u2549.a[0]
|
||||
u_logic/_al_u2549_o u_logic/_al_u2551|u_logic/Fpnpw6_reg.a[1]
|
||||
u_logic/_al_u2551_o u_logic/_al_u2552.a[1]
|
||||
u_logic/_al_u2552_o u_logic/_al_u2556|u_logic/_al_u1730.a[1]
|
||||
u_logic/_al_u2556_o u_logic/_al_u2563|u_logic/_al_u159.a[1]
|
||||
u_logic/_al_u2563_o u_logic/_al_u2564|u_logic/_al_u4431.d[1]
|
||||
u_logic/_al_u2564_o u_logic/_al_u2565|u_logic/_al_u2892.d[1]
|
||||
u_logic/_al_u2565_o u_logic/_al_u2566|u_logic/_al_u2882.d[1]
|
||||
u_logic/_al_u2566_o u_logic/_al_u2641|u_logic/_al_u2759.d[1]
|
||||
u_logic/Vtzhu6 u_logic/_al_u2643.d[0]
|
||||
u_logic/R0ghu6 u_logic/add2/ucin_al_u4809.b[0]
|
||||
u_logic/add2/c3 u_logic/add2/u3_al_u4810.fci
|
||||
u_logic/N5fpw6[4] u_logic/_al_u4753|u_logic/_al_u2604.c[0]
|
||||
u_logic/_al_u2604_o u_logic/_al_u2605|u_logic/Ibqpw6_reg.d[1]
|
||||
u_logic/_al_u2605_o u_logic/_al_u3990|RAMDATA_Interface/reg0_b3.b[0]
|
||||
HADDR[5] FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_r475_c1_m0.d[1]
|
||||
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_i475_005 FM_HW/_al_u2351|FM_HW/_al_u3012.b[0]
|
||||
FM_HW/_al_u3012_o FM_HW/_al_u3013|FM_HW/_al_u2666.c[1]
|
||||
FM_HW/_al_u3013_o FM_HW/_al_u3016.b[1]
|
||||
FM_HW/_al_u3016_o FM_HW/_al_u1918|FM_HW/_al_u3019.a[0]
|
||||
FM_HW/_al_u3019_o FM_HW/_al_u3030|FM_HW/_al_u795.b[1]
|
||||
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_mux_b5/B5_7 FM_HW/_al_u3158|FM_HW/FM_Demodulation/reg5_b52.a[0]
|
||||
FM_HW/_al_u3072_o FM_HW/_al_u3584|FM_HW/FM_Dump_Data_IQ/reg0_b5.c[0]
|
||||
|
||||
Timing path: u_logic/_al_u2680|u_logic/Vzupw6_reg.clk->FM_HW/_al_u1257|FM_HW/FM_Dump_Data_IQ/reg0_b2
|
||||
u_logic/_al_u2680|u_logic/Vzupw6_reg.clk
|
||||
FM_HW/_al_u1257|FM_HW/FM_Dump_Data_IQ/reg0_b2
|
||||
481 -10.589000 19.884000 30.473000 19 19
|
||||
u_logic/Vzupw6 u_logic/_al_u4224|u_logic/_al_u121.c[0]
|
||||
u_logic/Vo3ju6_lutinv u_logic/_al_u1992|u_logic/_al_u2497.a[0]
|
||||
u_logic/_al_u2497_o u_logic/_al_u2340|u_logic/_al_u2499.b[0]
|
||||
u_logic/_al_u2499_o u_logic/_al_u2508|u_logic/_al_u1569.a[1]
|
||||
u_logic/_al_u2508_o u_logic/_al_u2509|u_logic/_al_u4626.d[1]
|
||||
u_logic/_al_u2509_o u_logic/_al_u2510|u_logic/W8hbx6_reg.d[1]
|
||||
u_logic/_al_u2510_o u_logic/_al_u2587|u_logic/L6lax6_reg.d[1]
|
||||
u_logic/_al_u2587_o u_logic/_al_u2588|u_logic/T5yax6_reg.b[1]
|
||||
u_logic/R0ghu6 u_logic/add2/ucin_al_u4737.b[0]
|
||||
u_logic/N5fpw6[3] u_logic/_al_u2550|u_logic/_al_u2560.d[0]
|
||||
u_logic/_al_u2560_o u_logic/_al_u2561|u_logic/_al_u2551.b[1]
|
||||
u_logic/_al_u2561_o u_logic/_al_u4281|RAMDATA_Interface/reg0_b2.b[0]
|
||||
HADDR[4] FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_r65_c0_m1.c[0]
|
||||
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_i65_002 FM_HW/_al_u1318|FM_HW/_al_u1743.b[1]
|
||||
FM_HW/_al_u1318_o FM_HW/_al_u1746|FM_HW/_al_u1319.b[0]
|
||||
FM_HW/_al_u1319_o FM_HW/_al_u1320|FM_HW/_al_u3255.c[1]
|
||||
FM_HW/_al_u1320_o FM_HW/_al_u1321|FM_HW/_al_u3874.b[1]
|
||||
FM_HW/_al_u1321_o FM_HW/_al_u1344.b[0]
|
||||
FM_HW/_al_u1344_o FM_HW/_al_u1257|FM_HW/FM_Dump_Data_IQ/reg0_b2.c[0]
|
||||
Timing path: u_logic/P5vpw6_reg.clk->FM_HW/_al_u3584|FM_HW/FM_Dump_Data_IQ/reg0_b5
|
||||
u_logic/P5vpw6_reg.clk
|
||||
FM_HW/_al_u3584|FM_HW/FM_Dump_Data_IQ/reg0_b5
|
||||
539 -13.686000 19.884000 33.570000 24 24
|
||||
u_logic/P5vpw6 cw_top/wrapper_cwc_top/trigger_inst/HAS_BUS_DETECTOR$BUS_DETECTOR[0]$bus_detector_inst1/reg0_b7|cw_top/wrapper_cwc_top/trigger_inst/HAS_BUS_DETECTOR$BUS_DETECTOR[0]$bus_detector_inst1/reg0_b6.b[0]
|
||||
u_logic/Llaow6_lutinv u_logic/_al_u1671|u_logic/_al_u2549.a[0]
|
||||
u_logic/_al_u2549_o u_logic/_al_u2551|u_logic/Fpnpw6_reg.a[1]
|
||||
u_logic/_al_u2551_o u_logic/_al_u2552.a[0]
|
||||
u_logic/_al_u2552_o u_logic/_al_u2556|u_logic/_al_u1730.a[1]
|
||||
u_logic/_al_u2556_o u_logic/_al_u2563|u_logic/_al_u159.a[1]
|
||||
u_logic/_al_u2563_o u_logic/_al_u2564|u_logic/_al_u4431.d[1]
|
||||
u_logic/_al_u2564_o u_logic/_al_u2565|u_logic/_al_u2892.d[1]
|
||||
u_logic/_al_u2565_o u_logic/_al_u2566|u_logic/_al_u2882.d[1]
|
||||
u_logic/_al_u2566_o u_logic/_al_u2641|u_logic/_al_u2759.d[1]
|
||||
u_logic/Vtzhu6 u_logic/_al_u2643.d[0]
|
||||
u_logic/R0ghu6 u_logic/add2/ucin_al_u4809.b[0]
|
||||
u_logic/add2/c3 u_logic/add2/u3_al_u4810.fci
|
||||
u_logic/N5fpw6[4] u_logic/_al_u4753|u_logic/_al_u2604.c[0]
|
||||
u_logic/_al_u2604_o u_logic/_al_u2605|u_logic/Ibqpw6_reg.d[1]
|
||||
u_logic/_al_u2605_o u_logic/_al_u3990|RAMDATA_Interface/reg0_b3.b[0]
|
||||
HADDR[5] FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_r475_c1_m0.d[1]
|
||||
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_i475_005 FM_HW/_al_u2351|FM_HW/_al_u3012.b[0]
|
||||
FM_HW/_al_u3012_o FM_HW/_al_u3013|FM_HW/_al_u2666.c[1]
|
||||
FM_HW/_al_u3013_o FM_HW/_al_u3016.b[1]
|
||||
FM_HW/_al_u3016_o FM_HW/_al_u1918|FM_HW/_al_u3019.a[0]
|
||||
FM_HW/_al_u3019_o FM_HW/_al_u3030|FM_HW/_al_u795.b[1]
|
||||
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_mux_b5/B5_7 FM_HW/_al_u3158|FM_HW/FM_Demodulation/reg5_b52.a[0]
|
||||
FM_HW/_al_u3072_o FM_HW/_al_u3584|FM_HW/FM_Dump_Data_IQ/reg0_b5.c[0]
|
||||
|
||||
Timing path: u_logic/_al_u2662|u_logic/Ufopw6_reg.clk->FM_HW/_al_u1257|FM_HW/FM_Dump_Data_IQ/reg0_b2
|
||||
u_logic/_al_u2662|u_logic/Ufopw6_reg.clk
|
||||
FM_HW/_al_u1257|FM_HW/FM_Dump_Data_IQ/reg0_b2
|
||||
544 -10.574000 19.884000 30.458000 19 19
|
||||
u_logic/Ufopw6 u_logic/_al_u4224|u_logic/_al_u121.d[0]
|
||||
u_logic/Vo3ju6_lutinv u_logic/_al_u1992|u_logic/_al_u2497.a[0]
|
||||
u_logic/_al_u2497_o u_logic/_al_u2340|u_logic/_al_u2499.b[0]
|
||||
u_logic/_al_u2499_o u_logic/_al_u2508|u_logic/_al_u1569.a[1]
|
||||
u_logic/_al_u2508_o u_logic/_al_u2509|u_logic/_al_u4626.d[1]
|
||||
u_logic/_al_u2509_o u_logic/_al_u2510|u_logic/W8hbx6_reg.d[1]
|
||||
u_logic/_al_u2510_o u_logic/_al_u2587|u_logic/L6lax6_reg.d[1]
|
||||
u_logic/_al_u2587_o u_logic/_al_u2588|u_logic/T5yax6_reg.b[1]
|
||||
u_logic/R0ghu6 u_logic/add2/ucin_al_u4737.b[0]
|
||||
u_logic/N5fpw6[3] u_logic/_al_u2550|u_logic/_al_u2560.d[0]
|
||||
u_logic/_al_u2560_o u_logic/_al_u2561|u_logic/_al_u2551.b[1]
|
||||
u_logic/_al_u2561_o u_logic/_al_u4281|RAMDATA_Interface/reg0_b2.b[0]
|
||||
HADDR[4] FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_r65_c0_m1.c[0]
|
||||
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_i65_002 FM_HW/_al_u1318|FM_HW/_al_u1743.b[1]
|
||||
FM_HW/_al_u1318_o FM_HW/_al_u1746|FM_HW/_al_u1319.b[0]
|
||||
FM_HW/_al_u1319_o FM_HW/_al_u1320|FM_HW/_al_u3255.c[1]
|
||||
FM_HW/_al_u1320_o FM_HW/_al_u1321|FM_HW/_al_u3874.b[1]
|
||||
FM_HW/_al_u1321_o FM_HW/_al_u1344.b[1]
|
||||
FM_HW/_al_u1344_o FM_HW/_al_u1257|FM_HW/FM_Dump_Data_IQ/reg0_b2.c[0]
|
||||
Timing path: u_logic/P5vpw6_reg.clk->FM_HW/_al_u3584|FM_HW/FM_Dump_Data_IQ/reg0_b5
|
||||
u_logic/P5vpw6_reg.clk
|
||||
FM_HW/_al_u3584|FM_HW/FM_Dump_Data_IQ/reg0_b5
|
||||
612 -13.686000 19.884000 33.570000 24 24
|
||||
u_logic/P5vpw6 cw_top/wrapper_cwc_top/trigger_inst/HAS_BUS_DETECTOR$BUS_DETECTOR[0]$bus_detector_inst1/reg0_b7|cw_top/wrapper_cwc_top/trigger_inst/HAS_BUS_DETECTOR$BUS_DETECTOR[0]$bus_detector_inst1/reg0_b6.b[0]
|
||||
u_logic/Llaow6_lutinv u_logic/_al_u1671|u_logic/_al_u2549.a[0]
|
||||
u_logic/_al_u2549_o u_logic/_al_u2551|u_logic/Fpnpw6_reg.a[1]
|
||||
u_logic/_al_u2551_o u_logic/_al_u2552.a[1]
|
||||
u_logic/_al_u2552_o u_logic/_al_u2556|u_logic/_al_u1730.a[1]
|
||||
u_logic/_al_u2556_o u_logic/_al_u2563|u_logic/_al_u159.a[1]
|
||||
u_logic/_al_u2563_o u_logic/_al_u2564|u_logic/_al_u4431.d[1]
|
||||
u_logic/_al_u2564_o u_logic/_al_u2565|u_logic/_al_u2892.d[1]
|
||||
u_logic/_al_u2565_o u_logic/_al_u2566|u_logic/_al_u2882.d[1]
|
||||
u_logic/_al_u2566_o u_logic/_al_u2641|u_logic/_al_u2759.d[1]
|
||||
u_logic/Vtzhu6 u_logic/_al_u2643.d[0]
|
||||
u_logic/R0ghu6 u_logic/add2/ucin_al_u4809.b[0]
|
||||
u_logic/add2/c3 u_logic/add2/u3_al_u4810.fci
|
||||
u_logic/N5fpw6[4] u_logic/_al_u4753|u_logic/_al_u2604.c[0]
|
||||
u_logic/_al_u2604_o u_logic/_al_u2605|u_logic/Ibqpw6_reg.d[1]
|
||||
u_logic/_al_u2605_o u_logic/_al_u3990|RAMDATA_Interface/reg0_b3.b[0]
|
||||
HADDR[5] FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_r475_c1_m0.d[1]
|
||||
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_i475_005 FM_HW/_al_u2351|FM_HW/_al_u3012.b[0]
|
||||
FM_HW/_al_u3012_o FM_HW/_al_u3013|FM_HW/_al_u2666.c[1]
|
||||
FM_HW/_al_u3013_o FM_HW/_al_u3016.b[0]
|
||||
FM_HW/_al_u3016_o FM_HW/_al_u1918|FM_HW/_al_u3019.a[0]
|
||||
FM_HW/_al_u3019_o FM_HW/_al_u3030|FM_HW/_al_u795.b[1]
|
||||
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_mux_b5/B5_7 FM_HW/_al_u3158|FM_HW/FM_Demodulation/reg5_b52.a[0]
|
||||
FM_HW/_al_u3072_o FM_HW/_al_u3584|FM_HW/FM_Dump_Data_IQ/reg0_b5.c[0]
|
||||
|
||||
|
||||
|
||||
Hold check
|
||||
607 3
|
||||
Endpoint: RAM_CODE/ram_mem_unify_al_u20_4096x8_sub_000000_000
|
||||
609 0.249000 12 3
|
||||
Timing path: RAMCODE_Interface/reg0_b10|RAMCODE_Interface/reg0_b7.clk->RAM_CODE/ram_mem_unify_al_u20_4096x8_sub_000000_000
|
||||
RAMCODE_Interface/reg0_b10|RAMCODE_Interface/reg0_b7.clk
|
||||
RAM_CODE/ram_mem_unify_al_u20_4096x8_sub_000000_000
|
||||
611 0.249000 0.200000 0.449000 0 1
|
||||
RAMCODE_WADDR[7] RAM_CODE/ram_mem_unify_al_u20_4096x8_sub_000000_000.addra[8]
|
||||
685 3
|
||||
Endpoint: SPI_TX/FIFO_SPI/al_ram_mem_r1_c1_l
|
||||
687 0.304000 94 3
|
||||
Timing path: _al_u270|SPI_TX/FIFO_SPI/reg1_b0.clk->SPI_TX/FIFO_SPI/al_ram_mem_r1_c1_l
|
||||
_al_u270|SPI_TX/FIFO_SPI/reg1_b0.clk
|
||||
SPI_TX/FIFO_SPI/al_ram_mem_r1_c1_l
|
||||
689 0.304000 0.134000 0.438000 1 1
|
||||
SPI_TX/FIFO_SPI/wp[0] SPI_TX/FIFO_SPI/al_ram_mem_r1_c1_l.a[0]
|
||||
|
||||
Timing path: RAMCODE_Interface/reg0_b6|RAMCODE_Interface/reg0_b4.clk->RAM_CODE/ram_mem_unify_al_u20_4096x8_sub_000000_000
|
||||
RAMCODE_Interface/reg0_b6|RAMCODE_Interface/reg0_b4.clk
|
||||
RAM_CODE/ram_mem_unify_al_u20_4096x8_sub_000000_000
|
||||
638 0.259000 0.200000 0.459000 0 1
|
||||
RAMCODE_WADDR[4] RAM_CODE/ram_mem_unify_al_u20_4096x8_sub_000000_000.addra[5]
|
||||
Timing path: UART_Interface/rd_en_reg_reg|SPI_Interface/wr_en_reg_reg.clk->SPI_TX/FIFO_SPI/al_ram_mem_r1_c1_l
|
||||
UART_Interface/rd_en_reg_reg|SPI_Interface/wr_en_reg_reg.clk
|
||||
SPI_TX/FIFO_SPI/al_ram_mem_r1_c1_l
|
||||
716 1.596000 0.134000 1.730000 2 2
|
||||
SPI_Interface/wr_en_reg _al_u128|_al_u130.d[1]
|
||||
SPI_TX_Data[4] SPI_TX/FIFO_SPI/al_ram_mem_r1_c1_l.a[1]
|
||||
|
||||
Timing path: RAMCODE_Interface/reg0_b6|RAMCODE_Interface/reg0_b4.clk->RAM_CODE/ram_mem_unify_al_u20_4096x8_sub_000000_000
|
||||
RAMCODE_Interface/reg0_b6|RAMCODE_Interface/reg0_b4.clk
|
||||
RAM_CODE/ram_mem_unify_al_u20_4096x8_sub_000000_000
|
||||
665 0.411000 0.200000 0.611000 0 1
|
||||
RAMCODE_WADDR[6] RAM_CODE/ram_mem_unify_al_u20_4096x8_sub_000000_000.addra[7]
|
||||
Timing path: u_logic/_al_u3978|u_logic/Wvgax6_reg.clk->SPI_TX/FIFO_SPI/al_ram_mem_r1_c1_l
|
||||
u_logic/_al_u3978|u_logic/Wvgax6_reg.clk
|
||||
SPI_TX/FIFO_SPI/al_ram_mem_r1_c1_l
|
||||
745 3.696000 0.134000 3.830000 3 3
|
||||
u_logic/Wvgax6 u_logic/_al_u3342|u_logic/Kqhbx6_reg.d[0]
|
||||
HWDATA[4] _al_u128|_al_u130.c[1]
|
||||
SPI_TX_Data[4] SPI_TX/FIFO_SPI/al_ram_mem_r1_c1_l.a[1]
|
||||
|
||||
|
||||
Endpoint: SPI_TX/FIFO_SPI/al_ram_mem_r0_c1_l
|
||||
692 0.304000 94 3
|
||||
Timing path: _al_u376|SPI_TX/FIFO_SPI/reg1_b2.clk->SPI_TX/FIFO_SPI/al_ram_mem_r0_c1_l
|
||||
_al_u376|SPI_TX/FIFO_SPI/reg1_b2.clk
|
||||
SPI_TX/FIFO_SPI/al_ram_mem_r0_c1_l
|
||||
694 0.304000 0.134000 0.438000 1 1
|
||||
SPI_TX/FIFO_SPI/wp[2] SPI_TX/FIFO_SPI/al_ram_mem_r0_c1_l.c[0]
|
||||
Endpoint: FM_HW/FM_Demodulation/mult7_
|
||||
776 0.308000 10 3
|
||||
Timing path: FM_HW/FM_RSSI_SCAN/add2/ucin_al_u4000.clk->FM_HW/FM_Demodulation/mult7_
|
||||
FM_HW/FM_RSSI_SCAN/add2/ucin_al_u4000.clk
|
||||
FM_HW/FM_Demodulation/mult7_
|
||||
778 0.308000 0.100000 0.408000 0 1
|
||||
FM_HW/FM_Demodulation/dmd_data_filter[16][3] FM_HW/FM_Demodulation/mult7_.a[3]
|
||||
|
||||
Timing path: _al_u294|SPI_Interface/wr_en_reg_reg.clk->SPI_TX/FIFO_SPI/al_ram_mem_r0_c1_l
|
||||
_al_u294|SPI_Interface/wr_en_reg_reg.clk
|
||||
SPI_TX/FIFO_SPI/al_ram_mem_r0_c1_l
|
||||
721 1.964000 0.134000 2.098000 2 2
|
||||
SPI_Interface/wr_en_reg _al_u114|_al_u116.d[0]
|
||||
SPI_TX_Data[6] SPI_TX/FIFO_SPI/al_ram_mem_r0_c1_l.c[1]
|
||||
Timing path: FM_HW/FM_Demodulation/reg5_b160|FM_HW/FM_Demodulation/reg5_b162.clk->FM_HW/FM_Demodulation/mult7_
|
||||
FM_HW/FM_Demodulation/reg5_b160|FM_HW/FM_Demodulation/reg5_b162.clk
|
||||
FM_HW/FM_Demodulation/mult7_
|
||||
805 0.320000 0.100000 0.420000 0 1
|
||||
FM_HW/FM_Demodulation/dmd_data_filter[16][2] FM_HW/FM_Demodulation/mult7_.a[2]
|
||||
|
||||
Timing path: u_logic/_al_u2859|u_logic/Wvgax6_reg.clk->SPI_TX/FIFO_SPI/al_ram_mem_r0_c1_l
|
||||
u_logic/_al_u2859|u_logic/Wvgax6_reg.clk
|
||||
SPI_TX/FIFO_SPI/al_ram_mem_r0_c1_l
|
||||
750 3.117000 0.134000 3.251000 3 3
|
||||
u_logic/Wvgax6 u_logic/_al_u2540|u_logic/Z9abx6_reg.d[0]
|
||||
HWDATA[6] _al_u114|_al_u116.c[0]
|
||||
SPI_TX_Data[6] SPI_TX/FIFO_SPI/al_ram_mem_r0_c1_l.c[1]
|
||||
Timing path: FM_HW/FM_Demodulation/sub0_2/u0|sub0_2/ucin.clk->FM_HW/FM_Demodulation/mult7_
|
||||
FM_HW/FM_Demodulation/sub0_2/u0|sub0_2/ucin.clk
|
||||
FM_HW/FM_Demodulation/mult7_
|
||||
832 0.466000 0.100000 0.566000 0 1
|
||||
FM_HW/FM_Demodulation/dmd_data_filter[16][8] FM_HW/FM_Demodulation/mult7_.a[8]
|
||||
|
||||
|
||||
Endpoint: FM_HW/FM_Demodulation/mult20_
|
||||
781 0.308000 10 3
|
||||
Timing path: FM_HW/FM_Demodulation/reg5_b30|FM_HW/FM_Demodulation/reg5_b31.clk->FM_HW/FM_Demodulation/mult20_
|
||||
FM_HW/FM_Demodulation/reg5_b30|FM_HW/FM_Demodulation/reg5_b31.clk
|
||||
FM_HW/FM_Demodulation/mult20_
|
||||
783 0.308000 0.100000 0.408000 0 1
|
||||
FM_HW/FM_Demodulation/dmd_data_filter[3][0] FM_HW/FM_Demodulation/mult20_.a[0]
|
||||
Endpoint: RAM_CODE/ram_mem_unify_al_u10_4096x8_sub_000000_006
|
||||
859 0.313000 12 3
|
||||
Timing path: RAMCODE_Interface/reg0_b9|RAMCODE_Interface/reg0_b8.clk->RAM_CODE/ram_mem_unify_al_u10_4096x8_sub_000000_006
|
||||
RAMCODE_Interface/reg0_b9|RAMCODE_Interface/reg0_b8.clk
|
||||
RAM_CODE/ram_mem_unify_al_u10_4096x8_sub_000000_006
|
||||
861 0.313000 0.200000 0.513000 0 1
|
||||
RAMCODE_WADDR[8] RAM_CODE/ram_mem_unify_al_u10_4096x8_sub_000000_006.addra[9]
|
||||
|
||||
Timing path: FM_HW/FM_Demodulation/reg5_b30|FM_HW/FM_Demodulation/reg5_b31.clk->FM_HW/FM_Demodulation/mult20_
|
||||
FM_HW/FM_Demodulation/reg5_b30|FM_HW/FM_Demodulation/reg5_b31.clk
|
||||
FM_HW/FM_Demodulation/mult20_
|
||||
810 0.320000 0.100000 0.420000 0 1
|
||||
FM_HW/FM_Demodulation/dmd_data_filter[3][1] FM_HW/FM_Demodulation/mult20_.a[1]
|
||||
Timing path: RAMCODE_Interface/reg0_b9|RAMCODE_Interface/reg0_b8.clk->RAM_CODE/ram_mem_unify_al_u10_4096x8_sub_000000_006
|
||||
RAMCODE_Interface/reg0_b9|RAMCODE_Interface/reg0_b8.clk
|
||||
RAM_CODE/ram_mem_unify_al_u10_4096x8_sub_000000_006
|
||||
888 0.579000 0.200000 0.779000 0 1
|
||||
RAMCODE_WADDR[9] RAM_CODE/ram_mem_unify_al_u10_4096x8_sub_000000_006.addra[10]
|
||||
|
||||
Timing path: FM_HW/FM_Demodulation/reg5_b36|FM_HW/FM_Demodulation/reg5_b37.clk->FM_HW/FM_Demodulation/mult20_
|
||||
FM_HW/FM_Demodulation/reg5_b36|FM_HW/FM_Demodulation/reg5_b37.clk
|
||||
FM_HW/FM_Demodulation/mult20_
|
||||
837 0.320000 0.100000 0.420000 0 1
|
||||
FM_HW/FM_Demodulation/dmd_data_filter[3][6] FM_HW/FM_Demodulation/mult20_.a[6]
|
||||
Timing path: RAMCODE_Interface/reg0_b11|RAMCODE_Interface/reg0_b10.clk->RAM_CODE/ram_mem_unify_al_u10_4096x8_sub_000000_006
|
||||
RAMCODE_Interface/reg0_b11|RAMCODE_Interface/reg0_b10.clk
|
||||
RAM_CODE/ram_mem_unify_al_u10_4096x8_sub_000000_006
|
||||
915 0.582000 0.200000 0.782000 0 1
|
||||
RAMCODE_WADDR[10] RAM_CODE/ram_mem_unify_al_u10_4096x8_sub_000000_006.addra[11]
|
||||
|
||||
|
||||
|
||||
Recovery check
|
||||
864 3
|
||||
Endpoint: cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b212|cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b208
|
||||
866 6.858000 1 1
|
||||
Timing path: cw_top/wrapper_cwc_top/cfg_int_inst/tap_inst/rst_reg.clk->cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b212|cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b208
|
||||
cw_top/wrapper_cwc_top/cfg_int_inst/tap_inst/rst_reg.clk
|
||||
cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b212|cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b208
|
||||
868 6.858000 9.700000 2.842000 0 1
|
||||
cw_top/wrapper_cwc_top/cfg_int_inst/rst cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b212|cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b208.sr
|
||||
942 3
|
||||
Endpoint: cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b55|cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b68
|
||||
944 7.068000 1 1
|
||||
Timing path: _al_u570|cw_top/wrapper_cwc_top/cfg_int_inst/tap_inst/rst_reg.clk->cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b55|cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b68
|
||||
_al_u570|cw_top/wrapper_cwc_top/cfg_int_inst/tap_inst/rst_reg.clk
|
||||
cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b55|cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b68
|
||||
946 7.068000 9.700000 2.632000 0 1
|
||||
cw_top/wrapper_cwc_top/cfg_int_inst/rst cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b55|cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b68.sr
|
||||
|
||||
|
||||
Endpoint: cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b140|cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b144
|
||||
895 6.858000 1 1
|
||||
Timing path: cw_top/wrapper_cwc_top/cfg_int_inst/tap_inst/rst_reg.clk->cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b140|cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b144
|
||||
cw_top/wrapper_cwc_top/cfg_int_inst/tap_inst/rst_reg.clk
|
||||
cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b140|cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b144
|
||||
897 6.858000 9.700000 2.842000 0 1
|
||||
cw_top/wrapper_cwc_top/cfg_int_inst/rst cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b140|cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b144.sr
|
||||
Endpoint: cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b63|cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b64
|
||||
973 7.068000 1 1
|
||||
Timing path: _al_u570|cw_top/wrapper_cwc_top/cfg_int_inst/tap_inst/rst_reg.clk->cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b63|cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b64
|
||||
_al_u570|cw_top/wrapper_cwc_top/cfg_int_inst/tap_inst/rst_reg.clk
|
||||
cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b63|cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b64
|
||||
975 7.068000 9.700000 2.632000 0 1
|
||||
cw_top/wrapper_cwc_top/cfg_int_inst/rst cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b63|cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b64.sr
|
||||
|
||||
|
||||
Endpoint: cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg1_b47|cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg1_b48
|
||||
924 6.929000 1 1
|
||||
Timing path: cw_top/wrapper_cwc_top/cfg_int_inst/tap_inst/rst_reg.clk->cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg1_b47|cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg1_b48
|
||||
cw_top/wrapper_cwc_top/cfg_int_inst/tap_inst/rst_reg.clk
|
||||
cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg1_b47|cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg1_b48
|
||||
926 6.929000 9.700000 2.771000 0 1
|
||||
cw_top/wrapper_cwc_top/cfg_int_inst/rst cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg1_b47|cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg1_b48.sr
|
||||
Endpoint: cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b140|cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b141
|
||||
1002 7.197000 1 1
|
||||
Timing path: _al_u570|cw_top/wrapper_cwc_top/cfg_int_inst/tap_inst/rst_reg.clk->cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b140|cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b141
|
||||
_al_u570|cw_top/wrapper_cwc_top/cfg_int_inst/tap_inst/rst_reg.clk
|
||||
cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b140|cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b141
|
||||
1004 7.197000 9.700000 2.503000 0 1
|
||||
cw_top/wrapper_cwc_top/cfg_int_inst/rst cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b140|cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b141.sr
|
||||
|
||||
|
||||
|
||||
Removal check
|
||||
953 3
|
||||
Endpoint: cw_top/wrapper_cwc_top/trigger_inst/reg1_b15|cw_top/wrapper_cwc_top/trigger_inst/reg1_b14
|
||||
955 0.426000 1 1
|
||||
Timing path: _al_u300|cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg1_b0.clk->cw_top/wrapper_cwc_top/trigger_inst/reg1_b15|cw_top/wrapper_cwc_top/trigger_inst/reg1_b14
|
||||
_al_u300|cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg1_b0.clk
|
||||
cw_top/wrapper_cwc_top/trigger_inst/reg1_b15|cw_top/wrapper_cwc_top/trigger_inst/reg1_b14
|
||||
957 0.426000 0.300000 0.726000 0 1
|
||||
cw_top/wrapper_cwc_top/control[0] cw_top/wrapper_cwc_top/trigger_inst/reg1_b15|cw_top/wrapper_cwc_top/trigger_inst/reg1_b14.sr
|
||||
1031 3
|
||||
Endpoint: u_logic/_al_u2894|u_logic/Wfspw6_reg
|
||||
1033 0.438000 1 1
|
||||
Timing path: u_logic/_al_u2275|cpuresetn_reg.clk->u_logic/_al_u2894|u_logic/Wfspw6_reg
|
||||
u_logic/_al_u2275|cpuresetn_reg.clk
|
||||
u_logic/_al_u2894|u_logic/Wfspw6_reg
|
||||
1035 0.438000 0.300000 0.738000 0 1
|
||||
cpuresetn u_logic/_al_u2894|u_logic/Wfspw6_reg.sr
|
||||
|
||||
|
||||
Endpoint: cw_top/wrapper_cwc_top/trigger_inst/sub0/ucin_al_u598
|
||||
984 0.503000 1 1
|
||||
Timing path: _al_u300|cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg1_b0.clk->cw_top/wrapper_cwc_top/trigger_inst/sub0/ucin_al_u598
|
||||
_al_u300|cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg1_b0.clk
|
||||
cw_top/wrapper_cwc_top/trigger_inst/sub0/ucin_al_u598
|
||||
986 0.503000 0.300000 0.803000 0 1
|
||||
cw_top/wrapper_cwc_top/control[0] cw_top/wrapper_cwc_top/trigger_inst/sub0/ucin_al_u598.sr
|
||||
Endpoint: u_logic/_al_u3144|u_logic/Kojpw6_reg
|
||||
1062 0.465000 1 1
|
||||
Timing path: u_logic/_al_u2275|cpuresetn_reg.clk->u_logic/_al_u3144|u_logic/Kojpw6_reg
|
||||
u_logic/_al_u2275|cpuresetn_reg.clk
|
||||
u_logic/_al_u3144|u_logic/Kojpw6_reg
|
||||
1064 0.465000 0.300000 0.765000 0 1
|
||||
cpuresetn u_logic/_al_u3144|u_logic/Kojpw6_reg.sr
|
||||
|
||||
|
||||
Endpoint: cw_top/wrapper_cwc_top/trigger_inst/reg2_b2
|
||||
1013 0.503000 1 1
|
||||
Timing path: _al_u300|cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg1_b0.clk->cw_top/wrapper_cwc_top/trigger_inst/reg2_b2
|
||||
_al_u300|cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg1_b0.clk
|
||||
cw_top/wrapper_cwc_top/trigger_inst/reg2_b2
|
||||
1015 0.503000 0.300000 0.803000 0 1
|
||||
cw_top/wrapper_cwc_top/control[0] cw_top/wrapper_cwc_top/trigger_inst/reg2_b2.sr
|
||||
Endpoint: cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg1_b5|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg1_b6
|
||||
1091 0.475000 1 1
|
||||
Timing path: cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg1_b0.clk->cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg1_b5|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg1_b6
|
||||
cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg1_b0.clk
|
||||
cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg1_b5|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg1_b6
|
||||
1093 0.475000 0.300000 0.775000 0 1
|
||||
cw_top/wrapper_cwc_top/control[0] cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg1_b5|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg1_b6.sr
|
||||
|
||||
|
||||
|
||||
@ -371,11 +410,11 @@ cw_top/wrapper_cwc_top/control[0] cw_top/wrapper_cwc_top/trigger_inst/reg2_b2.sr
|
||||
Timing group statistics:
|
||||
Clock constraints:
|
||||
Clock Name Min Period Max Freq Skew Fanout TNS
|
||||
DeriveClock (50.0MHz) 30.879ns 32MHz 0.000ns 2706 -552.899ns
|
||||
DeriveClock (50.0MHz) 33.826ns 29MHz 0.000ns 2795 -2264.715ns
|
||||
Minimum input arrival time before clock: no constraint path
|
||||
Maximum output required time after clock: no constraint path
|
||||
Maximum combinational path delay: no constraint path
|
||||
Warning: No clock constraint on 13 clock net(s):
|
||||
Warning: No clock constraint on 14 clock net(s):
|
||||
CW_CLK_MSI
|
||||
FM_Display/clk_1KHz
|
||||
FM_HW/ADC_CLK
|
||||
@ -388,5 +427,6 @@ Warning: No clock constraint on 13 clock net(s):
|
||||
MSI_REFCLK_pad
|
||||
clk_pad
|
||||
jtck
|
||||
scan_unit/scan_clk
|
||||
u_logic/SWCLKTCK_pad
|
||||
|
||||
|
||||
@ -2,25 +2,25 @@ standard
|
||||
***Report Model: CortexM0_SoC***
|
||||
|
||||
IO Statistics
|
||||
#IO 31
|
||||
#input 4
|
||||
#output 26
|
||||
#IO 39
|
||||
#input 8
|
||||
#output 30
|
||||
#inout 1
|
||||
|
||||
Utilization Statistics
|
||||
#lut 16425 out of 19600 83.80%
|
||||
#reg 2390 out of 19600 12.19%
|
||||
#le 16791
|
||||
#lut only 14401 out of 16791 85.77%
|
||||
#reg only 366 out of 16791 2.18%
|
||||
#lut® 2024 out of 16791 12.05%
|
||||
#lut 16581 out of 19600 84.60%
|
||||
#reg 2517 out of 19600 12.84%
|
||||
#le 16834
|
||||
#lut only 14317 out of 16834 85.05%
|
||||
#reg only 253 out of 16834 1.50%
|
||||
#lut® 2264 out of 16834 13.45%
|
||||
#dsp 26 out of 29 89.66%
|
||||
#bram 32 out of 64 50.00%
|
||||
#bram9k 32
|
||||
#fifo9k 0
|
||||
#bram32k 7 out of 16 43.75%
|
||||
#bram32k 6 out of 16 37.50%
|
||||
#adc 1 out of 1 100.00%
|
||||
#pad 31 out of 186 16.67%
|
||||
#pad 39 out of 186 20.97%
|
||||
#ireg 0
|
||||
#oreg 0
|
||||
#treg 0
|
||||
@ -34,6 +34,10 @@ Detailed IO Report
|
||||
RXD INPUT F12 LVCMOS33 N/A PULLUP NONE
|
||||
SWCLK INPUT R2 LVCMOS33 N/A PULLUP NONE
|
||||
clk INPUT R7 LVCMOS33 N/A PULLUP NONE
|
||||
col[3] INPUT F10 LVTTL33 N/A PULLUP NONE
|
||||
col[2] INPUT C11 LVTTL33 N/A PULLUP NONE
|
||||
col[1] INPUT D11 LVTTL33 N/A PULLUP NONE
|
||||
col[0] INPUT E11 LVTTL33 N/A PULLUP NONE
|
||||
LED[7] OUTPUT F16 LVCMOS33 8 NONE NONE
|
||||
LED[6] OUTPUT E16 LVCMOS33 8 NONE NONE
|
||||
LED[5] OUTPUT E13 LVCMOS33 8 NONE NONE
|
||||
@ -48,6 +52,10 @@ Detailed IO Report
|
||||
MSI_SDATA OUTPUT N9 LVCMOS33 8 NONE NONE
|
||||
TXD OUTPUT D12 LVCMOS33 8 NONE NONE
|
||||
audio_pwm OUTPUT N8 LVCMOS33 8 NONE NONE
|
||||
row[3] OUTPUT D9 LVTTL33 8 NONE NONE
|
||||
row[2] OUTPUT F9 LVTTL33 8 NONE NONE
|
||||
row[1] OUTPUT C10 LVTTL33 8 NONE NONE
|
||||
row[0] OUTPUT E10 LVTTL33 8 NONE NONE
|
||||
seg[7] OUTPUT C8 LVCMOS33 8 NONE NONE
|
||||
seg[6] OUTPUT A8 LVCMOS33 8 NONE NONE
|
||||
seg[5] OUTPUT B5 LVCMOS33 8 NONE NONE
|
||||
@ -66,5 +74,5 @@ Report Hierarchy Area:
|
||||
+----------------------------------------------------------------------+
|
||||
|Instance |Module |le |lut |ripple |seq |bram |dsp |
|
||||
+----------------------------------------------------------------------+
|
||||
|top |CortexM0_SoC |16791 |15972 |453 |2390 |39 |26 |
|
||||
|top |CortexM0_SoC |16834 |16108 |473 |2517 |38 |26 |
|
||||
+----------------------------------------------------------------------+
|
||||
|
||||
@ -2,39 +2,39 @@ standard
|
||||
***Report Model: CortexM0_SoC***
|
||||
|
||||
IO Statistics
|
||||
#IO 31
|
||||
#input 4
|
||||
#output 26
|
||||
#IO 39
|
||||
#input 8
|
||||
#output 30
|
||||
#inout 1
|
||||
|
||||
Gate Statistics
|
||||
#Basic gates 20809
|
||||
#and 9619
|
||||
#Basic gates 21235
|
||||
#and 9763
|
||||
#nand 0
|
||||
#or 2076
|
||||
#or 2092
|
||||
#nor 0
|
||||
#xor 76
|
||||
#xnor 0
|
||||
#buf 0
|
||||
#not 6556
|
||||
#not 6669
|
||||
#bufif1 1
|
||||
#MX21 547
|
||||
#FADD 0
|
||||
#DFF 1934
|
||||
#DFF 2087
|
||||
#LATCH 0
|
||||
#MACRO_ADD 64
|
||||
#MACRO_EQ 110
|
||||
#MACRO_ADD 66
|
||||
#MACRO_EQ 112
|
||||
#MACRO_MULT 26
|
||||
#MACRO_MUX 590
|
||||
#MACRO_MUX 626
|
||||
#MACRO_OTHERS 13
|
||||
|
||||
Report Hierarchy Area:
|
||||
+--------------------------------------------------------------+
|
||||
|Instance |Module |gates |seq |macros |
|
||||
+--------------------------------------------------------------+
|
||||
|top |CortexM0_SoC |18875 |1934 |213 |
|
||||
|top |CortexM0_SoC |19148 |2087 |217 |
|
||||
| FM_Display |FM_Display |45 |81 |38 |
|
||||
| FM_HW |FM_HW |105 |403 |85 |
|
||||
| FM_Demodulation |FM_Demodulation |7 |280 |49 |
|
||||
| u_logic |cortexm0ds_logic |18489 |1302 |14 |
|
||||
| u_logic |cortexm0ds_logic |18681 |1318 |14 |
|
||||
+--------------------------------------------------------------+
|
||||
|
||||
@ -1,13 +1,13 @@
|
||||
module CW_TOP_WRAPPER(jtdi, jtck, jrstn, jscan, jshift, jupdate, jtdo, non_bus_din, bus_din, trig_clk, wt_ce, wt_en, wt_addr);
|
||||
localparam DEFAULT_CTRL_REG_LEN = 231;
|
||||
localparam DEFAULT_CTRL_REG_LEN = 223;
|
||||
localparam DEFAULT_STAT_REG_LEN = 18;
|
||||
localparam DEFAULT_STOP_LEN = 2730;
|
||||
localparam DEFAULT_NON_BUS_NODE_NUM = 2;
|
||||
localparam DEFAULT_NON_BUS_NODE_NUM = 0;
|
||||
localparam DEFAULT_BUS_NODE_NUM = 48;
|
||||
localparam DEFAULT_BUS_NUM = 3;
|
||||
localparam DEFAULT_BUS1_WIDTH = 32;
|
||||
localparam DEFAULT_BUS2_WIDTH = 3;
|
||||
localparam DEFAULT_BUS3_WIDTH = 13;
|
||||
localparam DEFAULT_BUS1_WIDTH = 16;
|
||||
localparam DEFAULT_BUS2_WIDTH = 16;
|
||||
localparam DEFAULT_BUS3_WIDTH = 16;
|
||||
input jtdi;
|
||||
input jtck;
|
||||
input jrstn;
|
||||
|
||||
312
project/rssi.cwc
312
project/rssi.cwc
File diff suppressed because one or more lines are too long
275091
project/simulation/MMC.sdf
275091
project/simulation/MMC.sdf
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because one or more lines are too long
120
rtl/peripherals/KeyScan.v
Normal file
120
rtl/peripherals/KeyScan.v
Normal file
@ -0,0 +1,120 @@
|
||||
module keyboard_scan(clk,col,row,key);
|
||||
input clk;
|
||||
input [3:0] col;
|
||||
output reg [3:0] row = 4'b1110;
|
||||
output reg [15:0] key;
|
||||
reg [31:0] cnt = 0;
|
||||
reg scan_clk = 0;
|
||||
always@(posedge clk) begin
|
||||
if(cnt == 2499) begin
|
||||
cnt <= 0;
|
||||
scan_clk <= ~scan_clk;
|
||||
end
|
||||
else
|
||||
cnt <= cnt + 1;
|
||||
end
|
||||
always@(posedge scan_clk)
|
||||
row <= {row[2:0],row[3]};
|
||||
always@(negedge scan_clk)
|
||||
case(row)
|
||||
4'b1110 : key[3:0] <= col;
|
||||
4'b1101 : key[7:4] <= col;
|
||||
4'b1011 : key[11:8] <= col;
|
||||
4'b0111 : key[15:12] <= col;
|
||||
default : key <= 0;
|
||||
endcase
|
||||
endmodule
|
||||
|
||||
module key_filter(clk,rstn,key_in,key_deb,en);
|
||||
input clk;
|
||||
input rstn;
|
||||
input [15:0] key_in;
|
||||
output [15:0] key_deb;
|
||||
output en;
|
||||
// Counting
|
||||
reg [19:0] cnt = 0;
|
||||
parameter CNTMAX = 999_999;
|
||||
always@(posedge clk or negedge rstn) begin
|
||||
if(~rstn)
|
||||
cnt <= 0;
|
||||
else if(cnt == CNTMAX)
|
||||
cnt <= 0;
|
||||
else
|
||||
cnt <= cnt + 1'b1;
|
||||
end
|
||||
// Sampling
|
||||
reg [15:0] key_reg0;
|
||||
reg [15:0] key_reg1;
|
||||
reg [15:0] key_reg2;
|
||||
always@(posedge clk or negedge rstn) begin
|
||||
if(~rstn) begin
|
||||
key_reg0 <= 16'hffff;
|
||||
key_reg1 <= 16'hffff;
|
||||
key_reg2 <= 16'hffff;
|
||||
end
|
||||
else if(cnt == CNTMAX) begin
|
||||
key_reg0 <= key_in;
|
||||
key_reg1 <= key_reg0;
|
||||
key_reg2 <= key_reg1;
|
||||
end
|
||||
end
|
||||
assign key_deb = (~key_reg0&~key_reg1& ~key_reg2)|(~key_reg0&~key_reg1&key_reg2);
|
||||
// State_machine
|
||||
parameter s0 = 1'b0 ;
|
||||
parameter s1 = 1'b1 ;
|
||||
reg [2:0] current_state ; //statement
|
||||
reg [2:0] next_state ; //statement
|
||||
reg [15:0] key_debb;// define the intermediate variable
|
||||
reg en;
|
||||
always@(posedge clk or negedge rstn) begin
|
||||
if(~rstn) begin
|
||||
current_state <= s0;
|
||||
next_state <= s0;
|
||||
end
|
||||
else begin
|
||||
current_state <= next_state;
|
||||
key_debb <= key_deb;
|
||||
case(current_state)
|
||||
s0:if(key_deb == key_debb) begin//s0
|
||||
next_state <= s0;
|
||||
en <= 0;
|
||||
end
|
||||
else begin
|
||||
next_state <= s1;
|
||||
en <= 1;
|
||||
end
|
||||
s1:if(key_deb == key_debb) begin//s1
|
||||
next_state <= s1;
|
||||
en <= 0;
|
||||
end
|
||||
else begin
|
||||
next_state <= s0;
|
||||
en <= 0;
|
||||
end
|
||||
default:next_state<=s0;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
||||
module pulse_gen
|
||||
(
|
||||
input clk,
|
||||
input RSTn,
|
||||
input [15:0] key_signal,
|
||||
output [15:0] pulse
|
||||
);
|
||||
reg [15:0] key_reg_1;
|
||||
reg [15:0] key_reg_2;
|
||||
always @(posedge clk or negedge RSTn) begin
|
||||
if (~RSTn) begin
|
||||
key_reg_1 <= 0;
|
||||
key_reg_2 <= 0;
|
||||
end
|
||||
else begin
|
||||
key_reg_1 <= key_signal;
|
||||
key_reg_2 <= key_reg_1;
|
||||
end
|
||||
end
|
||||
assign pulse = (key_signal) & (~key_reg_2);
|
||||
endmodule
|
||||
@ -17,7 +17,9 @@ module CortexM0_SoC #(
|
||||
output wire MSI_SCLK,
|
||||
output wire audio_pwm,
|
||||
output wire [3:0] sel,
|
||||
output wire [7:0] seg
|
||||
output wire [7:0] seg,
|
||||
input wire [3:0] col,
|
||||
output wire [3:0] row
|
||||
);
|
||||
|
||||
|
||||
@ -42,9 +44,14 @@ wire interrupt_UART;
|
||||
wire interrupt_IQ_done;
|
||||
wire Demo_Dump_Done_Interrupt;
|
||||
wire RSSI_interrupt;
|
||||
/*Connect the IRQ with UART*/
|
||||
assign IRQ = {28'b0,RSSI_interrupt,Demo_Dump_Done_Interrupt,interrupt_IQ_done,interrupt_UART};
|
||||
|
||||
wire [15:0] key_interrupt;
|
||||
wire [15:0] key_in;
|
||||
wire [15:0] key_out;
|
||||
/*Set IRQ*/
|
||||
assign IRQ = {12'b0,key_interrupt,RSSI_interrupt,Demo_Dump_Done_Interrupt,interrupt_IQ_done,interrupt_UART};
|
||||
keyboard_scan scan_unit(clk,col,row,key_in);
|
||||
key_filter filter_unit(.clk(clk),.rstn(RSTn),.key_in(key_in),.key_deb(key_out),.en());
|
||||
pulse_gen pulse_gen_unit(clk,RSTn,key_out,key_interrupt);
|
||||
/***************************/
|
||||
|
||||
wire RXEV;
|
||||
|
||||
@ -74,8 +74,7 @@ void ChannelSelection_control(unsigned int data)
|
||||
else if(data=='C')
|
||||
{
|
||||
singleFrequencyRSSI();
|
||||
UARTString("RSSI SCAN START!");
|
||||
WriteUART('\n');
|
||||
UARTString(" RSSI SCAN START! \n");
|
||||
RSSI_scan_cmd();
|
||||
}
|
||||
else if(data=='U') // Dump IQ data
|
||||
@ -379,12 +378,20 @@ void ChannelSelection_control(unsigned int data)
|
||||
|
||||
|
||||
|
||||
else if(data=='1') // formal FM receiver
|
||||
else if(data=='1') // formal FM receiver
|
||||
{
|
||||
MSI_SPI_Data = 0x00043420; //reg 0: 24M clk
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x0028bb85; //reg5: THRESH=3000
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
REG2 = 0x210002; //Reg2: INT=33,FRAC=0 99.0MHz in Shanghai
|
||||
REG2 = 0x210002; //Reg2: INT=33,FRAC=0 99.0MHz in Shanghai
|
||||
REG2 = 0x210002; //Reg2: INT=33,FRAC=0 99.0MHz in Shanghai
|
||||
REG2 = 0x210002; //Reg2: INT=33,FRAC=0 99.0MHz in Shanghai
|
||||
REG2 = 0x210002; //Reg2: INT=33,FRAC=0 99.0MHz in Shanghai
|
||||
REG2 = 0x210002; //Reg2: INT=33,FRAC=0 99.0MHz in Shanghai
|
||||
REG2 = 0x210002; //Reg2: INT=33,FRAC=0 99.0MHz in Shanghai
|
||||
REG2 = 0x210002; //Reg2: INT=33,FRAC=0 99.0MHz in Shanghai
|
||||
REG2 = 0x210002; //Reg2: INT=33,FRAC=0 99.0MHz in Shanghai
|
||||
SPI_RFD(REG2);
|
||||
MSI_SPI_Data = 0x0000e141; //Reg1: BB Gain decrease 20dB LNA Gain redcution: 23dB
|
||||
@ -410,12 +417,20 @@ void ChannelSelection_control(unsigned int data)
|
||||
UARTString(" Channel: 99.0MHz ");
|
||||
WriteUART('\n');
|
||||
}
|
||||
else if(data=='2') // formal FM receiver
|
||||
else if(data=='2') // formal FM receiver
|
||||
{
|
||||
MSI_SPI_Data = 0x00043420; //reg 0: 24M clk
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x0028bb85; //reg5: THRESH=3000
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
REG2 = 0x1e3842; //Reg2: INT=30,FRAC=900 97.7MHz in Shanghai
|
||||
REG2 = 0x1e3842; //Reg2: INT=30,FRAC=900 97.7MHz in Shanghai
|
||||
REG2 = 0x1e3842; //Reg2: INT=30,FRAC=900 97.7MHz in Shanghai
|
||||
REG2 = 0x1e3842; //Reg2: INT=30,FRAC=900 97.7MHz in Shanghai
|
||||
REG2 = 0x1e3842; //Reg2: INT=30,FRAC=900 97.7MHz in Shanghai
|
||||
REG2 = 0x1e3842; //Reg2: INT=30,FRAC=900 97.7MHz in Shanghai
|
||||
REG2 = 0x1e3842; //Reg2: INT=30,FRAC=900 97.7MHz in Shanghai
|
||||
REG2 = 0x1e3842; //Reg2: INT=30,FRAC=900 97.7MHz in Shanghai
|
||||
REG2 = 0x1e3842; //Reg2: INT=30,FRAC=900 97.7MHz in Shanghai
|
||||
SPI_RFD(REG2);
|
||||
MSI_SPI_Data = 0x0000e141; //Reg1: BB Gain decrease 20dB LNA Gain redcution: 23dB
|
||||
@ -436,12 +451,20 @@ void ChannelSelection_control(unsigned int data)
|
||||
ChannelControlDisplay.INT =FM_current_INT;
|
||||
ChannelControlDisplay.FRAC =FM_current_FRAC;
|
||||
Channel_control(ChannelControlDisplay);
|
||||
Channel_control(ChannelControlDisplay);
|
||||
Channel_control(ChannelControlDisplay);
|
||||
Channel_control(ChannelControlDisplay);
|
||||
Channel_control(ChannelControlDisplay);
|
||||
Channel_control(ChannelControlDisplay);
|
||||
Channel_control(ChannelControlDisplay);
|
||||
Channel_control(ChannelControlDisplay);
|
||||
Channel_control(ChannelControlDisplay);
|
||||
|
||||
|
||||
UARTString(" Channel: 90.9MHz ");
|
||||
WriteUART('\n');
|
||||
}
|
||||
else if(data=='3') // formal FM receiver
|
||||
else if(data=='3') // formal FM receiver
|
||||
{
|
||||
MSI_SPI_Data = 0x00043420; //reg 0: 24M clk
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
@ -471,7 +494,7 @@ void ChannelSelection_control(unsigned int data)
|
||||
UARTString(" Channel: 94.0MHz ");
|
||||
WriteUART('\n');
|
||||
}
|
||||
else if(data=='4') // formal FM receiver
|
||||
else if(data=='4') // formal FM receiver
|
||||
{
|
||||
MSI_SPI_Data = 0x00043420; //reg 0: 24M clk
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
@ -742,7 +765,6 @@ else if(data=='x') // formal FM receiver
|
||||
UARTString(" Channel: 101.7MHz Donggan 101.7 ");
|
||||
WriteUART('\n');
|
||||
}
|
||||
|
||||
else if(data=='v') // formal FM receiver
|
||||
{
|
||||
MSI_SPI_Data = 0x00043420; //reg 0: 24M clk
|
||||
@ -776,7 +798,6 @@ else if(data=='v') // formal FM receiver
|
||||
UARTString(" Channel: 98.1MHz ");
|
||||
WriteUART('\n');
|
||||
}
|
||||
|
||||
else if(data=='w') // formal FM receiver
|
||||
{
|
||||
MSI_SPI_Data = 0x00043420; //reg 0: 24M clk
|
||||
@ -843,7 +864,6 @@ else if(data=='a') // formal FM receiver
|
||||
UARTString(" Channel: 100.9 MHz ");
|
||||
WriteUART('\n');
|
||||
}
|
||||
|
||||
else if(data=='b') // formal FM receiver
|
||||
{
|
||||
MSI_SPI_Data = 0x00043420; //reg 0: 24M clk
|
||||
@ -877,7 +897,6 @@ else if(data=='b') // formal FM receiver
|
||||
UARTString(" Channel: 103.7 MHz ");
|
||||
WriteUART('\n');
|
||||
}
|
||||
|
||||
else if(data=='c') // formal FM receiver
|
||||
{
|
||||
MSI_SPI_Data = 0x00043420; //reg 0: 24M clk
|
||||
@ -911,7 +930,6 @@ else if(data=='c') // formal FM receiver
|
||||
UARTString(" Channel: 102.7 MHz ");
|
||||
WriteUART('\n');
|
||||
}
|
||||
|
||||
else if(data=='d') // formal FM receiver
|
||||
{
|
||||
MSI_SPI_Data = 0x00043420; //reg 0: 24M clk
|
||||
@ -945,7 +963,6 @@ else if(data=='d') // formal FM receiver
|
||||
UARTString(" Channel: 106.5 MHz ");
|
||||
WriteUART('\n');
|
||||
}
|
||||
|
||||
else if(data=='e') // formal FM receiver
|
||||
{
|
||||
MSI_SPI_Data = 0x00043420; //reg 0: 24M clk
|
||||
@ -979,7 +996,6 @@ else if(data=='e') // formal FM receiver
|
||||
UARTString(" Channel: 107.2 MHz ");
|
||||
WriteUART('\n');
|
||||
}
|
||||
|
||||
else if(data=='h') // formal FM receiver
|
||||
{
|
||||
MSI_SPI_Data = 0x00043420; //reg 0: 24M clk
|
||||
@ -1016,7 +1032,6 @@ else if(data=='h') // formal FM receiver
|
||||
|
||||
else
|
||||
{
|
||||
|
||||
UARTString(" Wrong command! ");
|
||||
WriteUART('\n');
|
||||
}
|
||||
|
||||
218
src/code_def.c
218
src/code_def.c
@ -5,15 +5,14 @@
|
||||
#define RSSI_Base 0x60000050
|
||||
#define STEP 0.02
|
||||
#define NUM 1060
|
||||
#define OUTNUM 16
|
||||
#define Thresh 1900
|
||||
|
||||
//global variables
|
||||
float freq_I=87.0;
|
||||
RSSIType rssilist[NUM];
|
||||
int rssi_index=0;
|
||||
/*
|
||||
//Insert your output declaration here
|
||||
|
||||
*/
|
||||
ChannelControlType channelcontrollist[OUTNUM];
|
||||
|
||||
/*
|
||||
|
||||
@ -202,6 +201,16 @@ void singleFrequencyRSSI()
|
||||
int AFC=0;
|
||||
SPIwrite(INT,FRAC,AFC,Gain);
|
||||
}
|
||||
|
||||
void regWrite(float freq)
|
||||
{
|
||||
int INT=floor(freq/3);
|
||||
int FRAC=(freq/3-INT)*3000;
|
||||
int Gain=15;
|
||||
int AFC=0;
|
||||
SPIwrite(INT,FRAC,AFC,Gain);
|
||||
}
|
||||
|
||||
void RSSI_scan_cmd(void)
|
||||
{
|
||||
(*(volatile unsigned int *)FM_Control_Base)=( unsigned int)256;
|
||||
@ -231,19 +240,206 @@ void RSSIScanHandler(void)
|
||||
rssi_index=0;
|
||||
#ifndef SIM_PROFILE
|
||||
// Used for Debug mode.
|
||||
/*
|
||||
for(j=0;j<NUM;j++){
|
||||
UARTString(int_to_str(rssilist[j].RSSI));
|
||||
UARTString("\n");
|
||||
}
|
||||
#endif
|
||||
/*
|
||||
//The function is supposed to be called here.
|
||||
|
||||
*/
|
||||
#endif
|
||||
RSSIScanscreen();
|
||||
UARTString("Scan done!\n");
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
//Insert the complete function here
|
||||
void RSSIScanscreen()
|
||||
{
|
||||
int i, j, k, n, rssi[OUTNUM];
|
||||
float temp, freq;
|
||||
freq = 87;
|
||||
i = 0;
|
||||
n = 1;
|
||||
for (j = 0; freq += STEP, j < (NUM - 10); j++)
|
||||
{
|
||||
if (rssilist[j].RSSI < Thresh)
|
||||
continue;
|
||||
if ((rssilist[j].RSSI >= rssilist[j - 12].RSSI * 4) && (rssilist[j].RSSI >= rssilist[j + 12].RSSI * 4))
|
||||
{
|
||||
for (k = 0; (k <= i) && (k < 16); k++)
|
||||
if ((freq - channelcontrollist[k].freq) < 0.2)
|
||||
{
|
||||
channelcontrollist[k].freq = (channelcontrollist[k].freq * n + freq) / (n + 1);
|
||||
n += 1;
|
||||
break;
|
||||
}
|
||||
if ((k <= i) && (k < 16))
|
||||
continue;
|
||||
else if (i == 0)
|
||||
{
|
||||
channelcontrollist[i].freq = freq;
|
||||
rssi[i] = rssilist[j].RSSI;
|
||||
i += 1;
|
||||
}
|
||||
else if (i < OUTNUM)
|
||||
{
|
||||
channelcontrollist[i].freq = freq;
|
||||
rssi[i] = rssilist[j].RSSI;
|
||||
if (rssilist[j].RSSI < rssi[0])
|
||||
{
|
||||
rssi[i] = rssi[0];
|
||||
rssi[0] = rssilist[j].RSSI;
|
||||
channelcontrollist[i].freq = channelcontrollist[0].freq;
|
||||
channelcontrollist[0].freq = freq;
|
||||
}
|
||||
i += 1;
|
||||
}
|
||||
else if (rssilist[j].RSSI > rssi[0])
|
||||
{
|
||||
rssi[0] = rssilist[j].RSSI;
|
||||
channelcontrollist[0].freq = freq;
|
||||
Bubbling(rssi);
|
||||
}
|
||||
else
|
||||
continue;
|
||||
n = 1;
|
||||
}
|
||||
|
||||
*/
|
||||
}
|
||||
for (i = 0; i < OUTNUM; i++)
|
||||
for (j = 1; j < (OUTNUM - i); j++)
|
||||
{
|
||||
if (channelcontrollist[j].freq < channelcontrollist[j - 1].freq)
|
||||
{
|
||||
temp = channelcontrollist[j].freq;
|
||||
channelcontrollist[j].freq = channelcontrollist[j - 1].freq;
|
||||
channelcontrollist[j - 1].freq = temp;
|
||||
}
|
||||
}
|
||||
for (i = 0; i < OUTNUM; i++)
|
||||
{
|
||||
channelcontrollist[i].INT = floor(channelcontrollist[i].freq / 3);
|
||||
channelcontrollist[i].FRAC = (channelcontrollist[i].freq / 3 - channelcontrollist[i].INT) * 3000;
|
||||
channelcontrollist[i].channel_no = i+1;
|
||||
}
|
||||
}
|
||||
|
||||
int Bubbling(int* rssi)
|
||||
{
|
||||
int i, j, k;
|
||||
float temp;
|
||||
for (i = 0; i < OUTNUM; i++)
|
||||
for (j = 1; j < (OUTNUM - i); j++)
|
||||
{
|
||||
if (rssi[j] < rssi[j - 1])
|
||||
{
|
||||
k = rssi[j];
|
||||
rssi[j] = rssi[j - 1];
|
||||
rssi[j - 1] = k;
|
||||
temp = channelcontrollist[j].freq;
|
||||
channelcontrollist[j].freq = channelcontrollist[j - 1].freq;
|
||||
channelcontrollist[j - 1].freq = temp;
|
||||
}
|
||||
}
|
||||
return rssi[0];
|
||||
}
|
||||
|
||||
|
||||
|
||||
//Key_interrupt handlers
|
||||
void KEY0(void)
|
||||
{
|
||||
UARTString("Channel0\n");
|
||||
regWrite(channelcontrollist[0].freq);
|
||||
Channel_control(channelcontrollist[0]);
|
||||
}
|
||||
void KEY1(void)
|
||||
{
|
||||
UARTString("Channel1\n");
|
||||
regWrite(channelcontrollist[1].freq);
|
||||
Channel_control(channelcontrollist[1]);
|
||||
}
|
||||
void KEY2(void)
|
||||
{
|
||||
UARTString("Channel2\n");
|
||||
regWrite(channelcontrollist[2].freq);
|
||||
Channel_control(channelcontrollist[2]);
|
||||
}
|
||||
void KEY3(void)
|
||||
{
|
||||
UARTString("Channel3\n");
|
||||
regWrite(channelcontrollist[3].freq);
|
||||
Channel_control(channelcontrollist[3]);
|
||||
}
|
||||
void KEY4(void)
|
||||
{
|
||||
UARTString("Channel4\n");
|
||||
regWrite(channelcontrollist[4].freq);
|
||||
Channel_control(channelcontrollist[4]);
|
||||
}
|
||||
void KEY5(void)
|
||||
{
|
||||
UARTString("Channel5\n");
|
||||
regWrite(channelcontrollist[5].freq);
|
||||
Channel_control(channelcontrollist[5]);
|
||||
}
|
||||
void KEY6(void)
|
||||
{
|
||||
UARTString("Channel6\n");
|
||||
regWrite(channelcontrollist[6].freq);
|
||||
Channel_control(channelcontrollist[6]);
|
||||
}
|
||||
void KEY7(void)
|
||||
{
|
||||
UARTString("Channel7\n");
|
||||
regWrite(channelcontrollist[7].freq);
|
||||
Channel_control(channelcontrollist[7]);
|
||||
}
|
||||
void KEY8(void)
|
||||
{
|
||||
UARTString("Channel8\n");
|
||||
regWrite(channelcontrollist[8].freq);
|
||||
Channel_control(channelcontrollist[8]);
|
||||
}
|
||||
void KEY9(void)
|
||||
{
|
||||
UARTString("Channel9\n");
|
||||
regWrite(channelcontrollist[9].freq);
|
||||
Channel_control(channelcontrollist[9]);
|
||||
}
|
||||
void KEY10(void)
|
||||
{
|
||||
UARTString("Channel10\n");
|
||||
regWrite(channelcontrollist[10].freq);
|
||||
Channel_control(channelcontrollist[10]);
|
||||
}
|
||||
void KEY11(void)
|
||||
{
|
||||
UARTString("Channel11\n");
|
||||
regWrite(channelcontrollist[11].freq);
|
||||
Channel_control(channelcontrollist[11]);
|
||||
}
|
||||
void KEY12(void)
|
||||
{
|
||||
UARTString("Channel12\n");
|
||||
regWrite(channelcontrollist[12].freq);
|
||||
Channel_control(channelcontrollist[12]);
|
||||
}
|
||||
void KEY13(void)
|
||||
{
|
||||
UARTString("Channel13\n");
|
||||
regWrite(channelcontrollist[13].freq);
|
||||
Channel_control(channelcontrollist[13]);
|
||||
}
|
||||
void KEY14(void)
|
||||
{
|
||||
UARTString("Channel14\n");
|
||||
regWrite(channelcontrollist[14].freq);
|
||||
Channel_control(channelcontrollist[14]);
|
||||
}
|
||||
void KEY15(void)
|
||||
{
|
||||
UARTString("Channel15\n");
|
||||
regWrite(channelcontrollist[15].freq);
|
||||
Channel_control(channelcontrollist[15]);
|
||||
}
|
||||
|
||||
@ -70,8 +70,24 @@ void SPIwrite(int INT, int FRAC, int AFC, int Gain);
|
||||
int RSSI_Read(void);
|
||||
void RSSIScanHandler(void);
|
||||
void RSSI_scan_cmd(void);
|
||||
/*
|
||||
//Insert your Function declaration here
|
||||
void RSSIScanscreen(void);
|
||||
int Bubbling(int* rssi);
|
||||
void regWrite(float freq);
|
||||
|
||||
|
||||
*/
|
||||
//Key interrupt handlers
|
||||
void KEY0(void);
|
||||
void KEY1(void);
|
||||
void KEY2(void);
|
||||
void KEY3(void);
|
||||
void KEY4(void);
|
||||
void KEY5(void);
|
||||
void KEY6(void);
|
||||
void KEY7(void);
|
||||
void KEY8(void);
|
||||
void KEY9(void);
|
||||
void KEY10(void);
|
||||
void KEY11(void);
|
||||
void KEY12(void);
|
||||
void KEY13(void);
|
||||
void KEY14(void);
|
||||
void KEY15(void);
|
||||
|
||||
@ -7,14 +7,12 @@
|
||||
|
||||
int main()
|
||||
{
|
||||
|
||||
NVIC_CTRL_ADDR = 0xFFFFF; //enable lowest 2 interrupts
|
||||
/*
|
||||
char string[32] = {0};
|
||||
|
||||
unsigned int MSI_SPI_Data= 0;
|
||||
ChannelControlType ChannelControlDisplay;
|
||||
|
||||
NVIC_CTRL_ADDR = 15; //enable lowest 2 interrupts
|
||||
/*
|
||||
MSI_SPI_Data = 0x00043420; //reg 0: 24M clk
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x0028bb85; //reg5: THRESH=3000
|
||||
@ -46,12 +44,12 @@ int main()
|
||||
Channel_control(ChannelControlDisplay);
|
||||
|
||||
Start_FM_command();
|
||||
IQ_Dump_data();
|
||||
*/
|
||||
|
||||
|
||||
|
||||
|
||||
//IQ_Dump_command();
|
||||
while(1)
|
||||
{
|
||||
|
||||
|
||||
@ -78,6 +78,22 @@ __Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD FM_IQ_Dump_Done ; IRQ1 Handler
|
||||
DCD Demodulated_Data_Dump_Done; IRQ2 Handler
|
||||
DCD RSSI_Scan_Done ; IRQ3 Handler
|
||||
DCD KEY15_Handler ; IRQ4 Handler
|
||||
DCD KEY14_Handler ; IRQ5 Handler
|
||||
DCD KEY13_Handler ; IRQ6 Handler
|
||||
DCD KEY12_Handler ; IRQ7 Handler
|
||||
DCD KEY11_Handler ; IRQ8 Handler
|
||||
DCD KEY10_Handler ; IRQ9 Handler
|
||||
DCD KEY9_Handler ; IRQ10 Handler
|
||||
DCD KEY8_Handler ; IRQ11 Handler
|
||||
DCD KEY7_Handler ; IRQ12 Handler
|
||||
DCD KEY6_Handler ; IRQ13 Handler
|
||||
DCD KEY5_Handler ; IRQ14 Handler
|
||||
DCD KEY4_Handler ; IRQ15 Handler
|
||||
DCD KEY3_Handler ; IRQ16 Handler
|
||||
DCD KEY2_Handler ; IRQ17 Handler
|
||||
DCD KEY1_Handler ; IRQ18 Handler
|
||||
DCD KEY0_Handler ; IRQ19 Handler
|
||||
|
||||
|
||||
|
||||
@ -136,6 +152,133 @@ RSSI_Scan_Done PROC
|
||||
POP {R0,R1,R2,PC}
|
||||
ENDP
|
||||
|
||||
KEY0_Handler PROC
|
||||
EXPORT KEY0_Handler [WEAK]
|
||||
IMPORT KEY0
|
||||
PUSH {R0,R1,R2,LR}
|
||||
BL KEY0
|
||||
POP {R0,R1,R2,PC}
|
||||
ENDP
|
||||
|
||||
KEY1_Handler PROC
|
||||
EXPORT KEY1_Handler [WEAK]
|
||||
IMPORT KEY1
|
||||
PUSH {R0,R1,R2,LR}
|
||||
BL KEY1
|
||||
POP {R0,R1,R2,PC}
|
||||
ENDP
|
||||
|
||||
KEY2_Handler PROC
|
||||
EXPORT KEY2_Handler [WEAK]
|
||||
IMPORT KEY2
|
||||
PUSH {R0,R1,R2,LR}
|
||||
BL KEY2
|
||||
POP {R0,R1,R2,PC}
|
||||
ENDP
|
||||
|
||||
KEY3_Handler PROC
|
||||
EXPORT KEY3_Handler [WEAK]
|
||||
IMPORT KEY3
|
||||
PUSH {R0,R1,R2,LR}
|
||||
BL KEY3
|
||||
POP {R0,R1,R2,PC}
|
||||
ENDP
|
||||
|
||||
KEY4_Handler PROC
|
||||
EXPORT KEY4_Handler [WEAK]
|
||||
IMPORT KEY4
|
||||
PUSH {R0,R1,R2,LR}
|
||||
BL KEY4
|
||||
POP {R0,R1,R2,PC}
|
||||
ENDP
|
||||
|
||||
KEY5_Handler PROC
|
||||
EXPORT KEY5_Handler [WEAK]
|
||||
IMPORT KEY5
|
||||
PUSH {R0,R1,R2,LR}
|
||||
BL KEY5
|
||||
POP {R0,R1,R2,PC}
|
||||
ENDP
|
||||
|
||||
KEY6_Handler PROC
|
||||
EXPORT KEY6_Handler [WEAK]
|
||||
IMPORT KEY6
|
||||
PUSH {R0,R1,R2,LR}
|
||||
BL KEY6
|
||||
POP {R0,R1,R2,PC}
|
||||
ENDP
|
||||
|
||||
KEY7_Handler PROC
|
||||
EXPORT KEY7_Handler [WEAK]
|
||||
IMPORT KEY7
|
||||
PUSH {R0,R1,R2,LR}
|
||||
BL KEY7
|
||||
POP {R0,R1,R2,PC}
|
||||
ENDP
|
||||
|
||||
KEY8_Handler PROC
|
||||
EXPORT KEY8_Handler [WEAK]
|
||||
IMPORT KEY8
|
||||
PUSH {R0,R1,R2,LR}
|
||||
BL KEY8
|
||||
POP {R0,R1,R2,PC}
|
||||
ENDP
|
||||
|
||||
KEY9_Handler PROC
|
||||
EXPORT KEY9_Handler [WEAK]
|
||||
IMPORT KEY9
|
||||
PUSH {R0,R1,R2,LR}
|
||||
BL KEY9
|
||||
POP {R0,R1,R2,PC}
|
||||
ENDP
|
||||
|
||||
KEY10_Handler PROC
|
||||
EXPORT KEY10_Handler [WEAK]
|
||||
IMPORT KEY10
|
||||
PUSH {R0,R1,R2,LR}
|
||||
BL KEY10
|
||||
POP {R0,R1,R2,PC}
|
||||
ENDP
|
||||
|
||||
KEY11_Handler PROC
|
||||
EXPORT KEY11_Handler [WEAK]
|
||||
IMPORT KEY11
|
||||
PUSH {R0,R1,R2,LR}
|
||||
BL KEY11
|
||||
POP {R0,R1,R2,PC}
|
||||
ENDP
|
||||
|
||||
KEY12_Handler PROC
|
||||
EXPORT KEY12_Handler [WEAK]
|
||||
IMPORT KEY12
|
||||
PUSH {R0,R1,R2,LR}
|
||||
BL KEY12
|
||||
POP {R0,R1,R2,PC}
|
||||
ENDP
|
||||
|
||||
KEY13_Handler PROC
|
||||
EXPORT KEY13_Handler [WEAK]
|
||||
IMPORT KEY13
|
||||
PUSH {R0,R1,R2,LR}
|
||||
BL KEY13
|
||||
POP {R0,R1,R2,PC}
|
||||
ENDP
|
||||
|
||||
KEY14_Handler PROC
|
||||
EXPORT KEY14_Handler [WEAK]
|
||||
IMPORT KEY14
|
||||
PUSH {R0,R1,R2,LR}
|
||||
BL KEY14
|
||||
POP {R0,R1,R2,PC}
|
||||
ENDP
|
||||
|
||||
KEY15_Handler PROC
|
||||
EXPORT KEY15_Handler [WEAK]
|
||||
IMPORT KEY15
|
||||
PUSH {R0,R1,R2,LR}
|
||||
BL KEY15
|
||||
POP {R0,R1,R2,PC}
|
||||
ENDP
|
||||
|
||||
ALIGN 4
|
||||
|
||||
|
||||
@ -1,11 +0,0 @@
|
||||
load RSSI_Scan.mat;
|
||||
figure(1);
|
||||
plot(linspace(87.02,107.98,1050),Dec_list);
|
||||
title('RSSI Dec_list')
|
||||
xlabel('Frequency(KHz)')
|
||||
ylabel('RSSI')
|
||||
figure(2);
|
||||
plot(Log_list);
|
||||
title('RSSI evaluation centered of real station channel')
|
||||
xlabel('Frequency(KHz)')
|
||||
ylabel('RSSI')
|
||||
@ -1,11 +1,11 @@
|
||||
load RSSI_Scan.mat;
|
||||
figure(1);
|
||||
plot(linspace(87.02,108,1050),Dec_list);
|
||||
title('RSSI Dec_list')
|
||||
title('RSSI Dec\_list')
|
||||
xlabel('Frequency(KHz)')
|
||||
ylabel('RSSI')
|
||||
figure(2);
|
||||
plot(linspace(87.02,108,1050),Log_list);
|
||||
title('RSSI Log_list')
|
||||
title('RSSI Log\_list')
|
||||
xlabel('Frequency(KHz)')
|
||||
ylabel('RSSI')
|
||||
Loading…
x
Reference in New Issue
Block a user