Update

src/AHBsubordinate/AHBlite_IQfetcher.v

@@ -16,11 +16,15 @@ module AHBlite_IQfetcher(
 );
 
 assign HRESP = 1'b0;
+//HREADY should be customed to the completion time of the fetch.
 assign HREADYOUT = 1'b1;
 
 wire write_en;
 assign write_en = HSEL & HTRANS[1] & HWRITE & HREADY;
 
+wire read_en;
+assign read_en = HSEL & HTRANS[1] & (~HWRITE) & HREADY;
+
 reg addr_reg;
 always@(posedge HCLK or negedge HRESETn) begin
   if(~HRESETn) addr_reg <= 1'b0;
@@ -34,6 +38,13 @@ always@(posedge HCLK or negedge HRESETn) begin
   else wr_en_reg <= 1'b0;
 end
 
+reg rd_en_reg;
+always@(posedge HCLK or negedge HRESETn) begin
+  if(~HRESETn) rd_en_reg <= 1'b0;
+  else if(read_en) rd_en_reg <= 1'b1;
+  else rd_en_reg <= 1'b0;
+end
+
 always@(posedge HCLK) begin
     if(~HRESETn) begin
         fetch_en<=0;

src/peripherals/FIFO.v

@@ -1,19 +1,22 @@
 
 
 //it is just a normal FIFO
-module FIFO(
+module FIFO #(
+    parameter data_width = 8
+)
+    (
     input clock,
     input sclr,
 
     input rdreq, wrreq,
     output reg full, empty,
 
-    input [7 : 0] data,
-    output [7 : 0] q
+    input [data_width-1 : 0] data,
+    output [data_width-1 : 0] q
 
 );
 
-reg [7 : 0] mem [15 : 0];
+reg [data_width-1 : 0] mem [15 : 0];
 reg [3 : 0] wp, rp;
 reg w_flag, r_flag;
 

src/peripherals/IQbuffer.v

@@ -0,0 +1,49 @@
+module IQbuffer(
+    input [11:0] din,
+    input writerq,
+    input readrq,
+    input sclr,
+    input clk,
+    output [23:0] dout
+);
+    reg wr_rq_1 = 0;
+    reg wr_rq_2 = 1;
+    reg wr_reg = 0;
+    reg flag=0;
+    reg [11:0] dout_1 = 0;
+    reg [11:0] dout_2 = 0;
+    always@(posedge clk) begin
+        if((writerq==1)&&(flag==1)) wr_reg<=1;
+        else begin
+            wr_reg<=0;
+            flag<=1;
+        end
+    end
+    always@(posedge writerq) flag=1;
+    always@(posedge clk)
+    begin
+        if (wr_reg==1) begin
+            wr_rq_1 <= ~wr_rq_1;
+            wr_rq_2 <= ~wr_rq_2;
+        end
+    end
+    FIFO #(.data_width(12)) bf1(
+        .clk(clk),
+        .sclr(sclr),
+        .rdreq(readrq),
+        .wrreq(wr_rq_1),
+        .data(din),
+        .q(dout_1)
+    );
+
+    FIFO #(.data_width(12)) bf2(
+        .clk(clk),
+        .sclr(sclr),
+        .rdreq(readrq),
+        .wrreq(wr_rq_2),
+        .data(din),
+        .q(dout_2)
+    );
+
+    assign dout = {dout_1,dout_2};
+endmodule