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77
src/SOC/AHBlite_Block_RAM.v Normal file
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module AHBlite_Block_RAM #(
parameter ADDR_WIDTH = 14)(
input wire HCLK,
input wire HRESETn,
input wire HSEL,
input wire [31:0] HADDR,
input wire [1:0] HTRANS,
input wire [2:0] HSIZE,
input wire [3:0] HPROT,
input wire HWRITE,
input wire [31:0] HWDATA,
input wire HREADY,
output wire HREADYOUT,
output wire [31:0] HRDATA,
output wire [1:0] HRESP,
output wire [ADDR_WIDTH-1:0] BRAM_RDADDR,
output wire [ADDR_WIDTH-1:0] BRAM_WRADDR,
input wire [31:0] BRAM_RDATA,
output wire [31:0] BRAM_WDATA,
output wire [3:0] BRAM_WRITE
);
assign HRESP = 2'b0;
assign HRDATA = BRAM_RDATA;
wire trans_en;
assign trans_en = HSEL & HTRANS[1];
wire write_en;
assign write_en = trans_en & HWRITE;
wire read_en;
assign read_en = trans_en & (~HWRITE);
reg [3:0] size_dec;
always@(*) begin
case({HADDR[1:0],HSIZE[1:0]})
4'h0 : size_dec = 4'h1;
4'h1 : size_dec = 4'h3;
4'h2 : size_dec = 4'hf;
4'h4 : size_dec = 4'h2;
4'h8 : size_dec = 4'h4;
4'h9 : size_dec = 4'hc;
4'hc : size_dec = 4'h8;
default : size_dec = 4'h0;
endcase
end
reg [3:0] size_reg;
always@(posedge HCLK or negedge HRESETn) begin
if(~HRESETn) size_reg <= 0;
else if(write_en & HREADY) size_reg <= size_dec;
end
reg [ADDR_WIDTH-1:0] addr_reg;
always@(posedge HCLK or negedge HRESETn) begin
if(~HRESETn) addr_reg <= 0;
else if(trans_en & HREADY) addr_reg <= HADDR[(ADDR_WIDTH+1):2];
end
reg wr_en_reg;
always@(posedge HCLK or negedge HRESETn) begin
if(~HRESETn) wr_en_reg <= 1'b0;
else if(HREADY) wr_en_reg <= write_en;
else wr_en_reg <= 1'b0;
end
assign BRAM_RDADDR = HADDR[(ADDR_WIDTH+1):2];
assign BRAM_WRADDR = addr_reg;
assign HREADYOUT = 1'b1;
assign BRAM_WRITE = wr_en_reg ? size_reg : 4'h0;
assign BRAM_WDATA = HWDATA;
endmodule

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src/SOC/AHBlite_Decoder.v Normal file
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module AHBlite_Decoder
#(
/*RAMCODE enable parameter*/
parameter Port0_en = 1,
/************************/
/*WaterLight enable parameter*/
parameter Port1_en = 1,
/************************/
/*RAMDATA enable parameter*/
parameter Port2_en = 1,
/************************/
/*UART enable parameter*/
parameter Port3_en = 1
/************************/
)(
input [31:0] HADDR,
/*RAMCODE OUTPUT SELECTION SIGNAL*/
output wire P0_HSEL,
/*WaterLight OUTPUT SELECTION SIGNAL*/
output wire P1_HSEL,
/*RAMDATA OUTPUT SELECTION SIGNAL*/
output wire P2_HSEL,
/*UART OUTPUT SELECTION SIGNAL*/
output wire P3_HSEL
);
//RAMCODE-----------------------------------
//0x00000000-0x0000ffff
/*Insert RAMCODE decoder code there*/
assign P0_HSEL = (HADDR[31:16] == 16'h0000) ? Port0_en : 1'b0;
/***********************************/
//PERIPHRAL-----------------------------
//0X40000000 WaterLight MODE
//0x40000004 WaterLight SPEED
/*Insert WaterLight decoder code there*/
assign P2_HSEL = (HADDR[31:4] == 28'h4000000) ? Port2_en : 1'b0;
/***********************************/
//0x40000000 signal I
//0x40000000 signal Q
/*Insert ADB decoder code here*/
//0X40000010 UART RX DATA
//0X40000014 UART TX STATE
//0X40000018 UART TX DATA
/*Insert UART decoder code there*/
assign P3_HSEL = (HADDR[31:4] == 28'h4000001) ? Port3_en : 1'b0;
/***********************************/
//RAMDATA-----------------------------
//0X20000000-0X2000FFFF
/*Insert RAMDATA decoder code there*/
assign P1_HSEL = (HADDR[31:16] == 16'h2000) ? Port1_en : 1'b0;
/***********************************/
endmodule

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src/SOC/AHBlite_Interconnect.v Normal file
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module AHBlite_Interconnect(
// CLK & RST
input wire HCLK,
input wire HRESETn,
// CORE SIDE
input wire [31:0] HADDR,
input wire [2:0] HBURST,
input wire HMASTLOCK,
input wire [3:0] HPROT,
input wire [2:0] HSIZE,
input wire [1:0] HTRANS,
input wire [31:0] HWDATA,
input wire HWRITE,
output wire HREADY,
output wire [31:0] HRDATA,
output wire HRESP,
// Peripheral 0
output wire HSEL_P0,
output wire [31:0] HADDR_P0,
output wire [2:0] HBURST_P0,
output wire HMASTLOCK_P0,
output wire [3:0] HPROT_P0,
output wire [2:0] HSIZE_P0,
output wire [1:0] HTRANS_P0,
output wire [31:0] HWDATA_P0,
output wire HWRITE_P0,
output wire HREADY_P0,
input wire HREADYOUT_P0,
input wire [31:0] HRDATA_P0,
input wire HRESP_P0,
// Peripheral 1
output wire HSEL_P1,
output wire [31:0] HADDR_P1,
output wire [2:0] HBURST_P1,
output wire HMASTLOCK_P1,
output wire [3:0] HPROT_P1,
output wire [2:0] HSIZE_P1,
output wire [1:0] HTRANS_P1,
output wire [31:0] HWDATA_P1,
output wire HWRITE_P1,
output wire HREADY_P1,
input wire HREADYOUT_P1,
input wire [31:0] HRDATA_P1,
input wire HRESP_P1,
// Peripheral 2
output wire HSEL_P2,
output wire [31:0] HADDR_P2,
output wire [2:0] HBURST_P2,
output wire HMASTLOCK_P2,
output wire [3:0] HPROT_P2,
output wire [2:0] HSIZE_P2,
output wire [1:0] HTRANS_P2,
output wire [31:0] HWDATA_P2,
output wire HWRITE_P2,
output wire HREADY_P2,
input wire HREADYOUT_P2,
input wire [31:0] HRDATA_P2,
input wire HRESP_P2,
// Peripheral 3
output wire HSEL_P3,
output wire [31:0] HADDR_P3,
output wire [2:0] HBURST_P3,
output wire HMASTLOCK_P3,
output wire [3:0] HPROT_P3,
output wire [2:0] HSIZE_P3,
output wire [1:0] HTRANS_P3,
output wire [31:0] HWDATA_P3,
output wire HWRITE_P3,
output wire HREADY_P3,
input wire HREADYOUT_P3,
input wire [31:0] HRDATA_P3,
input wire HRESP_P3
);
// Public signals--------------------------------
//-----------------------------------------------
// HADDR
assign HADDR_P0 = HADDR;
assign HADDR_P1 = HADDR;
assign HADDR_P2 = HADDR;
assign HADDR_P3 = HADDR;
// HBURST
assign HBURST_P0 = HBURST;
assign HBURST_P1 = HBURST;
assign HBURST_P2 = HBURST;
assign HBURST_P3 = HBURST;
// HMASTLOCK
assign HMASTLOCK_P0 = HMASTLOCK;
assign HMASTLOCK_P1 = HMASTLOCK;
assign HMASTLOCK_P2 = HMASTLOCK;
assign HMASTLOCK_P3 = HMASTLOCK;
// HPROT
assign HPROT_P0 = HPROT;
assign HPROT_P1 = HPROT;
assign HPROT_P2 = HPROT;
assign HPROT_P3 = HPROT;
// HSIZE
assign HSIZE_P0 = HSIZE;
assign HSIZE_P1 = HSIZE;
assign HSIZE_P2 = HSIZE;
assign HSIZE_P3 = HSIZE;
// HTRANS
assign HTRANS_P0 = HTRANS;
assign HTRANS_P1 = HTRANS;
assign HTRANS_P2 = HTRANS;
assign HTRANS_P3 = HTRANS;
// HWDATA
assign HWDATA_P0 = HWDATA;
assign HWDATA_P1 = HWDATA;
assign HWDATA_P2 = HWDATA;
assign HWDATA_P3 = HWDATA;
// HWRITE
assign HWRITE_P0 = HWRITE;
assign HWRITE_P1 = HWRITE;
assign HWRITE_P2 = HWRITE;
assign HWRITE_P3 = HWRITE;
// HREADY
assign HREADY_P0 = HREADY;
assign HREADY_P1 = HREADY;
assign HREADY_P2 = HREADY;
assign HREADY_P3 = HREADY;
// Decoder---------------------------------------
//-----------------------------------------------
AHBlite_Decoder Decoder(
.HADDR (HADDR),
.P0_HSEL (HSEL_P0),
.P1_HSEL (HSEL_P1),
.P2_HSEL (HSEL_P2),
.P3_HSEL (HSEL_P3)
);
// Slave MUX-------------------------------------
//-----------------------------------------------
AHBlite_SlaveMUX SlaveMUX(
// CLOCK & RST
.HCLK (HCLK),
.HRESETn (HRESETn),
.HREADY (HREADY),
//P0
.P0_HSEL (HSEL_P0),
.P0_HREADYOUT (HREADYOUT_P0),
.P0_HRESP (HRESP_P0),
.P0_HRDATA (HRDATA_P0),
//P1
.P1_HSEL (HSEL_P1),
.P1_HREADYOUT (HREADYOUT_P1),
.P1_HRESP (HRESP_P1),
.P1_HRDATA (HRDATA_P1),
//P2
.P2_HSEL (HSEL_P2),
.P2_HREADYOUT (HREADYOUT_P2),
.P2_HRESP (HRESP_P2),
.P2_HRDATA (HRDATA_P2),
//P3
.P3_HSEL (HSEL_P3),
.P3_HREADYOUT (HREADYOUT_P3),
.P3_HRESP (HRESP_P3),
.P3_HRDATA (HRDATA_P3),
.HREADYOUT (HREADY),
.HRESP (HRESP),
.HRDATA (HRDATA)
);
endmodule

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src/SOC/AHBlite_SlaveMUX.v Normal file
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module AHBlite_SlaveMUX (
input HCLK,
input HRESETn,
input HREADY,
//port 0
input P0_HSEL,
input P0_HREADYOUT,
input P0_HRESP,
input [31:0] P0_HRDATA,
//port 1
input P1_HSEL,
input P1_HREADYOUT,
input P1_HRESP,
input [31:0] P1_HRDATA,
//port 2
input P2_HSEL,
input P2_HREADYOUT,
input P2_HRESP,
input [31:0] P2_HRDATA,
//port 3
input P3_HSEL,
input P3_HREADYOUT,
input P3_HRESP,
input [31:0] P3_HRDATA,
//output
output wire HREADYOUT,
output wire HRESP,
output wire [31:0] HRDATA
);
//reg the hsel
reg [3:0] hsel_reg;
always@(posedge HCLK or negedge HRESETn) begin
if(~HRESETn) hsel_reg <= 4'b0000;
else if(HREADY) hsel_reg <= {P0_HSEL,P1_HSEL,P2_HSEL,P3_HSEL};
end
//hready mux
reg hready_mux;
always@(*) begin
case(hsel_reg)
4'b0001 : begin hready_mux = P3_HREADYOUT;end
4'b0010 : begin hready_mux = P2_HREADYOUT;end
4'b0100 : begin hready_mux = P1_HREADYOUT;end
4'b1000 : begin hready_mux = P0_HREADYOUT;end
default : begin hready_mux = 1'b1;end
endcase
end
assign HREADYOUT = hready_mux;
//hresp mux
reg hresp_mux;
always@(*) begin
case(hsel_reg)
4'b0001 : begin hresp_mux = P3_HRESP;end
4'b0010 : begin hresp_mux = P2_HRESP;end
4'b0100 : begin hresp_mux = P1_HRESP;end
4'b1000 : begin hresp_mux = P0_HRESP;end
default : begin hresp_mux = 1'b0;end
endcase
end
assign HRESP = hresp_mux;
//hrdata mux
reg [31:0] hrdata_mux;
always@(*) begin
case(hsel_reg)
4'b0001 : begin hrdata_mux = P3_HRDATA;end
4'b0010 : begin hrdata_mux = P2_HRDATA;end
4'b0100 : begin hrdata_mux = P1_HRDATA;end
4'b1000 : begin hrdata_mux = P0_HRDATA;end
default : begin hrdata_mux = 32'b0;end
endcase
end
assign HRDATA = hrdata_mux;
endmodule

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src/SOC/AHBlite_UART.v Normal file
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module AHBlite_UART(
input wire HCLK,
input wire HRESETn,
input wire HSEL,
input wire [31:0] HADDR,
input wire [1:0] HTRANS,
input wire [2:0] HSIZE,
input wire [3:0] HPROT,
input wire HWRITE,
input wire [31:0] HWDATA,
input wire HREADY,
output wire HREADYOUT,
output reg [31:0] HRDATA,
output wire HRESP,
input wire [7:0] UART_RX,
input wire state,
output wire tx_en,
output wire [7:0] UART_TX
);
assign HRESP = 1'b0;
assign HREADYOUT = 1'b1;
wire read_en;
assign read_en=HSEL&HTRANS[1]&(~HWRITE)&HREADY;
wire write_en;
assign write_en=HSEL&HTRANS[1]&(HWRITE)&HREADY;
reg [3:0] addr_reg;
always@(posedge HCLK or negedge HRESETn) begin
if(~HRESETn) addr_reg <= 4'h0;
else if(read_en || write_en) addr_reg <= HADDR[3:0];
end
reg rd_en_reg;
always@(posedge HCLK or negedge HRESETn) begin
if(~HRESETn) rd_en_reg <= 1'b0;
else if(read_en) rd_en_reg <= 1'b1;
else rd_en_reg <= 1'b0;
end
reg wr_en_reg;
always@(posedge HCLK or negedge HRESETn) begin
if(~HRESETn) wr_en_reg <= 1'b0;
else if(write_en) wr_en_reg <= 1'b1;
else wr_en_reg <= 1'b0;
end
always@(*) begin
if(rd_en_reg) begin
if(addr_reg == 4'h0) HRDATA <= {24'b0,UART_RX};
else if(addr_reg == 4'h4) HRDATA <= {31'b0,state};
else HRDATA <= 32'b0;
end else
HRDATA <= 32'b0;
end
assign tx_en = wr_en_reg ? 1'b1 : 1'b0;
assign UART_TX = wr_en_reg ? HWDATA[7:0] : 8'b0;
endmodule

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src/SOC/AHBlite_WaterLight.v Normal file
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module AHBlite_WaterLight(
input wire HCLK,
input wire HRESETn,
input wire HSEL,
input wire [31:0] HADDR,
input wire [1:0] HTRANS,
input wire [2:0] HSIZE,
input wire [3:0] HPROT,
input wire HWRITE,
input wire [31:0] HWDATA,
input wire HREADY,
output wire HREADYOUT,
output wire [31:0] HRDATA,
output wire HRESP,
output reg [7:0] WaterLight_mode,
output reg [31:0] WaterLight_speed
);
assign HRESP = 1'b0;
assign HREADYOUT = 1'b1;
wire write_en;
assign write_en = HSEL & HTRANS[1] & HWRITE & HREADY;
reg addr_reg;
always@(posedge HCLK or negedge HRESETn) begin
if(~HRESETn) addr_reg <= 1'b0;
else if(write_en) addr_reg <= HADDR[2];
end
reg wr_en_reg;
always@(posedge HCLK or negedge HRESETn) begin
if(~HRESETn) wr_en_reg <= 1'b0;
else if(write_en) wr_en_reg <= 1'b1;
else wr_en_reg <= 1'b0;
end
always@(posedge HCLK) begin
if(~HRESETn) begin
WaterLight_mode <= 8'h00;
WaterLight_speed <= 32'h00000000;
end else if(wr_en_reg && HREADY) begin
if(~addr_reg)
WaterLight_mode <= HWDATA[7:0];
else
WaterLight_speed <= HWDATA;
end
end
assign HRDATA = (addr_reg) ? WaterLight_speed : {24'b0,WaterLight_mode};
endmodule

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src/SOC/Block_RAM.v Normal file
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module Block_RAM #(
parameter ADDR_WIDTH = 14
) (
input clka,
input [ADDR_WIDTH-1:0] addra,
input [ADDR_WIDTH-1:0] addrb,
input [31:0] dina,
input [3:0] wea,
output reg [31:0] doutb
);
(* ram_style="bram32k" *)reg [31:0] mem [(2**ADDR_WIDTH-1):0];
initial begin
$readmemh("../../keil/code.hex",mem);
end
always@(posedge clka) begin
if(wea[0]) mem[addra][7:0] <= dina[7:0];
end
always@(posedge clka) begin
if(wea[1]) mem[addra][15:8] <= dina[15:8];
end
always@(posedge clka) begin
if(wea[2]) mem[addra][23:16] <= dina[23:16];
end
always@(posedge clka) begin
if(wea[3]) mem[addra][31:24] <= dina[31:24];
end
always@(posedge clka) begin
doutb <= mem[addrb];
end
endmodule

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src/SOC/CortexM0_SoC.v Normal file
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module CortexM0_SoC (
input wire clk,
input wire RSTn,
inout wire SWDIO,
input wire SWCLK,
output wire [7:0] LED,
output wire LEDclk,
output wire TXD,
input wire RXD
);
//------------------------------------------------------------------------------
// DEBUG IOBUF
//------------------------------------------------------------------------------
wire SWDO;
wire SWDOEN;
wire SWDI;
assign SWDI = SWDIO;
assign SWDIO = (SWDOEN) ? SWDO : 1'bz;
//------------------------------------------------------------------------------
// Interrupt
//------------------------------------------------------------------------------
wire [31:0] IRQ;
wire interrupt_UART;
/*Connect the IRQ with UART*/
assign IRQ = {31'b0,interrupt_UART};
/***************************/
wire RXEV;
assign RXEV = 1'b0;
//------------------------------------------------------------------------------
// AHB
//------------------------------------------------------------------------------
wire [31:0] HADDR;
wire [ 2:0] HBURST;
wire HMASTLOCK;
wire [ 3:0] HPROT;
wire [ 2:0] HSIZE;
wire [ 1:0] HTRANS;
wire [31:0] HWDATA;
wire HWRITE;
wire [31:0] HRDATA;
wire HRESP;
wire HMASTER;
wire HREADY;
//------------------------------------------------------------------------------
// RESET AND DEBUG
//------------------------------------------------------------------------------
wire SYSRESETREQ;
reg cpuresetn;
always @(posedge clk or negedge RSTn)begin
if (~RSTn) cpuresetn <= 1'b0;
else if (SYSRESETREQ) cpuresetn <= 1'b0;
else cpuresetn <= 1'b1;
end
wire CDBGPWRUPREQ;
reg CDBGPWRUPACK;
always @(posedge clk or negedge RSTn)begin
if (~RSTn) CDBGPWRUPACK <= 1'b0;
else CDBGPWRUPACK <= CDBGPWRUPREQ;
end
//------------------------------------------------------------------------------
// Instantiate Cortex-M0 processor logic level
//------------------------------------------------------------------------------
cortexm0ds_logic u_logic (
// System inputs
.FCLK (clk), //FREE running clock
.SCLK (clk), //system clock
.HCLK (clk), //AHB clock
.DCLK (clk), //Debug clock
.PORESETn (RSTn), //Power on reset
.HRESETn (cpuresetn), //AHB and System reset
.DBGRESETn (RSTn), //Debug Reset
.RSTBYPASS (1'b0), //Reset bypass
.SE (1'b0), // dummy scan enable port for synthesis
// Power management inputs
.SLEEPHOLDREQn (1'b1), // Sleep extension request from PMU
.WICENREQ (1'b0), // WIC enable request from PMU
.CDBGPWRUPACK (CDBGPWRUPACK), // Debug Power Up ACK from PMU
// Power management outputs
.CDBGPWRUPREQ (CDBGPWRUPREQ),
.SYSRESETREQ (SYSRESETREQ),
// System bus
.HADDR (HADDR[31:0]),
.HTRANS (HTRANS[1:0]),
.HSIZE (HSIZE[2:0]),
.HBURST (HBURST[2:0]),
.HPROT (HPROT[3:0]),
.HMASTER (HMASTER),
.HMASTLOCK (HMASTLOCK),
.HWRITE (HWRITE),
.HWDATA (HWDATA[31:0]),
.HRDATA (HRDATA[31:0]),
.HREADY (HREADY),
.HRESP (HRESP),
// Interrupts
.IRQ (IRQ), //Interrupt
.NMI (1'b0), //Watch dog interrupt
.IRQLATENCY (8'h0),
.ECOREVNUM (28'h0),
// Systick
.STCLKEN (1'b0),
.STCALIB (26'h0),
// Debug - JTAG or Serial wire
// Inputs
.nTRST (1'b1),
.SWDITMS (SWDI),
.SWCLKTCK (SWCLK),
.TDI (1'b0),
// Outputs
.SWDO (SWDO),
.SWDOEN (SWDOEN),
.DBGRESTART (1'b0),
// Event communication
.RXEV (RXEV), // Generate event when a DMA operation completed.
.EDBGRQ (1'b0) // multi-core synchronous halt request
);
//------------------------------------------------------------------------------
// AHBlite Interconncet
//------------------------------------------------------------------------------
wire HSEL_P0;
wire [31:0] HADDR_P0;
wire [2:0] HBURST_P0;
wire HMASTLOCK_P0;
wire [3:0] HPROT_P0;
wire [2:0] HSIZE_P0;
wire [1:0] HTRANS_P0;
wire [31:0] HWDATA_P0;
wire HWRITE_P0;
wire HREADY_P0;
wire HREADYOUT_P0;
wire [31:0] HRDATA_P0;
wire HRESP_P0;
wire HSEL_P1;
wire [31:0] HADDR_P1;
wire [2:0] HBURST_P1;
wire HMASTLOCK_P1;
wire [3:0] HPROT_P1;
wire [2:0] HSIZE_P1;
wire [1:0] HTRANS_P1;
wire [31:0] HWDATA_P1;
wire HWRITE_P1;
wire HREADY_P1;
wire HREADYOUT_P1;
wire [31:0] HRDATA_P1;
wire HRESP_P1;
wire HSEL_P2;
wire [31:0] HADDR_P2;
wire [2:0] HBURST_P2;
wire HMASTLOCK_P2;
wire [3:0] HPROT_P2;
wire [2:0] HSIZE_P2;
wire [1:0] HTRANS_P2;
wire [31:0] HWDATA_P2;
wire HWRITE_P2;
wire HREADY_P2;
wire HREADYOUT_P2;
wire [31:0] HRDATA_P2;
wire HRESP_P2;
wire HSEL_P3;
wire [31:0] HADDR_P3;
wire [2:0] HBURST_P3;
wire HMASTLOCK_P3;
wire [3:0] HPROT_P3;
wire [2:0] HSIZE_P3;
wire [1:0] HTRANS_P3;
wire [31:0] HWDATA_P3;
wire HWRITE_P3;
wire HREADY_P3;
wire HREADYOUT_P3;
wire [31:0] HRDATA_P3;
wire HRESP_P3;
AHBlite_Interconnect Interconncet(
.HCLK (clk),
.HRESETn (cpuresetn),
// CORE SIDE
.HADDR (HADDR),
.HTRANS (HTRANS),
.HSIZE (HSIZE),
.HBURST (HBURST),
.HPROT (HPROT),
.HMASTLOCK (HMASTLOCK),
.HWRITE (HWRITE),
.HWDATA (HWDATA),
.HRDATA (HRDATA),
.HREADY (HREADY),
.HRESP (HRESP),
// P0
.HSEL_P0 (HSEL_P0),
.HADDR_P0 (HADDR_P0),
.HBURST_P0 (HBURST_P0),
.HMASTLOCK_P0 (HMASTLOCK_P0),
.HPROT_P0 (HPROT_P0),
.HSIZE_P0 (HSIZE_P0),
.HTRANS_P0 (HTRANS_P0),
.HWDATA_P0 (HWDATA_P0),
.HWRITE_P0 (HWRITE_P0),
.HREADY_P0 (HREADY_P0),
.HREADYOUT_P0 (HREADYOUT_P0),
.HRDATA_P0 (HRDATA_P0),
.HRESP_P0 (HRESP_P0),
// P1
.HSEL_P1 (HSEL_P1),
.HADDR_P1 (HADDR_P1),
.HBURST_P1 (HBURST_P1),
.HMASTLOCK_P1 (HMASTLOCK_P1),
.HPROT_P1 (HPROT_P1),
.HSIZE_P1 (HSIZE_P1),
.HTRANS_P1 (HTRANS_P1),
.HWDATA_P1 (HWDATA_P1),
.HWRITE_P1 (HWRITE_P1),
.HREADY_P1 (HREADY_P1),
.HREADYOUT_P1 (HREADYOUT_P1),
.HRDATA_P1 (HRDATA_P1),
.HRESP_P1 (HRESP_P1),
// P2
.HSEL_P2 (HSEL_P2),
.HADDR_P2 (HADDR_P2),
.HBURST_P2 (HBURST_P2),
.HMASTLOCK_P2 (HMASTLOCK_P2),
.HPROT_P2 (HPROT_P2),
.HSIZE_P2 (HSIZE_P2),
.HTRANS_P2 (HTRANS_P2),
.HWDATA_P2 (HWDATA_P2),
.HWRITE_P2 (HWRITE_P2),
.HREADY_P2 (HREADY_P2),
.HREADYOUT_P2 (HREADYOUT_P2),
.HRDATA_P2 (HRDATA_P2),
.HRESP_P2 (HRESP_P2),
// P3
.HSEL_P3 (HSEL_P3),
.HADDR_P3 (HADDR_P3),
.HBURST_P3 (HBURST_P3),
.HMASTLOCK_P3 (HMASTLOCK_P3),
.HPROT_P3 (HPROT_P3),
.HSIZE_P3 (HSIZE_P3),
.HTRANS_P3 (HTRANS_P3),
.HWDATA_P3 (HWDATA_P3),
.HWRITE_P3 (HWRITE_P3),
.HREADY_P3 (HREADY_P3),
.HREADYOUT_P3 (HREADYOUT_P3),
.HRDATA_P3 (HRDATA_P3),
.HRESP_P3 (HRESP_P3)
);
//------------------------------------------------------------------------------
// AHB RAMCODE
//------------------------------------------------------------------------------
wire [31:0] RAMCODE_RDATA,RAMCODE_WDATA;
wire [13:0] RAMCODE_WADDR;
wire [13:0] RAMCODE_RADDR;
wire [3:0] RAMCODE_WRITE;
AHBlite_Block_RAM #(.ADDR_WIDTH(13)) RAMCODE_Interface(
/* Connect to Interconnect Port 0 */
.HCLK (clk),
.HRESETn (cpuresetn),
.HSEL (HSEL_P0),
.HADDR (HADDR_P0),
.HPROT (HPROT_P0),
.HSIZE (HSIZE_P0),
.HTRANS (HTRANS_P0),
.HWDATA (HWDATA_P0),
.HWRITE (HWRITE_P0),
.HRDATA (HRDATA_P0),
.HREADY (HREADY_P0),
.HREADYOUT (HREADYOUT_P0),
.HRESP (HRESP_P0),
.BRAM_WRADDR (RAMCODE_WADDR),
.BRAM_RDADDR (RAMCODE_RADDR),
.BRAM_RDATA (RAMCODE_RDATA),
.BRAM_WDATA (RAMCODE_WDATA),
.BRAM_WRITE (RAMCODE_WRITE)
/**********************************/
);
//------------------------------------------------------------------------------
// AHB WaterLight
//------------------------------------------------------------------------------
wire [7:0] WaterLight_mode;
wire [31:0] WaterLight_speed;
AHBlite_WaterLight WaterLight_Interface(
/* Connect to Interconnect Port 2 */
.HCLK (clk),
.HRESETn (cpuresetn),
.HSEL (HSEL_P2),
.HADDR (HADDR_P2),
.HPROT (HPROT_P2),
.HSIZE (HSIZE_P2),
.HTRANS (HTRANS_P2),
.HWDATA (HWDATA_P2),
.HWRITE (HWRITE_P2),
.HRDATA (HRDATA_P2),
.HREADY (HREADY_P2),
.HREADYOUT (HREADYOUT_P2),
.HRESP (HRESP_P2),
.WaterLight_mode (WaterLight_mode),
.WaterLight_speed (WaterLight_speed)
/**********************************/
);
//------------------------------------------------------------------------------
// AHB RAMDATA
//------------------------------------------------------------------------------
wire [31:0] RAMDATA_RDATA;
wire [31:0] RAMDATA_WDATA;
wire [13:0] RAMDATA_WADDR;
wire [13:0] RAMDATA_RADDR;
wire [3:0] RAMDATA_WRITE;
AHBlite_Block_RAM RAMDATA_Interface(
/* Connect to Interconnect Port 1 */
.HCLK (clk),
.HRESETn (cpuresetn),
.HSEL (HSEL_P1),
.HADDR (HADDR_P1),
.HPROT (HPROT_P1),
.HSIZE (HSIZE_P1),
.HTRANS (HTRANS_P1),
.HWDATA (HWDATA_P1),
.HWRITE (HWRITE_P1),
.HRDATA (HRDATA_P1),
.HREADY (HREADY_P1),
.HREADYOUT (HREADYOUT_P1),
.HRESP (HRESP_P1),
.BRAM_WRADDR (RAMDATA_WADDR),
.BRAM_RDADDR (RAMDATA_RADDR),
.BRAM_WDATA (RAMDATA_WDATA),
.BRAM_RDATA (RAMDATA_RDATA),
.BRAM_WRITE (RAMDATA_WRITE)
/**********************************/
);
//------------------------------------------------------------------------------
// AHB UART
//------------------------------------------------------------------------------
wire state;
wire [7:0] UART_RX_data;
wire [7:0] UART_TX_data;
wire tx_en;
AHBlite_UART UART_Interface(
.HCLK (clk),
.HRESETn (cpuresetn),
.HSEL (HSEL_P3),
.HADDR (HADDR_P3),
.HPROT (HPROT_P3),
.HSIZE (HSIZE_P3),
.HTRANS (HTRANS_P3),
.HWDATA (HWDATA_P3),
.HWRITE (HWRITE_P3),
.HRDATA (HRDATA_P3),
.HREADY (HREADY_P3),
.HREADYOUT (HREADYOUT_P3),
.HRESP (HRESP_P3),
.UART_RX (UART_RX_data),
.state (state),
.tx_en (tx_en),
.UART_TX (UART_TX_data)
);
//------------------------------------------------------------------------------
// RAM
//------------------------------------------------------------------------------
Block_RAM #(.ADDR_WIDTH(13)) RAM_CODE(
.clka (clk),
.addra (RAMCODE_WADDR),
.addrb (RAMCODE_RADDR),
.dina (RAMCODE_WDATA),
.doutb (RAMCODE_RDATA),
.wea (RAMCODE_WRITE)
);
Block_RAM #(.ADDR_WIDTH(13)) RAM_DATA(
.clka (clk),
.addra (RAMDATA_WADDR),
.addrb (RAMDATA_RADDR),
.dina (RAMDATA_WDATA),
.doutb (RAMDATA_RDATA),
.wea (RAMDATA_WRITE)
);
//------------------------------------------------------------------------------
// WaterLight
//------------------------------------------------------------------------------
WaterLight WaterLight(
.WaterLight_mode(WaterLight_mode),
.WaterLight_speed(WaterLight_speed),
.clk(clk),
.RSTn(cpuresetn),
.LED(LED),
.LEDclk(LEDclk)
);
//------------------------------------------------------------------------------
// UART
//------------------------------------------------------------------------------
wire clk_uart;
wire bps_en;
wire bps_en_rx,bps_en_tx;
assign bps_en = bps_en_rx | bps_en_tx;
clkuart_pwm clkuart_pwm(
.clk(clk),
.RSTn(cpuresetn),
.clk_uart(clk_uart),
.bps_en(bps_en)
);
UART_RX UART_RX(
.clk(clk),
.clk_uart(clk_uart),
.RSTn(cpuresetn),
.RXD(RXD),
.data(UART_RX_data),
.interrupt(interrupt_UART),
.bps_en(bps_en_rx)
);
UART_TX UART_TX(
.clk(clk),
.clk_uart(clk_uart),
.RSTn(cpuresetn),
.data(UART_TX_data),
.tx_en(tx_en),
.TXD(TXD),
.state(state),
.bps_en(bps_en_tx)
);
endmodule

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//it is just a normal FIFO
module FIFO(
input clock,
input sclr,
input rdreq, wrreq,
output reg full, empty,
input [7 : 0] data,
output [7 : 0] q
);
reg [7 : 0] mem [15 : 0];
reg [3 : 0] wp, rp;
reg w_flag, r_flag;
initial
begin
wp=0;
w_flag=0;
rp=0;
r_flag=0;
end
always @(posedge clock) begin
if (~sclr) begin
wp <= 0;
w_flag <= 0;
end else if(!full && wrreq) begin
wp<= (wp==16-1) ? 0 : wp+1;
w_flag <= (wp==16-1) ? ~w_flag : w_flag;
end
end
always @(posedge clock) begin
if(wrreq && !full)begin
mem[wp] <= data;
end
end
always @(posedge clock) begin
if (~sclr) begin
rp<=0;
r_flag <= 0;
end else if(!empty && rdreq) begin
rp<= (rp==16-1) ? 0 : rp+1;
r_flag <= (rp==16-1) ? ~r_flag : r_flag;
end
end
assign q = mem[rp];
always @(*) begin
if(wp==rp)begin
if(r_flag==w_flag)begin
full <= 0;
empty <= 1;
end else begin
full <= 1;
empty <= 0;
end
end else begin
full <= 0;
empty <= 0;
end
end
endmodule

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module UART_RX(
input clk,
input clk_uart,
input RSTn,
input RXD,
output reg [7:0] data,
output wire interrupt,
output wire bps_en
);
//shift register
reg [7:0] shift_reg;
always@(posedge clk) begin
if(~RSTn) shift_reg <= 8'hff;
else shift_reg <= {RXD,shift_reg[7:1]};
end
wire re_start;
assign re_start = (shift_reg == 8'h0f) ? 1'b1 : 1'b0;
// recive counter
reg counter_en;
reg [3:0] counter;
always@(posedge clk or negedge RSTn) begin
if(~RSTn) counter_en <= 1'b0;
else if(re_start&&(~counter_en)) counter_en <= 1'b1;
else if(counter == 4'h9) counter_en <= 1'b0;
end
always@(posedge clk or negedge RSTn) begin
if(~RSTn) counter <= 4'h0;
else if(counter_en) begin
if(clk_uart) counter <= counter + 1'b1;
else if(counter == 4'h9) counter <= 4'h0;
end
end
assign bps_en = counter_en;
// RXD re
always@(posedge clk or negedge RSTn) begin
if(~RSTn) data <= 8'h00;
else if(counter_en) begin
if(clk_uart && (counter <= 4'h8)) data[counter-1] <= RXD;
end
end
//interrupt
assign interrupt = (counter == 4'h9) ? 1'b1 : 1'b0;
endmodule

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module UART_TX(
input clk,
input clk_uart,
input RSTn,
input [7:0] data,
input tx_en,
output reg TXD,
output wire state,
output wire bps_en
);
//FIFO 8bit-16depth
wire FIFOrd_en;
wire FIFOwr_en;
wire [7:0] FIFOdata;
wire FIFOempty;
wire FIFOfull;
FIFO FIFO(
.clock(clk),
.sclr(RSTn),
.rdreq(FIFOrd_en),
.wrreq(FIFOwr_en),
.full(FIFOfull),
.empty(FIFOempty),
.data(data),
.q(FIFOdata)
);
//FIFO write control
assign FIFOwr_en = (~FIFOfull) & tx_en;
assign state = FIFOfull;
//UART TX
reg counter_en;
reg [3:0] counter;
wire trans_finish;
assign trans_finish = (counter == 4'hb);
wire trans_start;
assign trans_start = (~FIFOempty) & (~counter_en);
always@(posedge clk or negedge RSTn) begin
if(~RSTn) counter_en <= 1'b0;
else if(trans_start) counter_en <= 1'b1;
else if(trans_finish) counter_en <= 1'b0;
end
always@(posedge clk or negedge RSTn) begin
if(~RSTn) counter <= 4'h0;
else if(counter_en) begin
if(clk_uart) counter <= counter + 1'b1;
else if(trans_finish) counter <= 4'h0;
end
end
assign bps_en = counter_en;
wire [9:0] data_formed;
assign data_formed = {1'b1,FIFOdata,1'b0};
always@(posedge clk or negedge RSTn) begin
if(~RSTn) TXD <= 1'b1;
else if(counter_en) begin
if(clk_uart && (counter <= 4'h9)) TXD <= data_formed[counter];
end else TXD <= 1'b1;
end
//FIFO read control
assign FIFOrd_en = (~FIFOempty) & trans_finish;
endmodule

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module WaterLight(
input [7:0] WaterLight_mode,
input [31:0] WaterLight_speed,
input clk,
input RSTn,
output reg [7:0] LED,
output wire LEDclk
);
//------------------------------------------------------
// PWM
//------------------------------------------------------
reg [31:0] pwm_cnt;
always@(posedge clk or negedge RSTn) begin
if(~RSTn) pwm_cnt <= 32'b0;
else if(pwm_cnt == WaterLight_speed) pwm_cnt <= 32'b0;
else pwm_cnt <= pwm_cnt + 1'b1;
end
reg light_clk;
always@(posedge clk or negedge RSTn) begin
if(~RSTn) light_clk <= 1'b0;
else if(pwm_cnt == WaterLight_speed) light_clk <= ~light_clk;
end
assign LEDclk = light_clk;
//------------------------------------------------------
// LEFT MODE
//------------------------------------------------------
reg [7:0] mode1;
always@(posedge light_clk or negedge RSTn) begin
if(~RSTn) mode1 <= 8'h01;
else begin
case(mode1)
8'h01 : mode1 <= 8'h02;
8'h02 : mode1 <= 8'h04;
8'h04 : mode1 <= 8'h08;
8'h08 : mode1 <= 8'h10;
8'h10 : mode1 <= 8'h20;
8'h20 : mode1 <= 8'h40;
8'h40 : mode1 <= 8'h80;
default : mode1 <= 8'h01;
endcase
end
end
//------------------------------------------------------
// RIGHT MODE
//------------------------------------------------------
reg [7:0] mode2;
always@(posedge light_clk or negedge RSTn) begin
if(~RSTn) mode2 <= 8'h80;
else begin
case(mode2)
8'h80 : mode2 <= 8'h40;
8'h40 : mode2 <= 8'h20;
8'h20 : mode2 <= 8'h10;
8'h10 : mode2 <= 8'h08;
8'h08 : mode2 <= 8'h04;
8'h04 : mode2 <= 8'h02;
8'h02 : mode2 <= 8'h01;
default : mode2 <= 8'h80;
endcase
end
end
//------------------------------------------------------
// FLASH MODE
//------------------------------------------------------
wire [7:0] mode3;
assign mode3 = (light_clk == 1'b0) ? 8'h00 : 8'hff;
//------------------------------------------------------
// OUTPUT MUX
//------------------------------------------------------
always@(*) begin
case(WaterLight_mode)
8'h01 : begin LED = mode1;end
8'h02 : begin LED = mode2;end
8'h03 : begin LED = mode3;end
default : begin LED = 8'h00;end
endcase
end
endmodule

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module clkuart_pwm
#( parameter BPS_PARA = 434 )
(
input bps_en,
input clk,
input RSTn,
output reg clk_uart
);
reg [12:0] cnt = 0;
always @ (posedge clk or negedge RSTn) begin
if(~RSTn) cnt <= 13'b0;
else if((cnt >= BPS_PARA-1)||(!bps_en)) cnt <= 13'b0;
else cnt <= cnt + 1'b1;
end
always @ (posedge clk or negedge RSTn) begin
if(~RSTn) clk_uart <= 1'b0;
else if(cnt == (BPS_PARA>>1)) clk_uart <= 1'b1;
else clk_uart <= 1'b0;
end
endmodule

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src/SOC/cortexm0ds_logic.v Normal file
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0
src/Mul.v → src/demodulation/Mul.v
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0
src/demodulation.v → src/demodulation/demodulation.v
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