mirror of
https://github.com/JefferyLi0903/MMC.git
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更新了部分说明文档
This commit is contained in:
JefferyLi0903
parent
c86b446c69
commit
7b57f3fee0
80
README.md
80
README.md
@ -1,77 +1,3 @@
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# README
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## RSSI 扫频算法设计
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### RSSI分布描述
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<img src="docs/pic/image.png"/>
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该图为频率范围$f\in[87MHz,108MHz]$下的RSSI的对数坐标分布$RSSI_{log}=10\times\log{RSSI}$。
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此设计的目的是**利用编写的接口函数，筛选出图中标出的频点**。
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### 需求描述
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#### 输入
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##### RSSIType
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上图中对应的RSSI数据存放在下述定义的数据结构中：
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```c
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typedef struct{
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int index; //存放每个采样点的索引值
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int RSSI; //存放RSSI的值
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}RSSIType;
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```
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❤**注意此处的RSSI不是图中所示的对数形式，请不要对RSSI的值进行Log运算（尽量不要进行任何运算，因为数据量大，延迟很高）。**
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构成结构数组定义如下：
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```C
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#define NUM 1060
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#define STEP 0.02
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RSSIType rssilist[NUM];
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```
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不推荐更改`NUM`（数组长度设定为1060）和`STEP`（扫频步长设定为0.02MHz）的数值。由于不可名状的BUG，在第一次运行扫频函数时，`rssilist[0]`的RSSI值为0。因此可以使用的数据为`rssilist[1]`~`rssilist[1050]`共1050个RSSIType数据结构。（由于C的浮点数特性，导致频率为108时仍然可以运行扫频程序，因此会比期望的数量多一个）
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##### 门限值Thresh
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`RSSI>Thresh`时对应的频率才可能成为频点，**但若该门限过低，导致输出的频点多于16个时，仅输出最高的16个。**
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#### 输出
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观察数据规律，输出RSSI值最高的频点（**精度要求为0.1MHz**），将所有频点的频率**从小到大**存放在以下数据结构中。
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```C
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typedef struct{
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unsigned int channel_no; //存放频道号，从1开始递增编号
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float freq; //存放频点频率
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unsigned int INT; //存放整数部分
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unsigned int FRAC; //存放小数部分
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}ChannelControlType;
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```
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其中`INT`和`FRAC`与频率的转换公式如下：
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```C
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int INT=floor(freq/3);
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int FRAC=(freq/3-INT)*3000;
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```
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**可以使用提供的数据在x86平台进行测试，测试完毕后需要按照注释的位置插入相应的代码，并Build确认无报错**。
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需要插入的部分包括：
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`code_def.h`第73行声明函数名；
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`code_def.c`第13行创建ChannelControlType数组（含有16个元素）全局变量；
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`code_def.c`第239行调用函数；
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`code_def.c`第246行完成函数构建。
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# README
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本项目为基于Cortex M0软核，基于安路FPGA硬件平台搭建的一个收音机SOC系统。
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File diff suppressed because it is too large
Load Diff
BIN
keil/MMC.axf
BIN
keil/MMC.axf
Binary file not shown.
@ -22,7 +22,7 @@ Dialog DLL: TARMCM1.DLL V1.14.4.0
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<h2>Project:</h2>
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D:\Documents\MMC\keil\MMC.uvprojx
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Project File Date: 06/29/2022
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Project File Date: 06/30/2022
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<h2>Output:</h2>
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*** Using Compiler 'V5.06 update 7 (build 960)', folder: 'D:\Keil_v5\ARM\ARMCC\Bin'
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@ -34,17 +34,20 @@ compiling auxiliary.c...
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int isNegative = 0;
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..\src\auxiliary.c: 1 warning, 0 errors
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compiling channelSelection_control.c...
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..\src\channelSelection_control.c(68): warning: #177-D: variable "MSI_SPI_Data" was declared but never referenced
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unsigned int MSI_SPI_Data= 0;
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..\src\channelSelection_control.c: 1 warning, 0 errors
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compiling code_def.c...
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..\src\code_def.c(228): warning: #177-D: variable "j" was declared but never referenced
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..\src\code_def.c(230): warning: #177-D: variable "j" was declared but never referenced
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int j;
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..\src\code_def.c: 1 warning, 0 errors
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linking...
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.\MMC.axf: Warning: L6305W: Image does not have an entry point. (Not specified or not set due to multiple choices.)
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Program Size: Code=12384 RO-data=240 RW-data=40 ZI-data=10920
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Program Size: Code=10284 RO-data=280 RW-data=40 ZI-data=11096
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Finished: 0 information, 1 warning and 0 error messages.
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After Build - User command #1: fromelf -cvf .\MMC.axf --vhx --32x1 -o MMC.hex
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After Build - User command #2: fromelf -cvf .\MMC.axf -o MMC.txt
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".\MMC.axf" - 0 Error(s), 3 Warning(s).
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".\MMC.axf" - 0 Error(s), 4 Warning(s).
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<h2>Software Packages used:</h2>
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@ -57,7 +60,7 @@ Package Vendor: Keil
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C:\Users\JefferyLi\AppData\Local\Arm\Packs\Keil\V2M-MPS2_CMx_BSP\1.8.0\Device\CMSDK_CM0\Include
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<h2>Collection of Component Files used:</h2>
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Build Time Elapsed: 00:00:01
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Build Time Elapsed: 00:00:00
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</pre>
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</body>
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</html>
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2135
keil/MMC.hex
2135
keil/MMC.hex
File diff suppressed because it is too large
Load Diff
419
keil/MMC.htm
419
keil/MMC.htm
@ -3,11 +3,11 @@
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<title>Static Call Graph - [.\MMC.axf]</title></head>
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<body><HR>
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<H1>Static Call Graph for image .\MMC.axf</H1><HR>
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<BR><P>#<CALLGRAPH># ARM Linker, 5060960: Last Updated: Wed Jun 29 12:49:31 2022
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<BR><P>#<CALLGRAPH># ARM Linker, 5060960: Last Updated: Tue Jul 19 23:11:24 2022
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<BR><P>
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<H3>Maximum Stack Usage = 200 bytes + Unknown(Functions without stacksize, Cycles, Untraceable Function Pointers)</H3><H3>
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<H3>Maximum Stack Usage = 208 bytes + Unknown(Functions without stacksize, Cycles, Untraceable Function Pointers)</H3><H3>
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Call chain for Maximum Stack Depth:</H3>
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RSSI_Scan_Done ⇒ RSSIScanHandler ⇒ RSSIScanscreen ⇒ floor ⇒ __aeabi_cdrcmple
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RSSI_Scan_Done ⇒ RSSIScanHandler ⇒ RSSIScanscreen ⇒ __aeabi_dmul
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<P>
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<H3>
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Functions with no stack information
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@ -66,9 +66,9 @@ Global Symbols
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<BR><BR>[Calls]<UL><LI><a href="#[1f]">>></a> __rt_entry
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</UL>
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<P><STRONG><a name="[83]"></a>__scatterload_rt2_thumb_only</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, __scatter.o(!!!scatter), UNUSED)
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<P><STRONG><a name="[87]"></a>__scatterload_rt2_thumb_only</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, __scatter.o(!!!scatter), UNUSED)
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<P><STRONG><a name="[84]"></a>__scatterload_null</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, __scatter.o(!!!scatter), UNUSED)
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<P><STRONG><a name="[88]"></a>__scatterload_null</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, __scatter.o(!!!scatter), UNUSED)
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<P><STRONG><a name="[21]"></a>__scatterload_copy</STRONG> (Thumb, 26 bytes, Stack size unknown bytes, __scatter_copy.o(!!handler_copy), UNUSED)
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<BR><BR>[Calls]<UL><LI><a href="#[21]">>></a> __scatterload_copy
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@ -76,80 +76,80 @@ Global Symbols
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<BR>[Called By]<UL><LI><a href="#[21]">>></a> __scatterload_copy
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</UL>
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<P><STRONG><a name="[85]"></a>__scatterload_zeroinit</STRONG> (Thumb, 28 bytes, Stack size unknown bytes, __scatter_zi.o(!!handler_zi), UNUSED)
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<P><STRONG><a name="[89]"></a>__scatterload_zeroinit</STRONG> (Thumb, 28 bytes, Stack size unknown bytes, __scatter_zi.o(!!handler_zi), UNUSED)
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<P><STRONG><a name="[25]"></a>__rt_lib_init</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit.o(.ARM.Collect$$libinit$$00000000))
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<BR><BR>[Called By]<UL><LI><a href="#[24]">>></a> __rt_entry_li
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</UL>
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<P><STRONG><a name="[86]"></a>__rt_lib_init_alloca_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000002E))
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<P><STRONG><a name="[8a]"></a>__rt_lib_init_alloca_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000002E))
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<P><STRONG><a name="[87]"></a>__rt_lib_init_argv_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000002C))
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<P><STRONG><a name="[8b]"></a>__rt_lib_init_argv_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000002C))
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<P><STRONG><a name="[88]"></a>__rt_lib_init_atexit_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000001B))
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<P><STRONG><a name="[8c]"></a>__rt_lib_init_atexit_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000001B))
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<P><STRONG><a name="[89]"></a>__rt_lib_init_clock_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000021))
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<P><STRONG><a name="[8d]"></a>__rt_lib_init_clock_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000021))
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<P><STRONG><a name="[8a]"></a>__rt_lib_init_cpp_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000032))
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<P><STRONG><a name="[8e]"></a>__rt_lib_init_cpp_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000032))
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<P><STRONG><a name="[8b]"></a>__rt_lib_init_exceptions_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000030))
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<P><STRONG><a name="[8f]"></a>__rt_lib_init_exceptions_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000030))
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<P><STRONG><a name="[8c]"></a>__rt_lib_init_fp_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000002))
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<P><STRONG><a name="[90]"></a>__rt_lib_init_fp_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000002))
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<P><STRONG><a name="[8d]"></a>__rt_lib_init_fp_trap_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000001F))
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<P><STRONG><a name="[91]"></a>__rt_lib_init_fp_trap_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000001F))
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<P><STRONG><a name="[8e]"></a>__rt_lib_init_getenv_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000023))
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<P><STRONG><a name="[92]"></a>__rt_lib_init_getenv_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000023))
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<P><STRONG><a name="[8f]"></a>__rt_lib_init_heap_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000000A))
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<P><STRONG><a name="[93]"></a>__rt_lib_init_heap_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000000A))
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<P><STRONG><a name="[90]"></a>__rt_lib_init_lc_collate_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000011))
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<P><STRONG><a name="[94]"></a>__rt_lib_init_lc_collate_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000011))
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<P><STRONG><a name="[91]"></a>__rt_lib_init_lc_ctype_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000013))
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<P><STRONG><a name="[95]"></a>__rt_lib_init_lc_ctype_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000013))
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<P><STRONG><a name="[92]"></a>__rt_lib_init_lc_monetary_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000015))
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<P><STRONG><a name="[96]"></a>__rt_lib_init_lc_monetary_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000015))
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<P><STRONG><a name="[93]"></a>__rt_lib_init_lc_numeric_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000017))
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<P><STRONG><a name="[97]"></a>__rt_lib_init_lc_numeric_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000017))
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<P><STRONG><a name="[94]"></a>__rt_lib_init_lc_time_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000019))
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<P><STRONG><a name="[98]"></a>__rt_lib_init_lc_time_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000019))
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<P><STRONG><a name="[95]"></a>__rt_lib_init_preinit_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000004))
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<P><STRONG><a name="[99]"></a>__rt_lib_init_preinit_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000004))
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<P><STRONG><a name="[96]"></a>__rt_lib_init_rand_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000000E))
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<P><STRONG><a name="[9a]"></a>__rt_lib_init_rand_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000000E))
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<P><STRONG><a name="[97]"></a>__rt_lib_init_return</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000033))
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<P><STRONG><a name="[9b]"></a>__rt_lib_init_return</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000033))
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<P><STRONG><a name="[98]"></a>__rt_lib_init_signal_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000001D))
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<P><STRONG><a name="[9c]"></a>__rt_lib_init_signal_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000001D))
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<P><STRONG><a name="[99]"></a>__rt_lib_init_stdio_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000025))
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<P><STRONG><a name="[9d]"></a>__rt_lib_init_stdio_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000025))
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<P><STRONG><a name="[9a]"></a>__rt_lib_init_user_alloc_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000000C))
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<P><STRONG><a name="[9e]"></a>__rt_lib_init_user_alloc_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000000C))
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<P><STRONG><a name="[2a]"></a>__rt_lib_shutdown</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libshutdown.o(.ARM.Collect$$libshutdown$$00000000))
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<BR><BR>[Called By]<UL><LI><a href="#[29]">>></a> __rt_exit_ls
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</UL>
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<P><STRONG><a name="[9b]"></a>__rt_lib_shutdown_cpp_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$00000004))
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<P><STRONG><a name="[9f]"></a>__rt_lib_shutdown_cpp_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$00000004))
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<P><STRONG><a name="[9c]"></a>__rt_lib_shutdown_fini_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$00000002))
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<P><STRONG><a name="[a0]"></a>__rt_lib_shutdown_fini_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$00000002))
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<P><STRONG><a name="[9d]"></a>__rt_lib_shutdown_fp_trap_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$00000009))
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<P><STRONG><a name="[a1]"></a>__rt_lib_shutdown_fp_trap_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$00000009))
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<P><STRONG><a name="[9e]"></a>__rt_lib_shutdown_heap_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$00000011))
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<P><STRONG><a name="[a2]"></a>__rt_lib_shutdown_heap_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$00000011))
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<P><STRONG><a name="[9f]"></a>__rt_lib_shutdown_return</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$00000012))
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<P><STRONG><a name="[a3]"></a>__rt_lib_shutdown_return</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$00000012))
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<P><STRONG><a name="[a0]"></a>__rt_lib_shutdown_signal_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$0000000C))
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<P><STRONG><a name="[a4]"></a>__rt_lib_shutdown_signal_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$0000000C))
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<P><STRONG><a name="[a1]"></a>__rt_lib_shutdown_stdio_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$00000006))
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||||
<P><STRONG><a name="[a5]"></a>__rt_lib_shutdown_stdio_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$00000006))
|
||||
|
||||
<P><STRONG><a name="[a2]"></a>__rt_lib_shutdown_user_alloc_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$0000000E))
|
||||
<P><STRONG><a name="[a6]"></a>__rt_lib_shutdown_user_alloc_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$0000000E))
|
||||
|
||||
<P><STRONG><a name="[1f]"></a>__rt_entry</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, __rtentry.o(.ARM.Collect$$rtentry$$00000000))
|
||||
<BR><BR>[Called By]<UL><LI><a href="#[1c]">>></a> __main
|
||||
<LI><a href="#[20]">>></a> __scatterload_rt2
|
||||
</UL>
|
||||
|
||||
<P><STRONG><a name="[a3]"></a>__rt_entry_presh_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, __rtentry2.o(.ARM.Collect$$rtentry$$00000002))
|
||||
<P><STRONG><a name="[a7]"></a>__rt_entry_presh_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, __rtentry2.o(.ARM.Collect$$rtentry$$00000002))
|
||||
|
||||
<P><STRONG><a name="[22]"></a>__rt_entry_sh</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, __rtentry4.o(.ARM.Collect$$rtentry$$00000004))
|
||||
<BR><BR>[Stack]<UL><LI>Max Depth = 8 + Unknown Stack Size
|
||||
@ -162,17 +162,17 @@ Global Symbols
|
||||
<BR><BR>[Calls]<UL><LI><a href="#[25]">>></a> __rt_lib_init
|
||||
</UL>
|
||||
|
||||
<P><STRONG><a name="[a4]"></a>__rt_entry_postsh_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, __rtentry2.o(.ARM.Collect$$rtentry$$00000009))
|
||||
<P><STRONG><a name="[a8]"></a>__rt_entry_postsh_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, __rtentry2.o(.ARM.Collect$$rtentry$$00000009))
|
||||
|
||||
<P><STRONG><a name="[26]"></a>__rt_entry_main</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, __rtentry2.o(.ARM.Collect$$rtentry$$0000000D))
|
||||
<BR><BR>[Stack]<UL><LI>Max Depth = 8 + Unknown Stack Size
|
||||
<LI>Call Chain = __rt_entry_main ⇒ exit
|
||||
<BR><BR>[Stack]<UL><LI>Max Depth = 48 + Unknown Stack Size
|
||||
<LI>Call Chain = __rt_entry_main ⇒ main ⇒ initialize
|
||||
</UL>
|
||||
<BR>[Calls]<UL><LI><a href="#[28]">>></a> exit
|
||||
<LI><a href="#[27]">>></a> main
|
||||
</UL>
|
||||
|
||||
<P><STRONG><a name="[a5]"></a>__rt_entry_postli_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, __rtentry2.o(.ARM.Collect$$rtentry$$0000000C))
|
||||
<P><STRONG><a name="[a9]"></a>__rt_entry_postli_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, __rtentry2.o(.ARM.Collect$$rtentry$$0000000C))
|
||||
|
||||
<P><STRONG><a name="[53]"></a>__rt_exit</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, rtexit.o(.ARM.Collect$$rtexit$$00000000))
|
||||
<BR><BR>[Called By]<UL><LI><a href="#[28]">>></a> exit
|
||||
@ -182,12 +182,18 @@ Global Symbols
|
||||
<BR><BR>[Calls]<UL><LI><a href="#[2a]">>></a> __rt_lib_shutdown
|
||||
</UL>
|
||||
|
||||
<P><STRONG><a name="[a6]"></a>__rt_exit_prels_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, rtexit2.o(.ARM.Collect$$rtexit$$00000002))
|
||||
<P><STRONG><a name="[aa]"></a>__rt_exit_prels_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, rtexit2.o(.ARM.Collect$$rtexit$$00000002))
|
||||
|
||||
<P><STRONG><a name="[2b]"></a>__rt_exit_exit</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, rtexit2.o(.ARM.Collect$$rtexit$$00000004))
|
||||
<BR><BR>[Calls]<UL><LI><a href="#[2c]">>></a> _sys_exit
|
||||
</UL>
|
||||
|
||||
<P><STRONG><a name="[7c]"></a>__aeabi_memcpy4</STRONG> (Thumb, 56 bytes, Stack size 0 bytes, rt_memcpy.o(.emb_text))
|
||||
<BR><BR>[Called By]<UL><LI><a href="#[7b]">>></a> initialize
|
||||
</UL>
|
||||
|
||||
<P><STRONG><a name="[ab]"></a>__aeabi_memcpy8</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, rt_memcpy.o(.emb_text), UNUSED)
|
||||
|
||||
<P><STRONG><a name="[1b]"></a>Reset_Handler</STRONG> (Thumb, 10 bytes, Stack size 0 bytes, startup_cmsdk_cm0.o(.text))
|
||||
<BR><BR>[Calls]<UL><LI><a href="#[1c]">>></a> __main
|
||||
</UL>
|
||||
@ -207,14 +213,14 @@ Global Symbols
|
||||
<BR>[Address Reference Count : 1]<UL><LI> startup_cmsdk_cm0.o(RESET)
|
||||
</UL>
|
||||
<P><STRONG><a name="[6]"></a>UART_Handler</STRONG> (Thumb, 8 bytes, Stack size 0 bytes, startup_cmsdk_cm0.o(.text))
|
||||
<BR><BR>[Stack]<UL><LI>Max Depth = 120<LI>Call Chain = UART_Handler ⇒ UARTHandle ⇒ ChannelSelection_control ⇒ singleFrequencyRSSI ⇒ floor ⇒ __aeabi_cdrcmple
|
||||
<BR><BR>[Stack]<UL><LI>Max Depth = 128<LI>Call Chain = UART_Handler ⇒ UARTHandle ⇒ ChannelSelection_control ⇒ regWrite ⇒ floor ⇒ __aeabi_cdrcmple
|
||||
</UL>
|
||||
<BR>[Calls]<UL><LI><a href="#[2f]">>></a> UARTHandle
|
||||
</UL>
|
||||
<BR>[Address Reference Count : 1]<UL><LI> startup_cmsdk_cm0.o(RESET)
|
||||
</UL>
|
||||
<P><STRONG><a name="[9]"></a>RSSI_Scan_Done</STRONG> (Thumb, 8 bytes, Stack size 0 bytes, startup_cmsdk_cm0.o(.text))
|
||||
<BR><BR>[Stack]<UL><LI>Max Depth = 200<LI>Call Chain = RSSI_Scan_Done ⇒ RSSIScanHandler ⇒ RSSIScanscreen ⇒ floor ⇒ __aeabi_cdrcmple
|
||||
<BR><BR>[Stack]<UL><LI>Max Depth = 208<LI>Call Chain = RSSI_Scan_Done ⇒ RSSIScanHandler ⇒ RSSIScanscreen ⇒ __aeabi_dmul
|
||||
</UL>
|
||||
<BR>[Calls]<UL><LI><a href="#[30]">>></a> RSSIScanHandler
|
||||
</UL>
|
||||
@ -336,31 +342,31 @@ Global Symbols
|
||||
<BR><BR>[Called By]<UL><LI><a href="#[23]">>></a> __user_setup_stackheap
|
||||
</UL>
|
||||
|
||||
<P><STRONG><a name="[75]"></a>strlen</STRONG> (Thumb, 62 bytes, Stack size 12 bytes, strlen.o(.text))
|
||||
<P><STRONG><a name="[76]"></a>strlen</STRONG> (Thumb, 62 bytes, Stack size 12 bytes, strlen.o(.text))
|
||||
<BR><BR>[Stack]<UL><LI>Max Depth = 12<LI>Call Chain = strlen
|
||||
</UL>
|
||||
<BR>[Called By]<UL><LI><a href="#[56]">>></a> UARTString
|
||||
</UL>
|
||||
|
||||
<P><STRONG><a name="[a7]"></a>__aeabi_uidiv</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, aeabi_sdiv.o(.text), UNUSED)
|
||||
<P><STRONG><a name="[ac]"></a>__aeabi_uidiv</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, aeabi_sdiv.o(.text), UNUSED)
|
||||
|
||||
<P><STRONG><a name="[62]"></a>__aeabi_uidivmod</STRONG> (Thumb, 20 bytes, Stack size 0 bytes, aeabi_sdiv.o(.text))
|
||||
<BR><BR>[Called By]<UL><LI><a href="#[5f]">>></a> Channel_control
|
||||
<P><STRONG><a name="[63]"></a>__aeabi_uidivmod</STRONG> (Thumb, 20 bytes, Stack size 0 bytes, aeabi_sdiv.o(.text))
|
||||
<BR><BR>[Called By]<UL><LI><a href="#[60]">>></a> Channel_control
|
||||
</UL>
|
||||
|
||||
<P><STRONG><a name="[a8]"></a>__aeabi_idiv</STRONG> (Thumb, 0 bytes, Stack size 8 bytes, aeabi_sdiv.o(.text), UNUSED)
|
||||
<P><STRONG><a name="[ad]"></a>__aeabi_idiv</STRONG> (Thumb, 0 bytes, Stack size 8 bytes, aeabi_sdiv.o(.text), UNUSED)
|
||||
|
||||
<P><STRONG><a name="[79]"></a>__aeabi_idivmod</STRONG> (Thumb, 326 bytes, Stack size 8 bytes, aeabi_sdiv.o(.text))
|
||||
<P><STRONG><a name="[7d]"></a>__aeabi_idivmod</STRONG> (Thumb, 326 bytes, Stack size 8 bytes, aeabi_sdiv.o(.text))
|
||||
<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = __aeabi_idivmod
|
||||
</UL>
|
||||
<BR>[Called By]<UL><LI><a href="#[5e]">>></a> int_to_str
|
||||
</UL>
|
||||
|
||||
<P><STRONG><a name="[a9]"></a>__use_two_region_memory</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, heapauxi.o(.text), UNUSED)
|
||||
<P><STRONG><a name="[ae]"></a>__use_two_region_memory</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, heapauxi.o(.text), UNUSED)
|
||||
|
||||
<P><STRONG><a name="[aa]"></a>__rt_heap_escrow$2region</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, heapauxi.o(.text), UNUSED)
|
||||
<P><STRONG><a name="[af]"></a>__rt_heap_escrow$2region</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, heapauxi.o(.text), UNUSED)
|
||||
|
||||
<P><STRONG><a name="[ab]"></a>__rt_heap_expand$2region</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, heapauxi.o(.text), UNUSED)
|
||||
<P><STRONG><a name="[b0]"></a>__rt_heap_expand$2region</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, heapauxi.o(.text), UNUSED)
|
||||
|
||||
<P><STRONG><a name="[68]"></a>__aeabi_d2f</STRONG> (Thumb, 0 bytes, Stack size 12 bytes, d2f.o(.text))
|
||||
<BR><BR>[Stack]<UL><LI>Max Depth = 12<LI>Call Chain = __aeabi_d2f
|
||||
@ -369,12 +375,12 @@ Global Symbols
|
||||
<LI><a href="#[30]">>></a> RSSIScanHandler
|
||||
</UL>
|
||||
|
||||
<P><STRONG><a name="[ac]"></a>_d2f</STRONG> (Thumb, 120 bytes, Stack size 12 bytes, d2f.o(.text), UNUSED)
|
||||
<P><STRONG><a name="[b1]"></a>_d2f</STRONG> (Thumb, 120 bytes, Stack size 12 bytes, d2f.o(.text), UNUSED)
|
||||
|
||||
<P><STRONG><a name="[67]"></a>__aeabi_dadd</STRONG> (Thumb, 0 bytes, Stack size 8 bytes, daddsub.o(.text))
|
||||
<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = __aeabi_dadd
|
||||
</UL>
|
||||
<BR>[Called By]<UL><LI><a href="#[70]">>></a> floor
|
||||
<BR>[Called By]<UL><LI><a href="#[78]">>></a> floor
|
||||
<LI><a href="#[6a]">>></a> RSSIScanscreen
|
||||
<LI><a href="#[30]">>></a> RSSIScanHandler
|
||||
</UL>
|
||||
@ -384,17 +390,17 @@ Global Symbols
|
||||
<LI><a href="#[43]">>></a> _dadd1
|
||||
</UL>
|
||||
|
||||
<P><STRONG><a name="[ad]"></a>__aeabi_dsub</STRONG> (Thumb, 0 bytes, Stack size 8 bytes, daddsub.o(.text), UNUSED)
|
||||
<P><STRONG><a name="[b2]"></a>__aeabi_dsub</STRONG> (Thumb, 0 bytes, Stack size 8 bytes, daddsub.o(.text), UNUSED)
|
||||
|
||||
<P><STRONG><a name="[44]"></a>_dsub</STRONG> (Thumb, 22 bytes, Stack size 8 bytes, daddsub.o(.text), UNUSED)
|
||||
<BR><BR>[Calls]<UL><LI><a href="#[42]">>></a> _dsub1
|
||||
<LI><a href="#[43]">>></a> _dadd1
|
||||
</UL>
|
||||
|
||||
<P><STRONG><a name="[78]"></a>__aeabi_drsub</STRONG> (Thumb, 0 bytes, Stack size 16 bytes, daddsub.o(.text))
|
||||
<P><STRONG><a name="[7a]"></a>__aeabi_drsub</STRONG> (Thumb, 0 bytes, Stack size 16 bytes, daddsub.o(.text))
|
||||
<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = __aeabi_drsub
|
||||
</UL>
|
||||
<BR>[Called By]<UL><LI><a href="#[70]">>></a> floor
|
||||
<BR>[Called By]<UL><LI><a href="#[78]">>></a> floor
|
||||
</UL>
|
||||
|
||||
<P><STRONG><a name="[45]"></a>_drsb</STRONG> (Thumb, 28 bytes, Stack size 16 bytes, daddsub.o(.text), UNUSED)
|
||||
@ -402,37 +408,38 @@ Global Symbols
|
||||
<LI><a href="#[43]">>></a> _dadd1
|
||||
</UL>
|
||||
|
||||
<P><STRONG><a name="[7a]"></a>__aeabi_d2iz</STRONG> (Thumb, 0 bytes, Stack size 12 bytes, dfixi.o(.text))
|
||||
<P><STRONG><a name="[71]"></a>__aeabi_d2iz</STRONG> (Thumb, 0 bytes, Stack size 12 bytes, dfixi.o(.text))
|
||||
<BR><BR>[Stack]<UL><LI>Max Depth = 12<LI>Call Chain = __aeabi_d2iz
|
||||
</UL>
|
||||
<BR>[Called By]<UL><LI><a href="#[59]">>></a> singleFrequencyRSSI
|
||||
<LI><a href="#[63]">>></a> regWrite
|
||||
<LI><a href="#[5f]">>></a> regWrite
|
||||
<LI><a href="#[6a]">>></a> RSSIScanscreen
|
||||
</UL>
|
||||
|
||||
<P><STRONG><a name="[ae]"></a>_dfix</STRONG> (Thumb, 98 bytes, Stack size 12 bytes, dfixi.o(.text), UNUSED)
|
||||
<P><STRONG><a name="[b3]"></a>_dfix</STRONG> (Thumb, 98 bytes, Stack size 12 bytes, dfixi.o(.text), UNUSED)
|
||||
|
||||
<P><STRONG><a name="[71]"></a>__aeabi_d2uiz</STRONG> (Thumb, 0 bytes, Stack size 8 bytes, dfixui.o(.text))
|
||||
<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = __aeabi_d2uiz
|
||||
<P><STRONG><a name="[70]"></a>__aeabi_dmul</STRONG> (Thumb, 0 bytes, Stack size 56 bytes, dmul.o(.text))
|
||||
<BR><BR>[Stack]<UL><LI>Max Depth = 56<LI>Call Chain = __aeabi_dmul
|
||||
</UL>
|
||||
<BR>[Called By]<UL><LI><a href="#[6a]">>></a> RSSIScanscreen
|
||||
</UL>
|
||||
|
||||
<P><STRONG><a name="[af]"></a>_dfixu</STRONG> (Thumb, 68 bytes, Stack size 8 bytes, dfixui.o(.text), UNUSED)
|
||||
<P><STRONG><a name="[b4]"></a>_dmul</STRONG> (Thumb, 558 bytes, Stack size 56 bytes, dmul.o(.text), UNUSED)
|
||||
|
||||
<P><STRONG><a name="[66]"></a>__aeabi_f2d</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, f2d.o(.text))
|
||||
<BR><BR>[Called By]<UL><LI><a href="#[59]">>></a> singleFrequencyRSSI
|
||||
<LI><a href="#[63]">>></a> regWrite
|
||||
<LI><a href="#[5f]">>></a> regWrite
|
||||
<LI><a href="#[6a]">>></a> RSSIScanscreen
|
||||
<LI><a href="#[30]">>></a> RSSIScanHandler
|
||||
</UL>
|
||||
|
||||
<P><STRONG><a name="[b0]"></a>_f2d</STRONG> (Thumb, 80 bytes, Stack size 0 bytes, f2d.o(.text), UNUSED)
|
||||
<P><STRONG><a name="[b5]"></a>_f2d</STRONG> (Thumb, 80 bytes, Stack size 0 bytes, f2d.o(.text), UNUSED)
|
||||
|
||||
<P><STRONG><a name="[6e]"></a>__aeabi_fdiv</STRONG> (Thumb, 0 bytes, Stack size 20 bytes, fdiv.o(.text))
|
||||
<P><STRONG><a name="[6b]"></a>__aeabi_fdiv</STRONG> (Thumb, 0 bytes, Stack size 20 bytes, fdiv.o(.text))
|
||||
<BR><BR>[Stack]<UL><LI>Max Depth = 20<LI>Call Chain = __aeabi_fdiv
|
||||
</UL>
|
||||
<BR>[Called By]<UL><LI><a href="#[59]">>></a> singleFrequencyRSSI
|
||||
<LI><a href="#[63]">>></a> regWrite
|
||||
<LI><a href="#[5f]">>></a> regWrite
|
||||
<LI><a href="#[6a]">>></a> RSSIScanscreen
|
||||
</UL>
|
||||
|
||||
@ -444,21 +451,21 @@ Global Symbols
|
||||
<BR><BR>[Calls]<UL><LI><a href="#[47]">>></a> _fdiv
|
||||
</UL>
|
||||
|
||||
<P><STRONG><a name="[7b]"></a>__aeabi_f2iz</STRONG> (Thumb, 0 bytes, Stack size 8 bytes, ffixi.o(.text))
|
||||
<P><STRONG><a name="[7e]"></a>__aeabi_f2iz</STRONG> (Thumb, 0 bytes, Stack size 8 bytes, ffixi.o(.text))
|
||||
<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = __aeabi_f2iz
|
||||
</UL>
|
||||
<BR>[Called By]<UL><LI><a href="#[59]">>></a> singleFrequencyRSSI
|
||||
<LI><a href="#[63]">>></a> regWrite
|
||||
<LI><a href="#[5f]">>></a> regWrite
|
||||
</UL>
|
||||
|
||||
<P><STRONG><a name="[b1]"></a>_ffix</STRONG> (Thumb, 76 bytes, Stack size 8 bytes, ffixi.o(.text), UNUSED)
|
||||
<P><STRONG><a name="[b6]"></a>_ffix</STRONG> (Thumb, 76 bytes, Stack size 8 bytes, ffixi.o(.text), UNUSED)
|
||||
|
||||
<P><STRONG><a name="[61]"></a>__aeabi_f2uiz</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, ffixui.o(.text))
|
||||
<P><STRONG><a name="[62]"></a>__aeabi_f2uiz</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, ffixui.o(.text))
|
||||
<BR><BR>[Called By]<UL><LI><a href="#[6a]">>></a> RSSIScanscreen
|
||||
<LI><a href="#[5f]">>></a> Channel_control
|
||||
<LI><a href="#[60]">>></a> Channel_control
|
||||
</UL>
|
||||
|
||||
<P><STRONG><a name="[b2]"></a>_ffixu</STRONG> (Thumb, 48 bytes, Stack size 0 bytes, ffixui.o(.text), UNUSED)
|
||||
<P><STRONG><a name="[b7]"></a>_ffixu</STRONG> (Thumb, 48 bytes, Stack size 0 bytes, ffixui.o(.text), UNUSED)
|
||||
|
||||
<P><STRONG><a name="[49]"></a>__aeabi_i2f_normalise</STRONG> (Thumb, 72 bytes, Stack size 0 bytes, fflti.o(.text))
|
||||
<BR><BR>[Called By]<UL><LI><a href="#[4a]">>></a> __aeabi_ui2f
|
||||
@ -469,11 +476,11 @@ Global Symbols
|
||||
<BR><BR>[Calls]<UL><LI><a href="#[49]">>></a> __aeabi_i2f_normalise
|
||||
</UL>
|
||||
<BR>[Called By]<UL><LI><a href="#[59]">>></a> singleFrequencyRSSI
|
||||
<LI><a href="#[63]">>></a> regWrite
|
||||
<LI><a href="#[5f]">>></a> regWrite
|
||||
<LI><a href="#[6a]">>></a> RSSIScanscreen
|
||||
</UL>
|
||||
|
||||
<P><STRONG><a name="[b3]"></a>_fflt</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, fflti.o(.text), UNUSED)
|
||||
<P><STRONG><a name="[b8]"></a>_fflt</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, fflti.o(.text), UNUSED)
|
||||
|
||||
<P><STRONG><a name="[4a]"></a>__aeabi_ui2f</STRONG> (Thumb, 6 bytes, Stack size 0 bytes, fflti.o(.text))
|
||||
<BR><BR>[Calls]<UL><LI><a href="#[49]">>></a> __aeabi_i2f_normalise
|
||||
@ -481,21 +488,22 @@ Global Symbols
|
||||
<BR>[Called By]<UL><LI><a href="#[6a]">>></a> RSSIScanscreen
|
||||
</UL>
|
||||
|
||||
<P><STRONG><a name="[b4]"></a>_ffltu</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, fflti.o(.text), UNUSED)
|
||||
<P><STRONG><a name="[b9]"></a>_ffltu</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, fflti.o(.text), UNUSED)
|
||||
|
||||
<P><STRONG><a name="[4b]"></a>__fpl_dcmp_InfNaN</STRONG> (Thumb, 140 bytes, Stack size 24 bytes, dcmpin.o(.text), UNUSED)
|
||||
<BR><BR>[Calls]<UL><LI><a href="#[4d]">>></a> __fpl_dcheck_NaN2
|
||||
<LI><a href="#[4c]">>></a> __fpl_cmpreturn
|
||||
</UL>
|
||||
<BR>[Called By]<UL><LI><a href="#[7d]">>></a> _drcmple
|
||||
<LI><a href="#[7c]">>></a> _dcmple
|
||||
<BR>[Called By]<UL><LI><a href="#[80]">>></a> _drcmple
|
||||
<LI><a href="#[7f]">>></a> _dcmple
|
||||
</UL>
|
||||
|
||||
<P><STRONG><a name="[4e]"></a>__fpl_fcmp_InfNaN</STRONG> (Thumb, 96 bytes, Stack size 8 bytes, fcmpin.o(.text), UNUSED)
|
||||
<BR><BR>[Calls]<UL><LI><a href="#[4f]">>></a> __fpl_fcheck_NaN2
|
||||
<LI><a href="#[4c]">>></a> __fpl_cmpreturn
|
||||
</UL>
|
||||
<BR>[Called By]<UL><LI><a href="#[80]">>></a> _fcmple
|
||||
<BR>[Called By]<UL><LI><a href="#[84]">>></a> _fcmple
|
||||
<LI><a href="#[83]">>></a> _fcmpeq
|
||||
</UL>
|
||||
|
||||
<P><STRONG><a name="[4c]"></a>__fpl_cmpreturn</STRONG> (Thumb, 46 bytes, Stack size 0 bytes, cmpret.o(.text), UNUSED)
|
||||
@ -543,23 +551,23 @@ Global Symbols
|
||||
<LI><a href="#[4d]">>></a> __fpl_dcheck_NaN2
|
||||
</UL>
|
||||
|
||||
<P><STRONG><a name="[b5]"></a>__user_libspace</STRONG> (Thumb, 8 bytes, Stack size 0 bytes, libspace.o(.text), UNUSED)
|
||||
<P><STRONG><a name="[ba]"></a>__user_libspace</STRONG> (Thumb, 8 bytes, Stack size 0 bytes, libspace.o(.text), UNUSED)
|
||||
|
||||
<P><STRONG><a name="[51]"></a>__user_perproc_libspace</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, libspace.o(.text))
|
||||
<BR><BR>[Called By]<UL><LI><a href="#[23]">>></a> __user_setup_stackheap
|
||||
</UL>
|
||||
|
||||
<P><STRONG><a name="[b6]"></a>__user_perthread_libspace</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, libspace.o(.text), UNUSED)
|
||||
<P><STRONG><a name="[bb]"></a>__user_perthread_libspace</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, libspace.o(.text), UNUSED)
|
||||
|
||||
<P><STRONG><a name="[2c]"></a>_sys_exit</STRONG> (Thumb, 8 bytes, Stack size 0 bytes, sys_exit.o(.text))
|
||||
<BR><BR>[Called By]<UL><LI><a href="#[2b]">>></a> __rt_exit_exit
|
||||
</UL>
|
||||
|
||||
<P><STRONG><a name="[b7]"></a>__I$use$semihosting</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, use_no_semi.o(.text), UNUSED)
|
||||
<P><STRONG><a name="[bc]"></a>__I$use$semihosting</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, use_no_semi.o(.text), UNUSED)
|
||||
|
||||
<P><STRONG><a name="[b8]"></a>__use_no_semihosting_swi</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, use_no_semi.o(.text), UNUSED)
|
||||
<P><STRONG><a name="[bd]"></a>__use_no_semihosting_swi</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, use_no_semi.o(.text), UNUSED)
|
||||
|
||||
<P><STRONG><a name="[b9]"></a>__semihosting_library_function</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, indicate_semi.o(.text), UNUSED)
|
||||
<P><STRONG><a name="[be]"></a>__semihosting_library_function</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, indicate_semi.o(.text), UNUSED)
|
||||
|
||||
<P><STRONG><a name="[6f]"></a>Bubbling</STRONG> (Thumb, 100 bytes, Stack size 20 bytes, code_def.o(i.Bubbling))
|
||||
<BR><BR>[Stack]<UL><LI>Max Depth = 20<LI>Call Chain = Bubbling
|
||||
@ -567,10 +575,11 @@ Global Symbols
|
||||
<BR>[Called By]<UL><LI><a href="#[6a]">>></a> RSSIScanscreen
|
||||
</UL>
|
||||
|
||||
<P><STRONG><a name="[54]"></a>ChannelSelection_control</STRONG> (Thumb, 5260 bytes, Stack size 16 bytes, channelselection_control.o(i.ChannelSelection_control))
|
||||
<BR><BR>[Stack]<UL><LI>Max Depth = 112<LI>Call Chain = ChannelSelection_control ⇒ singleFrequencyRSSI ⇒ floor ⇒ __aeabi_cdrcmple
|
||||
<P><STRONG><a name="[54]"></a>ChannelSelection_control</STRONG> (Thumb, 2280 bytes, Stack size 16 bytes, channelselection_control.o(i.ChannelSelection_control))
|
||||
<BR><BR>[Stack]<UL><LI>Max Depth = 120<LI>Call Chain = ChannelSelection_control ⇒ regWrite ⇒ floor ⇒ __aeabi_cdrcmple
|
||||
</UL>
|
||||
<BR>[Calls]<UL><LI><a href="#[59]">>></a> singleFrequencyRSSI
|
||||
<LI><a href="#[5f]">>></a> regWrite
|
||||
<LI><a href="#[57]">>></a> WriteUART
|
||||
<LI><a href="#[56]">>></a> UARTString
|
||||
<LI><a href="#[58]">>></a> Stop_FM_command
|
||||
@ -579,20 +588,21 @@ Global Symbols
|
||||
<LI><a href="#[5a]">>></a> RSSI_scan_cmd
|
||||
<LI><a href="#[5b]">>></a> IQ_Dump_command
|
||||
<LI><a href="#[5c]">>></a> Demodulated_Data_Dump_command
|
||||
<LI><a href="#[5f]">>></a> Channel_control
|
||||
<LI><a href="#[60]">>></a> Channel_control
|
||||
<LI><a href="#[5e]">>></a> int_to_str
|
||||
</UL>
|
||||
<BR>[Called By]<UL><LI><a href="#[2f]">>></a> UARTHandle
|
||||
</UL>
|
||||
|
||||
<P><STRONG><a name="[5f]"></a>Channel_control</STRONG> (Thumb, 106 bytes, Stack size 32 bytes, code_def.o(i.Channel_control))
|
||||
<P><STRONG><a name="[60]"></a>Channel_control</STRONG> (Thumb, 106 bytes, Stack size 32 bytes, code_def.o(i.Channel_control))
|
||||
<BR><BR>[Stack]<UL><LI>Max Depth = 48<LI>Call Chain = Channel_control ⇒ __aeabi_fmul
|
||||
</UL>
|
||||
<BR>[Calls]<UL><LI><a href="#[60]">>></a> __aeabi_fmul
|
||||
<LI><a href="#[61]">>></a> __aeabi_f2uiz
|
||||
<LI><a href="#[62]">>></a> __aeabi_uidivmod
|
||||
<BR>[Calls]<UL><LI><a href="#[61]">>></a> __aeabi_fmul
|
||||
<LI><a href="#[62]">>></a> __aeabi_f2uiz
|
||||
<LI><a href="#[63]">>></a> __aeabi_uidivmod
|
||||
</UL>
|
||||
<BR>[Called By]<UL><LI><a href="#[54]">>></a> ChannelSelection_control
|
||||
<LI><a href="#[30]">>></a> RSSIScanHandler
|
||||
<LI><a href="#[3a]">>></a> KEY9
|
||||
<LI><a href="#[39]">>></a> KEY8
|
||||
<LI><a href="#[38]">>></a> KEY7
|
||||
@ -611,7 +621,7 @@ Global Symbols
|
||||
<LI><a href="#[31]">>></a> KEY0
|
||||
</UL>
|
||||
|
||||
<P><STRONG><a name="[74]"></a>Delay</STRONG> (Thumb, 18 bytes, Stack size 0 bytes, code_def.o(i.Delay))
|
||||
<P><STRONG><a name="[75]"></a>Delay</STRONG> (Thumb, 18 bytes, Stack size 0 bytes, code_def.o(i.Delay))
|
||||
<BR><BR>[Called By]<UL><LI><a href="#[27]">>></a> main
|
||||
<LI><a href="#[56]">>></a> UARTString
|
||||
</UL>
|
||||
@ -627,9 +637,9 @@ Global Symbols
|
||||
<P><STRONG><a name="[31]"></a>KEY0</STRONG> (Thumb, 26 bytes, Stack size 8 bytes, code_def.o(i.KEY0))
|
||||
<BR><BR>[Stack]<UL><LI>Max Depth = 112<LI>Call Chain = KEY0 ⇒ regWrite ⇒ floor ⇒ __aeabi_cdrcmple
|
||||
</UL>
|
||||
<BR>[Calls]<UL><LI><a href="#[63]">>></a> regWrite
|
||||
<BR>[Calls]<UL><LI><a href="#[5f]">>></a> regWrite
|
||||
<LI><a href="#[56]">>></a> UARTString
|
||||
<LI><a href="#[5f]">>></a> Channel_control
|
||||
<LI><a href="#[60]">>></a> Channel_control
|
||||
</UL>
|
||||
<BR>[Called By]<UL><LI><a href="#[19]">>></a> KEY0_Handler
|
||||
</UL>
|
||||
@ -637,9 +647,9 @@ Global Symbols
|
||||
<P><STRONG><a name="[32]"></a>KEY1</STRONG> (Thumb, 28 bytes, Stack size 8 bytes, code_def.o(i.KEY1))
|
||||
<BR><BR>[Stack]<UL><LI>Max Depth = 112<LI>Call Chain = KEY1 ⇒ regWrite ⇒ floor ⇒ __aeabi_cdrcmple
|
||||
</UL>
|
||||
<BR>[Calls]<UL><LI><a href="#[63]">>></a> regWrite
|
||||
<BR>[Calls]<UL><LI><a href="#[5f]">>></a> regWrite
|
||||
<LI><a href="#[56]">>></a> UARTString
|
||||
<LI><a href="#[5f]">>></a> Channel_control
|
||||
<LI><a href="#[60]">>></a> Channel_control
|
||||
</UL>
|
||||
<BR>[Called By]<UL><LI><a href="#[18]">>></a> KEY1_Handler
|
||||
</UL>
|
||||
@ -647,9 +657,9 @@ Global Symbols
|
||||
<P><STRONG><a name="[3b]"></a>KEY10</STRONG> (Thumb, 30 bytes, Stack size 8 bytes, code_def.o(i.KEY10))
|
||||
<BR><BR>[Stack]<UL><LI>Max Depth = 112<LI>Call Chain = KEY10 ⇒ regWrite ⇒ floor ⇒ __aeabi_cdrcmple
|
||||
</UL>
|
||||
<BR>[Calls]<UL><LI><a href="#[63]">>></a> regWrite
|
||||
<BR>[Calls]<UL><LI><a href="#[5f]">>></a> regWrite
|
||||
<LI><a href="#[56]">>></a> UARTString
|
||||
<LI><a href="#[5f]">>></a> Channel_control
|
||||
<LI><a href="#[60]">>></a> Channel_control
|
||||
</UL>
|
||||
<BR>[Called By]<UL><LI><a href="#[f]">>></a> KEY10_Handler
|
||||
</UL>
|
||||
@ -657,9 +667,9 @@ Global Symbols
|
||||
<P><STRONG><a name="[3c]"></a>KEY11</STRONG> (Thumb, 30 bytes, Stack size 8 bytes, code_def.o(i.KEY11))
|
||||
<BR><BR>[Stack]<UL><LI>Max Depth = 112<LI>Call Chain = KEY11 ⇒ regWrite ⇒ floor ⇒ __aeabi_cdrcmple
|
||||
</UL>
|
||||
<BR>[Calls]<UL><LI><a href="#[63]">>></a> regWrite
|
||||
<BR>[Calls]<UL><LI><a href="#[5f]">>></a> regWrite
|
||||
<LI><a href="#[56]">>></a> UARTString
|
||||
<LI><a href="#[5f]">>></a> Channel_control
|
||||
<LI><a href="#[60]">>></a> Channel_control
|
||||
</UL>
|
||||
<BR>[Called By]<UL><LI><a href="#[e]">>></a> KEY11_Handler
|
||||
</UL>
|
||||
@ -667,9 +677,9 @@ Global Symbols
|
||||
<P><STRONG><a name="[3d]"></a>KEY12</STRONG> (Thumb, 30 bytes, Stack size 8 bytes, code_def.o(i.KEY12))
|
||||
<BR><BR>[Stack]<UL><LI>Max Depth = 112<LI>Call Chain = KEY12 ⇒ regWrite ⇒ floor ⇒ __aeabi_cdrcmple
|
||||
</UL>
|
||||
<BR>[Calls]<UL><LI><a href="#[63]">>></a> regWrite
|
||||
<BR>[Calls]<UL><LI><a href="#[5f]">>></a> regWrite
|
||||
<LI><a href="#[56]">>></a> UARTString
|
||||
<LI><a href="#[5f]">>></a> Channel_control
|
||||
<LI><a href="#[60]">>></a> Channel_control
|
||||
</UL>
|
||||
<BR>[Called By]<UL><LI><a href="#[d]">>></a> KEY12_Handler
|
||||
</UL>
|
||||
@ -677,9 +687,9 @@ Global Symbols
|
||||
<P><STRONG><a name="[3e]"></a>KEY13</STRONG> (Thumb, 30 bytes, Stack size 8 bytes, code_def.o(i.KEY13))
|
||||
<BR><BR>[Stack]<UL><LI>Max Depth = 112<LI>Call Chain = KEY13 ⇒ regWrite ⇒ floor ⇒ __aeabi_cdrcmple
|
||||
</UL>
|
||||
<BR>[Calls]<UL><LI><a href="#[63]">>></a> regWrite
|
||||
<BR>[Calls]<UL><LI><a href="#[5f]">>></a> regWrite
|
||||
<LI><a href="#[56]">>></a> UARTString
|
||||
<LI><a href="#[5f]">>></a> Channel_control
|
||||
<LI><a href="#[60]">>></a> Channel_control
|
||||
</UL>
|
||||
<BR>[Called By]<UL><LI><a href="#[c]">>></a> KEY13_Handler
|
||||
</UL>
|
||||
@ -687,9 +697,9 @@ Global Symbols
|
||||
<P><STRONG><a name="[3f]"></a>KEY14</STRONG> (Thumb, 30 bytes, Stack size 8 bytes, code_def.o(i.KEY14))
|
||||
<BR><BR>[Stack]<UL><LI>Max Depth = 112<LI>Call Chain = KEY14 ⇒ regWrite ⇒ floor ⇒ __aeabi_cdrcmple
|
||||
</UL>
|
||||
<BR>[Calls]<UL><LI><a href="#[63]">>></a> regWrite
|
||||
<BR>[Calls]<UL><LI><a href="#[5f]">>></a> regWrite
|
||||
<LI><a href="#[56]">>></a> UARTString
|
||||
<LI><a href="#[5f]">>></a> Channel_control
|
||||
<LI><a href="#[60]">>></a> Channel_control
|
||||
</UL>
|
||||
<BR>[Called By]<UL><LI><a href="#[b]">>></a> KEY14_Handler
|
||||
</UL>
|
||||
@ -697,9 +707,9 @@ Global Symbols
|
||||
<P><STRONG><a name="[40]"></a>KEY15</STRONG> (Thumb, 30 bytes, Stack size 8 bytes, code_def.o(i.KEY15))
|
||||
<BR><BR>[Stack]<UL><LI>Max Depth = 112<LI>Call Chain = KEY15 ⇒ regWrite ⇒ floor ⇒ __aeabi_cdrcmple
|
||||
</UL>
|
||||
<BR>[Calls]<UL><LI><a href="#[63]">>></a> regWrite
|
||||
<BR>[Calls]<UL><LI><a href="#[5f]">>></a> regWrite
|
||||
<LI><a href="#[56]">>></a> UARTString
|
||||
<LI><a href="#[5f]">>></a> Channel_control
|
||||
<LI><a href="#[60]">>></a> Channel_control
|
||||
</UL>
|
||||
<BR>[Called By]<UL><LI><a href="#[a]">>></a> KEY15_Handler
|
||||
</UL>
|
||||
@ -707,9 +717,9 @@ Global Symbols
|
||||
<P><STRONG><a name="[33]"></a>KEY2</STRONG> (Thumb, 28 bytes, Stack size 8 bytes, code_def.o(i.KEY2))
|
||||
<BR><BR>[Stack]<UL><LI>Max Depth = 112<LI>Call Chain = KEY2 ⇒ regWrite ⇒ floor ⇒ __aeabi_cdrcmple
|
||||
</UL>
|
||||
<BR>[Calls]<UL><LI><a href="#[63]">>></a> regWrite
|
||||
<BR>[Calls]<UL><LI><a href="#[5f]">>></a> regWrite
|
||||
<LI><a href="#[56]">>></a> UARTString
|
||||
<LI><a href="#[5f]">>></a> Channel_control
|
||||
<LI><a href="#[60]">>></a> Channel_control
|
||||
</UL>
|
||||
<BR>[Called By]<UL><LI><a href="#[17]">>></a> KEY2_Handler
|
||||
</UL>
|
||||
@ -717,9 +727,9 @@ Global Symbols
|
||||
<P><STRONG><a name="[34]"></a>KEY3</STRONG> (Thumb, 28 bytes, Stack size 8 bytes, code_def.o(i.KEY3))
|
||||
<BR><BR>[Stack]<UL><LI>Max Depth = 112<LI>Call Chain = KEY3 ⇒ regWrite ⇒ floor ⇒ __aeabi_cdrcmple
|
||||
</UL>
|
||||
<BR>[Calls]<UL><LI><a href="#[63]">>></a> regWrite
|
||||
<BR>[Calls]<UL><LI><a href="#[5f]">>></a> regWrite
|
||||
<LI><a href="#[56]">>></a> UARTString
|
||||
<LI><a href="#[5f]">>></a> Channel_control
|
||||
<LI><a href="#[60]">>></a> Channel_control
|
||||
</UL>
|
||||
<BR>[Called By]<UL><LI><a href="#[16]">>></a> KEY3_Handler
|
||||
</UL>
|
||||
@ -727,9 +737,9 @@ Global Symbols
|
||||
<P><STRONG><a name="[35]"></a>KEY4</STRONG> (Thumb, 28 bytes, Stack size 8 bytes, code_def.o(i.KEY4))
|
||||
<BR><BR>[Stack]<UL><LI>Max Depth = 112<LI>Call Chain = KEY4 ⇒ regWrite ⇒ floor ⇒ __aeabi_cdrcmple
|
||||
</UL>
|
||||
<BR>[Calls]<UL><LI><a href="#[63]">>></a> regWrite
|
||||
<BR>[Calls]<UL><LI><a href="#[5f]">>></a> regWrite
|
||||
<LI><a href="#[56]">>></a> UARTString
|
||||
<LI><a href="#[5f]">>></a> Channel_control
|
||||
<LI><a href="#[60]">>></a> Channel_control
|
||||
</UL>
|
||||
<BR>[Called By]<UL><LI><a href="#[15]">>></a> KEY4_Handler
|
||||
</UL>
|
||||
@ -737,9 +747,9 @@ Global Symbols
|
||||
<P><STRONG><a name="[36]"></a>KEY5</STRONG> (Thumb, 28 bytes, Stack size 8 bytes, code_def.o(i.KEY5))
|
||||
<BR><BR>[Stack]<UL><LI>Max Depth = 112<LI>Call Chain = KEY5 ⇒ regWrite ⇒ floor ⇒ __aeabi_cdrcmple
|
||||
</UL>
|
||||
<BR>[Calls]<UL><LI><a href="#[63]">>></a> regWrite
|
||||
<BR>[Calls]<UL><LI><a href="#[5f]">>></a> regWrite
|
||||
<LI><a href="#[56]">>></a> UARTString
|
||||
<LI><a href="#[5f]">>></a> Channel_control
|
||||
<LI><a href="#[60]">>></a> Channel_control
|
||||
</UL>
|
||||
<BR>[Called By]<UL><LI><a href="#[14]">>></a> KEY5_Handler
|
||||
</UL>
|
||||
@ -747,9 +757,9 @@ Global Symbols
|
||||
<P><STRONG><a name="[37]"></a>KEY6</STRONG> (Thumb, 28 bytes, Stack size 8 bytes, code_def.o(i.KEY6))
|
||||
<BR><BR>[Stack]<UL><LI>Max Depth = 112<LI>Call Chain = KEY6 ⇒ regWrite ⇒ floor ⇒ __aeabi_cdrcmple
|
||||
</UL>
|
||||
<BR>[Calls]<UL><LI><a href="#[63]">>></a> regWrite
|
||||
<BR>[Calls]<UL><LI><a href="#[5f]">>></a> regWrite
|
||||
<LI><a href="#[56]">>></a> UARTString
|
||||
<LI><a href="#[5f]">>></a> Channel_control
|
||||
<LI><a href="#[60]">>></a> Channel_control
|
||||
</UL>
|
||||
<BR>[Called By]<UL><LI><a href="#[13]">>></a> KEY6_Handler
|
||||
</UL>
|
||||
@ -757,9 +767,9 @@ Global Symbols
|
||||
<P><STRONG><a name="[38]"></a>KEY7</STRONG> (Thumb, 28 bytes, Stack size 8 bytes, code_def.o(i.KEY7))
|
||||
<BR><BR>[Stack]<UL><LI>Max Depth = 112<LI>Call Chain = KEY7 ⇒ regWrite ⇒ floor ⇒ __aeabi_cdrcmple
|
||||
</UL>
|
||||
<BR>[Calls]<UL><LI><a href="#[63]">>></a> regWrite
|
||||
<BR>[Calls]<UL><LI><a href="#[5f]">>></a> regWrite
|
||||
<LI><a href="#[56]">>></a> UARTString
|
||||
<LI><a href="#[5f]">>></a> Channel_control
|
||||
<LI><a href="#[60]">>></a> Channel_control
|
||||
</UL>
|
||||
<BR>[Called By]<UL><LI><a href="#[12]">>></a> KEY7_Handler
|
||||
</UL>
|
||||
@ -767,9 +777,9 @@ Global Symbols
|
||||
<P><STRONG><a name="[39]"></a>KEY8</STRONG> (Thumb, 26 bytes, Stack size 8 bytes, code_def.o(i.KEY8))
|
||||
<BR><BR>[Stack]<UL><LI>Max Depth = 112<LI>Call Chain = KEY8 ⇒ regWrite ⇒ floor ⇒ __aeabi_cdrcmple
|
||||
</UL>
|
||||
<BR>[Calls]<UL><LI><a href="#[63]">>></a> regWrite
|
||||
<BR>[Calls]<UL><LI><a href="#[5f]">>></a> regWrite
|
||||
<LI><a href="#[56]">>></a> UARTString
|
||||
<LI><a href="#[5f]">>></a> Channel_control
|
||||
<LI><a href="#[60]">>></a> Channel_control
|
||||
</UL>
|
||||
<BR>[Called By]<UL><LI><a href="#[11]">>></a> KEY8_Handler
|
||||
</UL>
|
||||
@ -777,45 +787,49 @@ Global Symbols
|
||||
<P><STRONG><a name="[3a]"></a>KEY9</STRONG> (Thumb, 30 bytes, Stack size 8 bytes, code_def.o(i.KEY9))
|
||||
<BR><BR>[Stack]<UL><LI>Max Depth = 112<LI>Call Chain = KEY9 ⇒ regWrite ⇒ floor ⇒ __aeabi_cdrcmple
|
||||
</UL>
|
||||
<BR>[Calls]<UL><LI><a href="#[63]">>></a> regWrite
|
||||
<BR>[Calls]<UL><LI><a href="#[5f]">>></a> regWrite
|
||||
<LI><a href="#[56]">>></a> UARTString
|
||||
<LI><a href="#[5f]">>></a> Channel_control
|
||||
<LI><a href="#[60]">>></a> Channel_control
|
||||
</UL>
|
||||
<BR>[Called By]<UL><LI><a href="#[10]">>></a> KEY9_Handler
|
||||
</UL>
|
||||
|
||||
<P><STRONG><a name="[30]"></a>RSSIScanHandler</STRONG> (Thumb, 120 bytes, Stack size 24 bytes, code_def.o(i.RSSIScanHandler))
|
||||
<BR><BR>[Stack]<UL><LI>Max Depth = 200<LI>Call Chain = RSSIScanHandler ⇒ RSSIScanscreen ⇒ floor ⇒ __aeabi_cdrcmple
|
||||
<P><STRONG><a name="[30]"></a>RSSIScanHandler</STRONG> (Thumb, 140 bytes, Stack size 24 bytes, code_def.o(i.RSSIScanHandler))
|
||||
<BR><BR>[Stack]<UL><LI>Max Depth = 208<LI>Call Chain = RSSIScanHandler ⇒ RSSIScanscreen ⇒ __aeabi_dmul
|
||||
</UL>
|
||||
<BR>[Calls]<UL><LI><a href="#[69]">>></a> __aeabi_cfcmple
|
||||
<LI><a href="#[66]">>></a> __aeabi_f2d
|
||||
<LI><a href="#[67]">>></a> __aeabi_dadd
|
||||
<LI><a href="#[68]">>></a> __aeabi_d2f
|
||||
<LI><a href="#[59]">>></a> singleFrequencyRSSI
|
||||
<LI><a href="#[5f]">>></a> regWrite
|
||||
<LI><a href="#[56]">>></a> UARTString
|
||||
<LI><a href="#[55]">>></a> Start_FM_command
|
||||
<LI><a href="#[5a]">>></a> RSSI_scan_cmd
|
||||
<LI><a href="#[64]">>></a> RSSI_read
|
||||
<LI><a href="#[65]">>></a> RSSI_done
|
||||
<LI><a href="#[6a]">>></a> RSSIScanscreen
|
||||
<LI><a href="#[60]">>></a> Channel_control
|
||||
</UL>
|
||||
<BR>[Called By]<UL><LI><a href="#[9]">>></a> RSSI_Scan_Done
|
||||
</UL>
|
||||
|
||||
<P><STRONG><a name="[6a]"></a>RSSIScanscreen</STRONG> (Thumb, 608 bytes, Stack size 120 bytes, code_def.o(i.RSSIScanscreen))
|
||||
<BR><BR>[Stack]<UL><LI>Max Depth = 176<LI>Call Chain = RSSIScanscreen ⇒ floor ⇒ __aeabi_cdrcmple
|
||||
<P><STRONG><a name="[6a]"></a>RSSIScanscreen</STRONG> (Thumb, 892 bytes, Stack size 128 bytes, code_def.o(i.RSSIScanscreen))
|
||||
<BR><BR>[Stack]<UL><LI>Max Depth = 184<LI>Call Chain = RSSIScanscreen ⇒ __aeabi_dmul
|
||||
</UL>
|
||||
<BR>[Calls]<UL><LI><a href="#[70]">>></a> floor
|
||||
<LI><a href="#[60]">>></a> __aeabi_fmul
|
||||
<BR>[Calls]<UL><LI><a href="#[61]">>></a> __aeabi_fmul
|
||||
<LI><a href="#[69]">>></a> __aeabi_cfcmple
|
||||
<LI><a href="#[4a]">>></a> __aeabi_ui2f
|
||||
<LI><a href="#[48]">>></a> __aeabi_i2f
|
||||
<LI><a href="#[61]">>></a> __aeabi_f2uiz
|
||||
<LI><a href="#[6e]">>></a> __aeabi_fdiv
|
||||
<LI><a href="#[6b]">>></a> __aeabi_fsub
|
||||
<LI><a href="#[6d]">>></a> __aeabi_fadd
|
||||
<LI><a href="#[62]">>></a> __aeabi_f2uiz
|
||||
<LI><a href="#[72]">>></a> __aeabi_cfcmpeq
|
||||
<LI><a href="#[6b]">>></a> __aeabi_fdiv
|
||||
<LI><a href="#[6c]">>></a> __aeabi_fsub
|
||||
<LI><a href="#[6e]">>></a> __aeabi_fadd
|
||||
<LI><a href="#[66]">>></a> __aeabi_f2d
|
||||
<LI><a href="#[6c]">>></a> __aeabi_cdcmple
|
||||
<LI><a href="#[71]">>></a> __aeabi_d2uiz
|
||||
<LI><a href="#[70]">>></a> __aeabi_dmul
|
||||
<LI><a href="#[6d]">>></a> __aeabi_cdcmple
|
||||
<LI><a href="#[71]">>></a> __aeabi_d2iz
|
||||
<LI><a href="#[67]">>></a> __aeabi_dadd
|
||||
<LI><a href="#[68]">>></a> __aeabi_d2f
|
||||
<LI><a href="#[6f]">>></a> Bubbling
|
||||
@ -836,11 +850,11 @@ Global Symbols
|
||||
<LI><a href="#[30]">>></a> RSSIScanHandler
|
||||
</UL>
|
||||
|
||||
<P><STRONG><a name="[73]"></a>ReadUART</STRONG> (Thumb, 10 bytes, Stack size 0 bytes, code_def.o(i.ReadUART))
|
||||
<P><STRONG><a name="[74]"></a>ReadUART</STRONG> (Thumb, 10 bytes, Stack size 0 bytes, code_def.o(i.ReadUART))
|
||||
<BR><BR>[Called By]<UL><LI><a href="#[2f]">>></a> UARTHandle
|
||||
</UL>
|
||||
|
||||
<P><STRONG><a name="[76]"></a>ReadUARTState</STRONG> (Thumb, 10 bytes, Stack size 0 bytes, code_def.o(i.ReadUARTState))
|
||||
<P><STRONG><a name="[77]"></a>ReadUARTState</STRONG> (Thumb, 10 bytes, Stack size 0 bytes, code_def.o(i.ReadUARTState))
|
||||
<BR><BR>[Called By]<UL><LI><a href="#[57]">>></a> WriteUART
|
||||
</UL>
|
||||
|
||||
@ -848,20 +862,21 @@ Global Symbols
|
||||
<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = SPI_RFD
|
||||
</UL>
|
||||
<BR>[Called By]<UL><LI><a href="#[54]">>></a> ChannelSelection_control
|
||||
<LI><a href="#[72]">>></a> SPIwrite
|
||||
<LI><a href="#[73]">>></a> SPIwrite
|
||||
</UL>
|
||||
|
||||
<P><STRONG><a name="[72]"></a>SPIwrite</STRONG> (Thumb, 64 bytes, Stack size 16 bytes, code_def.o(i.SPIwrite))
|
||||
<P><STRONG><a name="[73]"></a>SPIwrite</STRONG> (Thumb, 64 bytes, Stack size 16 bytes, code_def.o(i.SPIwrite))
|
||||
<BR><BR>[Stack]<UL><LI>Max Depth = 24<LI>Call Chain = SPIwrite ⇒ SPI_RFD
|
||||
</UL>
|
||||
<BR>[Calls]<UL><LI><a href="#[5d]">>></a> SPI_RFD
|
||||
</UL>
|
||||
<BR>[Called By]<UL><LI><a href="#[59]">>></a> singleFrequencyRSSI
|
||||
<LI><a href="#[63]">>></a> regWrite
|
||||
<LI><a href="#[5f]">>></a> regWrite
|
||||
</UL>
|
||||
|
||||
<P><STRONG><a name="[55]"></a>Start_FM_command</STRONG> (Thumb, 10 bytes, Stack size 0 bytes, code_def.o(i.Start_FM_command))
|
||||
<BR><BR>[Called By]<UL><LI><a href="#[54]">>></a> ChannelSelection_control
|
||||
<LI><a href="#[30]">>></a> RSSIScanHandler
|
||||
</UL>
|
||||
|
||||
<P><STRONG><a name="[58]"></a>Stop_FM_command</STRONG> (Thumb, 10 bytes, Stack size 0 bytes, code_def.o(i.Stop_FM_command))
|
||||
@ -887,10 +902,10 @@ Global Symbols
|
||||
</UL>
|
||||
|
||||
<P><STRONG><a name="[2f]"></a>UARTHandle</STRONG> (Thumb, 16 bytes, Stack size 8 bytes, code_def.o(i.UARTHandle))
|
||||
<BR><BR>[Stack]<UL><LI>Max Depth = 120<LI>Call Chain = UARTHandle ⇒ ChannelSelection_control ⇒ singleFrequencyRSSI ⇒ floor ⇒ __aeabi_cdrcmple
|
||||
<BR><BR>[Stack]<UL><LI>Max Depth = 128<LI>Call Chain = UARTHandle ⇒ ChannelSelection_control ⇒ regWrite ⇒ floor ⇒ __aeabi_cdrcmple
|
||||
</UL>
|
||||
<BR>[Calls]<UL><LI><a href="#[54]">>></a> ChannelSelection_control
|
||||
<LI><a href="#[73]">>></a> ReadUART
|
||||
<LI><a href="#[74]">>></a> ReadUART
|
||||
</UL>
|
||||
<BR>[Called By]<UL><LI><a href="#[6]">>></a> UART_Handler
|
||||
</UL>
|
||||
@ -898,9 +913,9 @@ Global Symbols
|
||||
<P><STRONG><a name="[56]"></a>UARTString</STRONG> (Thumb, 36 bytes, Stack size 16 bytes, code_def.o(i.UARTString))
|
||||
<BR><BR>[Stack]<UL><LI>Max Depth = 28<LI>Call Chain = UARTString ⇒ strlen
|
||||
</UL>
|
||||
<BR>[Calls]<UL><LI><a href="#[75]">>></a> strlen
|
||||
<BR>[Calls]<UL><LI><a href="#[76]">>></a> strlen
|
||||
<LI><a href="#[57]">>></a> WriteUART
|
||||
<LI><a href="#[74]">>></a> Delay
|
||||
<LI><a href="#[75]">>></a> Delay
|
||||
</UL>
|
||||
<BR>[Called By]<UL><LI><a href="#[54]">>></a> ChannelSelection_control
|
||||
<LI><a href="#[2e]">>></a> UARTFM_IQ_Dump_Done_Handler
|
||||
@ -927,29 +942,36 @@ Global Symbols
|
||||
<P><STRONG><a name="[57]"></a>WriteUART</STRONG> (Thumb, 22 bytes, Stack size 4 bytes, code_def.o(i.WriteUART))
|
||||
<BR><BR>[Stack]<UL><LI>Max Depth = 4<LI>Call Chain = WriteUART
|
||||
</UL>
|
||||
<BR>[Calls]<UL><LI><a href="#[76]">>></a> ReadUARTState
|
||||
<BR>[Calls]<UL><LI><a href="#[77]">>></a> ReadUARTState
|
||||
</UL>
|
||||
<BR>[Called By]<UL><LI><a href="#[54]">>></a> ChannelSelection_control
|
||||
<LI><a href="#[56]">>></a> UARTString
|
||||
</UL>
|
||||
|
||||
<P><STRONG><a name="[70]"></a>floor</STRONG> (Thumb, 180 bytes, Stack size 24 bytes, floor.o(i.floor))
|
||||
<P><STRONG><a name="[78]"></a>floor</STRONG> (Thumb, 180 bytes, Stack size 24 bytes, floor.o(i.floor))
|
||||
<BR><BR>[Stack]<UL><LI>Max Depth = 56<LI>Call Chain = floor ⇒ __aeabi_cdrcmple
|
||||
</UL>
|
||||
<BR>[Calls]<UL><LI><a href="#[77]">>></a> __aeabi_cdrcmple
|
||||
<LI><a href="#[78]">>></a> __aeabi_drsub
|
||||
<BR>[Calls]<UL><LI><a href="#[79]">>></a> __aeabi_cdrcmple
|
||||
<LI><a href="#[7a]">>></a> __aeabi_drsub
|
||||
<LI><a href="#[67]">>></a> __aeabi_dadd
|
||||
</UL>
|
||||
<BR>[Called By]<UL><LI><a href="#[59]">>></a> singleFrequencyRSSI
|
||||
<LI><a href="#[63]">>></a> regWrite
|
||||
<LI><a href="#[6a]">>></a> RSSIScanscreen
|
||||
<LI><a href="#[5f]">>></a> regWrite
|
||||
</UL>
|
||||
|
||||
<P><STRONG><a name="[7b]"></a>initialize</STRONG> (Thumb, 54 bytes, Stack size 48 bytes, channelselection_control.o(i.initialize))
|
||||
<BR><BR>[Stack]<UL><LI>Max Depth = 48<LI>Call Chain = initialize
|
||||
</UL>
|
||||
<BR>[Calls]<UL><LI><a href="#[7c]">>></a> __aeabi_memcpy4
|
||||
</UL>
|
||||
<BR>[Called By]<UL><LI><a href="#[27]">>></a> main
|
||||
</UL>
|
||||
|
||||
<P><STRONG><a name="[5e]"></a>int_to_str</STRONG> (Thumb, 170 bytes, Stack size 24 bytes, auxiliary.o(i.int_to_str))
|
||||
<BR><BR>[Stack]<UL><LI>Max Depth = 32 + In Cycle
|
||||
<LI>Call Chain = int_to_str ⇒ int_to_str (Cycle)
|
||||
</UL>
|
||||
<BR>[Calls]<UL><LI><a href="#[79]">>></a> __aeabi_idivmod
|
||||
<BR>[Calls]<UL><LI><a href="#[7d]">>></a> __aeabi_idivmod
|
||||
<LI><a href="#[5e]">>></a> int_to_str
|
||||
</UL>
|
||||
<BR>[Called By]<UL><LI><a href="#[54]">>></a> ChannelSelection_control
|
||||
@ -958,26 +980,31 @@ Global Symbols
|
||||
<LI><a href="#[5e]">>></a> int_to_str
|
||||
</UL>
|
||||
|
||||
<P><STRONG><a name="[27]"></a>main</STRONG> (Thumb, 16 bytes, Stack size 0 bytes, main.o(i.main))
|
||||
<BR><BR>[Calls]<UL><LI><a href="#[74]">>></a> Delay
|
||||
<P><STRONG><a name="[27]"></a>main</STRONG> (Thumb, 20 bytes, Stack size 0 bytes, main.o(i.main))
|
||||
<BR><BR>[Stack]<UL><LI>Max Depth = 48<LI>Call Chain = main ⇒ initialize
|
||||
</UL>
|
||||
<BR>[Calls]<UL><LI><a href="#[7b]">>></a> initialize
|
||||
<LI><a href="#[75]">>></a> Delay
|
||||
</UL>
|
||||
<BR>[Called By]<UL><LI><a href="#[26]">>></a> __rt_entry_main
|
||||
</UL>
|
||||
|
||||
<P><STRONG><a name="[63]"></a>regWrite</STRONG> (Thumb, 96 bytes, Stack size 48 bytes, code_def.o(i.regWrite))
|
||||
<P><STRONG><a name="[5f]"></a>regWrite</STRONG> (Thumb, 96 bytes, Stack size 48 bytes, code_def.o(i.regWrite))
|
||||
<BR><BR>[Stack]<UL><LI>Max Depth = 104<LI>Call Chain = regWrite ⇒ floor ⇒ __aeabi_cdrcmple
|
||||
</UL>
|
||||
<BR>[Calls]<UL><LI><a href="#[70]">>></a> floor
|
||||
<LI><a href="#[60]">>></a> __aeabi_fmul
|
||||
<BR>[Calls]<UL><LI><a href="#[78]">>></a> floor
|
||||
<LI><a href="#[61]">>></a> __aeabi_fmul
|
||||
<LI><a href="#[48]">>></a> __aeabi_i2f
|
||||
<LI><a href="#[7b]">>></a> __aeabi_f2iz
|
||||
<LI><a href="#[6e]">>></a> __aeabi_fdiv
|
||||
<LI><a href="#[6b]">>></a> __aeabi_fsub
|
||||
<LI><a href="#[7e]">>></a> __aeabi_f2iz
|
||||
<LI><a href="#[6b]">>></a> __aeabi_fdiv
|
||||
<LI><a href="#[6c]">>></a> __aeabi_fsub
|
||||
<LI><a href="#[66]">>></a> __aeabi_f2d
|
||||
<LI><a href="#[7a]">>></a> __aeabi_d2iz
|
||||
<LI><a href="#[72]">>></a> SPIwrite
|
||||
<LI><a href="#[71]">>></a> __aeabi_d2iz
|
||||
<LI><a href="#[73]">>></a> SPIwrite
|
||||
</UL>
|
||||
<BR>[Called By]<UL><LI><a href="#[3a]">>></a> KEY9
|
||||
<BR>[Called By]<UL><LI><a href="#[54]">>></a> ChannelSelection_control
|
||||
<LI><a href="#[30]">>></a> RSSIScanHandler
|
||||
<LI><a href="#[3a]">>></a> KEY9
|
||||
<LI><a href="#[39]">>></a> KEY8
|
||||
<LI><a href="#[38]">>></a> KEY7
|
||||
<LI><a href="#[37]">>></a> KEY6
|
||||
@ -998,48 +1025,58 @@ Global Symbols
|
||||
<P><STRONG><a name="[59]"></a>singleFrequencyRSSI</STRONG> (Thumb, 100 bytes, Stack size 40 bytes, code_def.o(i.singleFrequencyRSSI))
|
||||
<BR><BR>[Stack]<UL><LI>Max Depth = 96<LI>Call Chain = singleFrequencyRSSI ⇒ floor ⇒ __aeabi_cdrcmple
|
||||
</UL>
|
||||
<BR>[Calls]<UL><LI><a href="#[70]">>></a> floor
|
||||
<LI><a href="#[60]">>></a> __aeabi_fmul
|
||||
<BR>[Calls]<UL><LI><a href="#[78]">>></a> floor
|
||||
<LI><a href="#[61]">>></a> __aeabi_fmul
|
||||
<LI><a href="#[48]">>></a> __aeabi_i2f
|
||||
<LI><a href="#[7b]">>></a> __aeabi_f2iz
|
||||
<LI><a href="#[6e]">>></a> __aeabi_fdiv
|
||||
<LI><a href="#[6b]">>></a> __aeabi_fsub
|
||||
<LI><a href="#[7e]">>></a> __aeabi_f2iz
|
||||
<LI><a href="#[6b]">>></a> __aeabi_fdiv
|
||||
<LI><a href="#[6c]">>></a> __aeabi_fsub
|
||||
<LI><a href="#[66]">>></a> __aeabi_f2d
|
||||
<LI><a href="#[7a]">>></a> __aeabi_d2iz
|
||||
<LI><a href="#[72]">>></a> SPIwrite
|
||||
<LI><a href="#[71]">>></a> __aeabi_d2iz
|
||||
<LI><a href="#[73]">>></a> SPIwrite
|
||||
</UL>
|
||||
<BR>[Called By]<UL><LI><a href="#[54]">>></a> ChannelSelection_control
|
||||
<LI><a href="#[30]">>></a> RSSIScanHandler
|
||||
</UL>
|
||||
|
||||
<P><STRONG><a name="[6c]"></a>__aeabi_cdcmple</STRONG> (Thumb, 0 bytes, Stack size 24 bytes, dlef.o(x$fpl$dleqf))
|
||||
<P><STRONG><a name="[6d]"></a>__aeabi_cdcmple</STRONG> (Thumb, 0 bytes, Stack size 24 bytes, dlef.o(x$fpl$dleqf))
|
||||
<BR><BR>[Stack]<UL><LI>Max Depth = 24<LI>Call Chain = __aeabi_cdcmple
|
||||
</UL>
|
||||
<BR>[Called By]<UL><LI><a href="#[6a]">>></a> RSSIScanscreen
|
||||
</UL>
|
||||
|
||||
<P><STRONG><a name="[7c]"></a>_dcmple</STRONG> (Thumb, 94 bytes, Stack size 24 bytes, dlef.o(x$fpl$dleqf), UNUSED)
|
||||
<P><STRONG><a name="[7f]"></a>_dcmple</STRONG> (Thumb, 94 bytes, Stack size 24 bytes, dlef.o(x$fpl$dleqf), UNUSED)
|
||||
<BR><BR>[Calls]<UL><LI><a href="#[4b]">>></a> __fpl_dcmp_InfNaN
|
||||
</UL>
|
||||
|
||||
<P><STRONG><a name="[77]"></a>__aeabi_cdrcmple</STRONG> (Thumb, 0 bytes, Stack size 32 bytes, drlef.o(x$fpl$drleqf))
|
||||
<P><STRONG><a name="[79]"></a>__aeabi_cdrcmple</STRONG> (Thumb, 0 bytes, Stack size 32 bytes, drlef.o(x$fpl$drleqf))
|
||||
<BR><BR>[Stack]<UL><LI>Max Depth = 32<LI>Call Chain = __aeabi_cdrcmple
|
||||
</UL>
|
||||
<BR>[Called By]<UL><LI><a href="#[70]">>></a> floor
|
||||
<BR>[Called By]<UL><LI><a href="#[78]">>></a> floor
|
||||
</UL>
|
||||
|
||||
<P><STRONG><a name="[7d]"></a>_drcmple</STRONG> (Thumb, 100 bytes, Stack size 32 bytes, drlef.o(x$fpl$drleqf), UNUSED)
|
||||
<P><STRONG><a name="[80]"></a>_drcmple</STRONG> (Thumb, 100 bytes, Stack size 32 bytes, drlef.o(x$fpl$drleqf), UNUSED)
|
||||
<BR><BR>[Calls]<UL><LI><a href="#[4b]">>></a> __fpl_dcmp_InfNaN
|
||||
</UL>
|
||||
|
||||
<P><STRONG><a name="[6d]"></a>__aeabi_fadd</STRONG> (Thumb, 0 bytes, Stack size 16 bytes, faddsub.o(x$fpl$fadd))
|
||||
<P><STRONG><a name="[6e]"></a>__aeabi_fadd</STRONG> (Thumb, 0 bytes, Stack size 16 bytes, faddsub.o(x$fpl$fadd))
|
||||
<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = __aeabi_fadd
|
||||
</UL>
|
||||
<BR>[Called By]<UL><LI><a href="#[6a]">>></a> RSSIScanscreen
|
||||
</UL>
|
||||
|
||||
<P><STRONG><a name="[7e]"></a>_fadd</STRONG> (Thumb, 134 bytes, Stack size 16 bytes, faddsub.o(x$fpl$fadd), UNUSED)
|
||||
<BR><BR>[Calls]<UL><LI><a href="#[7f]">>></a> _fsub1
|
||||
<P><STRONG><a name="[81]"></a>_fadd</STRONG> (Thumb, 134 bytes, Stack size 16 bytes, faddsub.o(x$fpl$fadd), UNUSED)
|
||||
<BR><BR>[Calls]<UL><LI><a href="#[82]">>></a> _fsub1
|
||||
</UL>
|
||||
|
||||
<P><STRONG><a name="[72]"></a>__aeabi_cfcmpeq</STRONG> (Thumb, 0 bytes, Stack size 8 bytes, feqf.o(x$fpl$feqf))
|
||||
<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = __aeabi_cfcmpeq
|
||||
</UL>
|
||||
<BR>[Called By]<UL><LI><a href="#[6a]">>></a> RSSIScanscreen
|
||||
</UL>
|
||||
|
||||
<P><STRONG><a name="[83]"></a>_fcmpeq</STRONG> (Thumb, 78 bytes, Stack size 8 bytes, feqf.o(x$fpl$feqf), UNUSED)
|
||||
<BR><BR>[Calls]<UL><LI><a href="#[4e]">>></a> __fpl_fcmp_InfNaN
|
||||
</UL>
|
||||
|
||||
<P><STRONG><a name="[69]"></a>__aeabi_cfcmple</STRONG> (Thumb, 0 bytes, Stack size 8 bytes, flef.o(x$fpl$fleqf))
|
||||
@ -1049,31 +1086,31 @@ Global Symbols
|
||||
<LI><a href="#[30]">>></a> RSSIScanHandler
|
||||
</UL>
|
||||
|
||||
<P><STRONG><a name="[80]"></a>_fcmple</STRONG> (Thumb, 78 bytes, Stack size 8 bytes, flef.o(x$fpl$fleqf), UNUSED)
|
||||
<P><STRONG><a name="[84]"></a>_fcmple</STRONG> (Thumb, 78 bytes, Stack size 8 bytes, flef.o(x$fpl$fleqf), UNUSED)
|
||||
<BR><BR>[Calls]<UL><LI><a href="#[4e]">>></a> __fpl_fcmp_InfNaN
|
||||
</UL>
|
||||
|
||||
<P><STRONG><a name="[60]"></a>__aeabi_fmul</STRONG> (Thumb, 0 bytes, Stack size 16 bytes, fmul.o(x$fpl$fmul))
|
||||
<P><STRONG><a name="[61]"></a>__aeabi_fmul</STRONG> (Thumb, 0 bytes, Stack size 16 bytes, fmul.o(x$fpl$fmul))
|
||||
<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = __aeabi_fmul
|
||||
</UL>
|
||||
<BR>[Called By]<UL><LI><a href="#[59]">>></a> singleFrequencyRSSI
|
||||
<LI><a href="#[63]">>></a> regWrite
|
||||
<LI><a href="#[5f]">>></a> regWrite
|
||||
<LI><a href="#[6a]">>></a> RSSIScanscreen
|
||||
<LI><a href="#[5f]">>></a> Channel_control
|
||||
<LI><a href="#[60]">>></a> Channel_control
|
||||
</UL>
|
||||
|
||||
<P><STRONG><a name="[ba]"></a>_fmul</STRONG> (Thumb, 172 bytes, Stack size 16 bytes, fmul.o(x$fpl$fmul), UNUSED)
|
||||
<P><STRONG><a name="[bf]"></a>_fmul</STRONG> (Thumb, 172 bytes, Stack size 16 bytes, fmul.o(x$fpl$fmul), UNUSED)
|
||||
|
||||
<P><STRONG><a name="[6b]"></a>__aeabi_fsub</STRONG> (Thumb, 0 bytes, Stack size 16 bytes, faddsub.o(x$fpl$fsub))
|
||||
<P><STRONG><a name="[6c]"></a>__aeabi_fsub</STRONG> (Thumb, 0 bytes, Stack size 16 bytes, faddsub.o(x$fpl$fsub))
|
||||
<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = __aeabi_fsub
|
||||
</UL>
|
||||
<BR>[Called By]<UL><LI><a href="#[59]">>></a> singleFrequencyRSSI
|
||||
<LI><a href="#[63]">>></a> regWrite
|
||||
<LI><a href="#[5f]">>></a> regWrite
|
||||
<LI><a href="#[6a]">>></a> RSSIScanscreen
|
||||
</UL>
|
||||
|
||||
<P><STRONG><a name="[81]"></a>_fsub</STRONG> (Thumb, 204 bytes, Stack size 16 bytes, faddsub.o(x$fpl$fsub), UNUSED)
|
||||
<BR><BR>[Calls]<UL><LI><a href="#[82]">>></a> _fadd1
|
||||
<P><STRONG><a name="[85]"></a>_fsub</STRONG> (Thumb, 204 bytes, Stack size 16 bytes, faddsub.o(x$fpl$fsub), UNUSED)
|
||||
<BR><BR>[Calls]<UL><LI><a href="#[86]">>></a> _fadd1
|
||||
</UL>
|
||||
<P>
|
||||
<H3>
|
||||
@ -1091,12 +1128,12 @@ Local Symbols
|
||||
<LI><a href="#[41]">>></a> _dadd
|
||||
</UL>
|
||||
|
||||
<P><STRONG><a name="[82]"></a>_fadd1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, faddsub.o(x$fpl$fadd), UNUSED)
|
||||
<BR><BR>[Called By]<UL><LI><a href="#[81]">>></a> _fsub
|
||||
<P><STRONG><a name="[86]"></a>_fadd1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, faddsub.o(x$fpl$fadd), UNUSED)
|
||||
<BR><BR>[Called By]<UL><LI><a href="#[85]">>></a> _fsub
|
||||
</UL>
|
||||
|
||||
<P><STRONG><a name="[7f]"></a>_fsub1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, faddsub.o(x$fpl$fsub), UNUSED)
|
||||
<BR><BR>[Called By]<UL><LI><a href="#[7e]">>></a> _fadd
|
||||
<P><STRONG><a name="[82]"></a>_fsub1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, faddsub.o(x$fpl$fsub), UNUSED)
|
||||
<BR><BR>[Called By]<UL><LI><a href="#[81]">>></a> _fadd
|
||||
</UL>
|
||||
<P>
|
||||
<H3>
|
||||
|
||||
9505
keil/MMC.txt
9505
keil/MMC.txt
File diff suppressed because it is too large
Load Diff
File diff suppressed because one or more lines are too long
@ -117,6 +117,16 @@
|
||||
<pMon>BIN\CMSIS_AGDI.dll</pMon>
|
||||
</DebugOpt>
|
||||
<TargetDriverDllRegistry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>CMSIS_AGDI</Key>
|
||||
<Name>-X"Any" -UAny -O206 -S8 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN0</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>UL2CM3</Key>
|
||||
<Name>UL2CM3(-S0 -C0 -P0 -FC1000 -FD20000000</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>DLGUARM</Key>
|
||||
@ -137,16 +147,6 @@
|
||||
<Key>ARMDBGFLAGS</Key>
|
||||
<Name></Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>CMSIS_AGDI</Key>
|
||||
<Name>-X"Any" -UAny -O206 -S8 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO0 -FD20000000 -FC1000 -FN0</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>UL2CM3</Key>
|
||||
<Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000)</Name>
|
||||
</SetRegEntry>
|
||||
</TargetDriverDllRegistry>
|
||||
<Breakpoint/>
|
||||
<WatchWindow1>
|
||||
@ -180,6 +180,11 @@
|
||||
<WinNumber>1</WinNumber>
|
||||
<ItemText>channelcontrollist</ItemText>
|
||||
</Ww>
|
||||
<Ww>
|
||||
<count>6</count>
|
||||
<WinNumber>1</WinNumber>
|
||||
<ItemText>channelcontrollist</ItemText>
|
||||
</Ww>
|
||||
</WatchWindow1>
|
||||
<Tracepoint>
|
||||
<THDelay>0</THDelay>
|
||||
@ -255,7 +260,7 @@
|
||||
<GroupNumber>1</GroupNumber>
|
||||
<FileNumber>2</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\src\code_def.c</PathWithFileName>
|
||||
|
||||
@ -1,21 +1,21 @@
|
||||
Dependencies for Project 'MMC', Target 'Target 1': (DO NOT MODIFY !)
|
||||
CompilerVersion: 5060960::V5.06 update 7 (build 960)::.\ARMCC
|
||||
F (..\src\auxiliary.c)(0x6288D9F3)(-c --cpu Cortex-M0 -D__EVAL -g -O0 --apcs=interwork --split_sections
-IC:\Users\JefferyLi\AppData\Local\Arm\Packs\Keil\V2M-MPS2_CMx_BSP\1.8.0\Device\CMSDK_CM0\Include
-D__UVISION_VERSION="536" -DCMSDK_CM0
-o .\auxiliary.o --omf_browse .\auxiliary.crf --depend .\auxiliary.d)
|
||||
I (..\src\code_def.h)(0x62BB11B0)
|
||||
I (..\src\code_def.h)(0x62CC3F32)
|
||||
I (D:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x6025237E)
|
||||
I (D:\Keil_v5\ARM\ARMCC\include\string.h)(0x6025237E)
|
||||
F (..\src\code_def.c)(0x62BBD34E)(-c --cpu Cortex-M0 -D__EVAL -g -O0 --apcs=interwork --split_sections
-IC:\Users\JefferyLi\AppData\Local\Arm\Packs\Keil\V2M-MPS2_CMx_BSP\1.8.0\Device\CMSDK_CM0\Include
-D__UVISION_VERSION="536" -DCMSDK_CM0
-o .\code_def.o --omf_browse .\code_def.crf --depend .\code_def.d)
|
||||
I (..\src\code_def.h)(0x62BB11B0)
|
||||
F (..\src\code_def.c)(0x62D6C98D)(-c --cpu Cortex-M0 -D__EVAL -g -O0 --apcs=interwork --split_sections
-IC:\Users\JefferyLi\AppData\Local\Arm\Packs\Keil\V2M-MPS2_CMx_BSP\1.8.0\Device\CMSDK_CM0\Include
-D__UVISION_VERSION="536" -DCMSDK_CM0
-o .\code_def.o --omf_browse .\code_def.crf --depend .\code_def.d)
|
||||
I (..\src\code_def.h)(0x62CC3F32)
|
||||
I (D:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x6025237E)
|
||||
I (D:\Keil_v5\ARM\ARMCC\include\string.h)(0x6025237E)
|
||||
I (D:\Keil_v5\ARM\ARMCC\include\math.h)(0x60252378)
|
||||
F (..\src\code_def.h)(0x62BB11B0)()
|
||||
F (..\src\main.c)(0x62B85C66)(-c --cpu Cortex-M0 -D__EVAL -g -O0 --apcs=interwork --split_sections
-IC:\Users\JefferyLi\AppData\Local\Arm\Packs\Keil\V2M-MPS2_CMx_BSP\1.8.0\Device\CMSDK_CM0\Include
-D__UVISION_VERSION="536" -DCMSDK_CM0
-o .\main.o --omf_browse .\main.crf --depend .\main.d)
|
||||
I (..\src\code_def.h)(0x62BB11B0)
|
||||
F (..\src\code_def.h)(0x62CC3F32)()
|
||||
F (..\src\main.c)(0x62CC3EB3)(-c --cpu Cortex-M0 -D__EVAL -g -O0 --apcs=interwork --split_sections
-IC:\Users\JefferyLi\AppData\Local\Arm\Packs\Keil\V2M-MPS2_CMx_BSP\1.8.0\Device\CMSDK_CM0\Include
-D__UVISION_VERSION="536" -DCMSDK_CM0
-o .\main.o --omf_browse .\main.crf --depend .\main.d)
|
||||
I (..\src\code_def.h)(0x62CC3F32)
|
||||
I (D:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x6025237E)
|
||||
I (D:\Keil_v5\ARM\ARMCC\include\string.h)(0x6025237E)
|
||||
F (..\src\startup_CMSDK_CM0.s)(0x62B85B7A)(--cpu Cortex-M0 --pd "__EVAL SETA 1" -g --apcs=interwork
-IC:\Users\JefferyLi\AppData\Local\Arm\Packs\Keil\V2M-MPS2_CMx_BSP\1.8.0\Device\CMSDK_CM0\Include
--pd "__UVISION_VERSION SETA 536" --pd "CMSDK_CM0 SETA 1"
--list .\listings\startup_cmsdk_cm0.lst --xref -o .\startup_cmsdk_cm0.o --depend .\startup_cmsdk_cm0.d)
|
||||
F (..\src\channelSelection_control.c)(0x62BBB5B7)(-c --cpu Cortex-M0 -D__EVAL -g -O0 --apcs=interwork --split_sections
-IC:\Users\JefferyLi\AppData\Local\Arm\Packs\Keil\V2M-MPS2_CMx_BSP\1.8.0\Device\CMSDK_CM0\Include
-D__UVISION_VERSION="536" -DCMSDK_CM0
-o .\channelselection_control.o --omf_browse .\channelselection_control.crf --depend .\channelselection_control.d)
|
||||
I (..\src\code_def.h)(0x62BB11B0)
|
||||
F (..\src\startup_CMSDK_CM0.s)(0x62CE4475)(--cpu Cortex-M0 --pd "__EVAL SETA 1" -g --apcs=interwork
-IC:\Users\JefferyLi\AppData\Local\Arm\Packs\Keil\V2M-MPS2_CMx_BSP\1.8.0\Device\CMSDK_CM0\Include
--pd "__UVISION_VERSION SETA 536" --pd "CMSDK_CM0 SETA 1"
--list .\listings\startup_cmsdk_cm0.lst --xref -o .\startup_cmsdk_cm0.o --depend .\startup_cmsdk_cm0.d)
|
||||
F (..\src\channelSelection_control.c)(0x62D4FC03)(-c --cpu Cortex-M0 -D__EVAL -g -O0 --apcs=interwork --split_sections
-IC:\Users\JefferyLi\AppData\Local\Arm\Packs\Keil\V2M-MPS2_CMx_BSP\1.8.0\Device\CMSDK_CM0\Include
-D__UVISION_VERSION="536" -DCMSDK_CM0
-o .\channelselection_control.o --omf_browse .\channelselection_control.crf --depend .\channelselection_control.d)
|
||||
I (..\src\code_def.h)(0x62CC3F32)
|
||||
I (D:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x6025237E)
|
||||
I (D:\Keil_v5\ARM\ARMCC\include\string.h)(0x6025237E)
|
||||
|
||||
@ -2,14 +2,14 @@
|
||||
; *** Scatter-Loading Description File generated by uVision ***
|
||||
; *************************************************************
|
||||
|
||||
LR_IROM1 0x00000000 0x00100000 { ; load region size_region
|
||||
ER_IROM1 0x00000000 0x00100000 { ; load address = execution address
|
||||
LR_IROM1 0x00000000 0x00400000 { ; load region size_region
|
||||
ER_IROM1 0x00000000 0x00400000 { ; load address = execution address
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
.ANY (+XO)
|
||||
}
|
||||
RW_IRAM1 0x20000000 0x00100000 { ; RW data
|
||||
RW_IRAM1 0x20000000 0x00400000 { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
}
|
||||
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
BIN
keil/main.crf
BIN
keil/main.crf
Binary file not shown.
@ -1,8 +1,8 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<Project Version="1" Path="D:/Documents/MMC/project">
|
||||
<Project_Created_Time>2022-06-25 10:35:14</Project_Created_Time>
|
||||
<Project_Created_Time>2022-07-11 21:44:56</Project_Created_Time>
|
||||
<TD_Version>5.0.43066</TD_Version>
|
||||
<UCode>11111100</UCode>
|
||||
<UCode>11100000</UCode>
|
||||
<Name>MMC</Name>
|
||||
<HardWare>
|
||||
<Family>EG4</Family>
|
||||
@ -223,7 +223,7 @@
|
||||
<Attr Name="UsedInSyn" Val="true"/>
|
||||
<Attr Name="UsedInP&R" Val="true"/>
|
||||
<Attr Name="BelongTo" Val="design_1"/>
|
||||
<Attr Name="CompileOrder" Val="29"/>
|
||||
<Attr Name="CompileOrder" Val="28"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="../rtl/peripherals/KeyScan.v">
|
||||
@ -231,7 +231,7 @@
|
||||
<Attr Name="UsedInSyn" Val="true"/>
|
||||
<Attr Name="UsedInP&R" Val="true"/>
|
||||
<Attr Name="BelongTo" Val="design_1"/>
|
||||
<Attr Name="CompileOrder" Val="30"/>
|
||||
<Attr Name="CompileOrder" Val="29"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
</Verilog>
|
||||
@ -241,7 +241,7 @@
|
||||
<Attr Name="UsedInSyn" Val="true"/>
|
||||
<Attr Name="UsedInP&R" Val="true"/>
|
||||
<Attr Name="BelongTo" Val="design_1"/>
|
||||
<Attr Name="CompileOrder" Val="28"/>
|
||||
<Attr Name="CompileOrder" Val="27"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
</Header>
|
||||
@ -255,16 +255,6 @@
|
||||
</FileInfo>
|
||||
</File>
|
||||
</ADC_FILE>
|
||||
<CWC_FILE>
|
||||
<File Path="rssi.cwc">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedInSyn" Val="true"/>
|
||||
<Attr Name="UsedInP&R" Val="true"/>
|
||||
<Attr Name="BelongTo" Val="design_1"/>
|
||||
<Attr Name="CompileOrder" Val="27"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
</CWC_FILE>
|
||||
</Source_Files>
|
||||
<FileSets>
|
||||
<FileSet Name="constrain_1" Type="ConstrainFiles">
|
||||
@ -299,7 +289,7 @@
|
||||
<Configurations>
|
||||
</Configurations>
|
||||
<Project_Settings>
|
||||
<Step_Last_Change>2022-06-29 12:53:13.536</Step_Last_Change>
|
||||
<Step_Last_Change>2022-07-22 13:39:39.195</Step_Last_Change>
|
||||
<Current_Step>60</Current_Step>
|
||||
<Step_Status>true</Step_Status>
|
||||
</Project_Settings>
|
||||
|
||||
BIN
project/MMC.bit
BIN
project/MMC.bit
Binary file not shown.
@ -1,6 +1,6 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<All_Bram_Infos>
|
||||
<Ucode>11111100</Ucode>
|
||||
<Ucode>11100000</Ucode>
|
||||
<AL_PHY_BRAM>
|
||||
<INST_1>
|
||||
<rid>0X0004</rid>
|
||||
@ -995,192 +995,4 @@
|
||||
</sub_bid_info>
|
||||
</INST_32>
|
||||
</AL_PHY_BRAM>
|
||||
<AL_PHY_BRAM32K>
|
||||
<INST_1>
|
||||
<rid>0X0024</rid>
|
||||
<wid>0X0024</wid>
|
||||
<is_debuggable>y</is_debuggable>
|
||||
<is_initialize>n</is_initialize>
|
||||
<model_type>AL_PHY_BRAM32K</model_type>
|
||||
<name>auto_chipwatcher_0_logicbram_4096x48_sub_000000_000</name>
|
||||
<width_a>8</width_a>
|
||||
<width_b>8</width_b>
|
||||
<logic_name>auto_chipwatcher_0_logicbram</logic_name>
|
||||
<logic_width>48</logic_width>
|
||||
<logic_depth>4096</logic_depth>
|
||||
<sub_bid_info>
|
||||
<address_offset>0</address_offset>
|
||||
<data_offset>0</data_offset>
|
||||
<depth>4096</depth>
|
||||
<width>8</width>
|
||||
<num_section>1</num_section>
|
||||
<section_size>48</section_size>
|
||||
<width_per_section>8</width_per_section>
|
||||
<bytes_in_per_section>1</bytes_in_per_section>
|
||||
<working_mode>
|
||||
<address_step>1</address_step>
|
||||
<depth>4096</depth>
|
||||
<mode_type>113</mode_type>
|
||||
<width>8</width>
|
||||
<num_byte>1</num_byte>
|
||||
<ecc>0</ecc>
|
||||
</working_mode>
|
||||
</sub_bid_info>
|
||||
</INST_1>
|
||||
<INST_2>
|
||||
<rid>0X0028</rid>
|
||||
<wid>0X0028</wid>
|
||||
<is_debuggable>y</is_debuggable>
|
||||
<is_initialize>n</is_initialize>
|
||||
<model_type>AL_PHY_BRAM32K</model_type>
|
||||
<name>auto_chipwatcher_0_logicbram_4096x48_sub_000000_008</name>
|
||||
<width_a>8</width_a>
|
||||
<width_b>8</width_b>
|
||||
<logic_name>auto_chipwatcher_0_logicbram</logic_name>
|
||||
<logic_width>48</logic_width>
|
||||
<logic_depth>4096</logic_depth>
|
||||
<sub_bid_info>
|
||||
<address_offset>0</address_offset>
|
||||
<data_offset>8</data_offset>
|
||||
<depth>4096</depth>
|
||||
<width>8</width>
|
||||
<num_section>1</num_section>
|
||||
<section_size>48</section_size>
|
||||
<width_per_section>8</width_per_section>
|
||||
<bytes_in_per_section>1</bytes_in_per_section>
|
||||
<working_mode>
|
||||
<address_step>1</address_step>
|
||||
<depth>4096</depth>
|
||||
<mode_type>113</mode_type>
|
||||
<width>8</width>
|
||||
<num_byte>1</num_byte>
|
||||
<ecc>0</ecc>
|
||||
</working_mode>
|
||||
</sub_bid_info>
|
||||
</INST_2>
|
||||
<INST_3>
|
||||
<rid>0X002C</rid>
|
||||
<wid>0X002C</wid>
|
||||
<is_debuggable>y</is_debuggable>
|
||||
<is_initialize>n</is_initialize>
|
||||
<model_type>AL_PHY_BRAM32K</model_type>
|
||||
<name>auto_chipwatcher_0_logicbram_4096x48_sub_000000_016</name>
|
||||
<width_a>8</width_a>
|
||||
<width_b>8</width_b>
|
||||
<logic_name>auto_chipwatcher_0_logicbram</logic_name>
|
||||
<logic_width>48</logic_width>
|
||||
<logic_depth>4096</logic_depth>
|
||||
<sub_bid_info>
|
||||
<address_offset>0</address_offset>
|
||||
<data_offset>16</data_offset>
|
||||
<depth>4096</depth>
|
||||
<width>8</width>
|
||||
<num_section>1</num_section>
|
||||
<section_size>48</section_size>
|
||||
<width_per_section>8</width_per_section>
|
||||
<bytes_in_per_section>1</bytes_in_per_section>
|
||||
<working_mode>
|
||||
<address_step>1</address_step>
|
||||
<depth>4096</depth>
|
||||
<mode_type>113</mode_type>
|
||||
<width>8</width>
|
||||
<num_byte>1</num_byte>
|
||||
<ecc>0</ecc>
|
||||
</working_mode>
|
||||
</sub_bid_info>
|
||||
</INST_3>
|
||||
<INST_4>
|
||||
<rid>0X0030</rid>
|
||||
<wid>0X0030</wid>
|
||||
<is_debuggable>y</is_debuggable>
|
||||
<is_initialize>n</is_initialize>
|
||||
<model_type>AL_PHY_BRAM32K</model_type>
|
||||
<name>auto_chipwatcher_0_logicbram_4096x48_sub_000000_024</name>
|
||||
<width_a>8</width_a>
|
||||
<width_b>8</width_b>
|
||||
<logic_name>auto_chipwatcher_0_logicbram</logic_name>
|
||||
<logic_width>48</logic_width>
|
||||
<logic_depth>4096</logic_depth>
|
||||
<sub_bid_info>
|
||||
<address_offset>0</address_offset>
|
||||
<data_offset>24</data_offset>
|
||||
<depth>4096</depth>
|
||||
<width>8</width>
|
||||
<num_section>1</num_section>
|
||||
<section_size>48</section_size>
|
||||
<width_per_section>8</width_per_section>
|
||||
<bytes_in_per_section>1</bytes_in_per_section>
|
||||
<working_mode>
|
||||
<address_step>1</address_step>
|
||||
<depth>4096</depth>
|
||||
<mode_type>113</mode_type>
|
||||
<width>8</width>
|
||||
<num_byte>1</num_byte>
|
||||
<ecc>0</ecc>
|
||||
</working_mode>
|
||||
</sub_bid_info>
|
||||
</INST_4>
|
||||
<INST_5>
|
||||
<rid>0X0034</rid>
|
||||
<wid>0X0034</wid>
|
||||
<is_debuggable>y</is_debuggable>
|
||||
<is_initialize>n</is_initialize>
|
||||
<model_type>AL_PHY_BRAM32K</model_type>
|
||||
<name>auto_chipwatcher_0_logicbram_4096x48_sub_000000_032</name>
|
||||
<width_a>8</width_a>
|
||||
<width_b>8</width_b>
|
||||
<logic_name>auto_chipwatcher_0_logicbram</logic_name>
|
||||
<logic_width>48</logic_width>
|
||||
<logic_depth>4096</logic_depth>
|
||||
<sub_bid_info>
|
||||
<address_offset>0</address_offset>
|
||||
<data_offset>32</data_offset>
|
||||
<depth>4096</depth>
|
||||
<width>8</width>
|
||||
<num_section>1</num_section>
|
||||
<section_size>48</section_size>
|
||||
<width_per_section>8</width_per_section>
|
||||
<bytes_in_per_section>1</bytes_in_per_section>
|
||||
<working_mode>
|
||||
<address_step>1</address_step>
|
||||
<depth>4096</depth>
|
||||
<mode_type>113</mode_type>
|
||||
<width>8</width>
|
||||
<num_byte>1</num_byte>
|
||||
<ecc>0</ecc>
|
||||
</working_mode>
|
||||
</sub_bid_info>
|
||||
</INST_5>
|
||||
<INST_6>
|
||||
<rid>0X0038</rid>
|
||||
<wid>0X0038</wid>
|
||||
<is_debuggable>y</is_debuggable>
|
||||
<is_initialize>n</is_initialize>
|
||||
<model_type>AL_PHY_BRAM32K</model_type>
|
||||
<name>auto_chipwatcher_0_logicbram_4096x48_sub_000000_040</name>
|
||||
<width_a>8</width_a>
|
||||
<width_b>8</width_b>
|
||||
<logic_name>auto_chipwatcher_0_logicbram</logic_name>
|
||||
<logic_width>48</logic_width>
|
||||
<logic_depth>4096</logic_depth>
|
||||
<sub_bid_info>
|
||||
<address_offset>0</address_offset>
|
||||
<data_offset>40</data_offset>
|
||||
<depth>4096</depth>
|
||||
<width>8</width>
|
||||
<num_section>1</num_section>
|
||||
<section_size>48</section_size>
|
||||
<width_per_section>8</width_per_section>
|
||||
<bytes_in_per_section>1</bytes_in_per_section>
|
||||
<working_mode>
|
||||
<address_step>1</address_step>
|
||||
<depth>4096</depth>
|
||||
<mode_type>113</mode_type>
|
||||
<width>8</width>
|
||||
<num_byte>1</num_byte>
|
||||
<ecc>0</ecc>
|
||||
</working_mode>
|
||||
</sub_bid_info>
|
||||
</INST_6>
|
||||
</AL_PHY_BRAM32K>
|
||||
</All_Bram_Infos>
|
||||
|
||||
@ -8,24 +8,24 @@ IO Statistics
|
||||
#inout 1
|
||||
|
||||
Utilization Statistics
|
||||
#lut 17402 out of 19600 88.79%
|
||||
#reg 2517 out of 19600 12.84%
|
||||
#le 17610
|
||||
#lut only 15093 out of 17610 85.71%
|
||||
#reg only 208 out of 17610 1.18%
|
||||
#lut® 2309 out of 17610 13.11%
|
||||
#lut 17019 out of 19600 86.83%
|
||||
#reg 2074 out of 19600 10.58%
|
||||
#le 17133
|
||||
#lut only 15059 out of 17133 87.89%
|
||||
#reg only 114 out of 17133 0.67%
|
||||
#lut® 1960 out of 17133 11.44%
|
||||
#dsp 26 out of 29 89.66%
|
||||
#bram 32 out of 64 50.00%
|
||||
#bram9k 32
|
||||
#fifo9k 0
|
||||
#bram32k 6 out of 16 37.50%
|
||||
#bram32k 0 out of 16 0.00%
|
||||
#adc 1 out of 1 100.00%
|
||||
#pad 39 out of 186 20.97%
|
||||
#ireg 0
|
||||
#oreg 0
|
||||
#treg 0
|
||||
#pll 2 out of 4 50.00%
|
||||
#gclk 14 out of 16 87.50%
|
||||
#gclk 13 out of 16 81.25%
|
||||
|
||||
|
||||
Detailed IO Report
|
||||
@ -75,20 +75,20 @@ Report Hierarchy Area:
|
||||
+----------------------------------------------------------------------+
|
||||
|Instance |Module |le |lut |ripple |seq |bram |dsp |
|
||||
+----------------------------------------------------------------------+
|
||||
|top |CortexM0_SoC |17610 |16929 |473 |2517 |38 |26 |
|
||||
|top |CortexM0_SoC |17133 |16646 |373 |2074 |32 |26 |
|
||||
+----------------------------------------------------------------------+
|
||||
|
||||
|
||||
DataNet Average Fanout:
|
||||
|
||||
Index Fanout Nets
|
||||
#1 1 15657
|
||||
#2 2 10209
|
||||
#3 3 657
|
||||
#4 4 524
|
||||
#5 5-10 653
|
||||
#6 11-50 473
|
||||
#7 51-100 36
|
||||
#8 101-500 9
|
||||
#1 1 15257
|
||||
#2 2 10084
|
||||
#3 3 525
|
||||
#4 4 510
|
||||
#5 5-10 633
|
||||
#6 11-50 463
|
||||
#7 51-100 35
|
||||
#8 101-500 7
|
||||
#9 >500 18
|
||||
Average 3.09
|
||||
Average 3.11
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,407 +1,401 @@
|
||||
eagle_s20
|
||||
12 22 687 18594 896242330 9 0
|
||||
-13.826 0.304 CortexM0_SoC eagle_s20 BG256 Detail 8 1
|
||||
12 22 1021 17132 932245162 9 0
|
||||
-10.123 0.281 CortexM0_SoC eagle_s20 BG256 Detail 8 1
|
||||
clock: DeriveClock
|
||||
12 896242330 18594 4
|
||||
12 932245162 17132 4
|
||||
Setup check
|
||||
22 3
|
||||
Endpoint: FM_HW/FM_Dump_Data_IQ/reg0_b1|FM_HW/FM_Dump_Data_IQ/reg0_b4
|
||||
22 -13.826000 48997858 3
|
||||
Timing path: u_logic/P5vpw6_reg.clk->FM_HW/FM_Dump_Data_IQ/reg0_b1|FM_HW/FM_Dump_Data_IQ/reg0_b4
|
||||
u_logic/P5vpw6_reg.clk
|
||||
FM_HW/FM_Dump_Data_IQ/reg0_b1|FM_HW/FM_Dump_Data_IQ/reg0_b4
|
||||
24 -13.826000 19.884000 33.710000 24 24
|
||||
u_logic/P5vpw6 cw_top/wrapper_cwc_top/trigger_inst/HAS_BUS_DETECTOR$BUS_DETECTOR[0]$bus_detector_inst1/reg0_b7|cw_top/wrapper_cwc_top/trigger_inst/HAS_BUS_DETECTOR$BUS_DETECTOR[0]$bus_detector_inst1/reg0_b6.b[0]
|
||||
u_logic/Llaow6_lutinv u_logic/_al_u1671|u_logic/_al_u2549.a[0]
|
||||
u_logic/_al_u2549_o u_logic/_al_u2551|u_logic/Fpnpw6_reg.a[1]
|
||||
Endpoint: FM_HW/_al_u3394|FM_HW/FM_Dump_Data_IQ/reg0_b5
|
||||
22 -10.123000 48096076 3
|
||||
Timing path: u_logic/Wkipw6_reg|u_logic/U9ypw6_reg.clk->FM_HW/_al_u3394|FM_HW/FM_Dump_Data_IQ/reg0_b5
|
||||
u_logic/Wkipw6_reg|u_logic/U9ypw6_reg.clk
|
||||
FM_HW/_al_u3394|FM_HW/FM_Dump_Data_IQ/reg0_b5
|
||||
24 -10.123000 19.884000 30.007000 23 23
|
||||
u_logic/U9ypw6 u_logic/_al_u708|u_logic/_al_u2324.c[1]
|
||||
u_logic/Ya1ju6_lutinv u_logic/_al_u2451|u_logic/_al_u2549.b[0]
|
||||
u_logic/_al_u2549_o u_logic/_al_u2551|u_logic/R3vpw6_reg.a[1]
|
||||
u_logic/_al_u2551_o u_logic/_al_u2552.a[1]
|
||||
u_logic/_al_u2552_o u_logic/_al_u2556|u_logic/_al_u1730.a[1]
|
||||
u_logic/_al_u2556_o u_logic/_al_u2563|u_logic/_al_u159.a[1]
|
||||
u_logic/_al_u2563_o u_logic/_al_u2564|u_logic/_al_u4431.d[1]
|
||||
u_logic/_al_u2564_o u_logic/_al_u2565|u_logic/_al_u2892.d[1]
|
||||
u_logic/_al_u2565_o u_logic/_al_u2566|u_logic/_al_u2882.d[1]
|
||||
u_logic/_al_u2566_o u_logic/_al_u2641|u_logic/_al_u2759.d[1]
|
||||
u_logic/Vtzhu6 u_logic/_al_u2643.d[0]
|
||||
u_logic/_al_u2552_o u_logic/_al_u2556|u_logic/_al_u2555.a[1]
|
||||
u_logic/_al_u2556_o u_logic/_al_u2563|u_logic/_al_u641.a[1]
|
||||
u_logic/_al_u2563_o u_logic/_al_u2564|u_logic/_al_u411.d[1]
|
||||
u_logic/_al_u2564_o u_logic/_al_u2565|u_logic/_al_u2847.d[1]
|
||||
u_logic/_al_u2565_o u_logic/_al_u2566|u_logic/J0iax6_reg.d[1]
|
||||
u_logic/_al_u2566_o u_logic/_al_u2641|u_logic/_al_u4457.d[1]
|
||||
u_logic/Vtzhu6 u_logic/_al_u2643|u_logic/_al_u954.d[1]
|
||||
u_logic/R0ghu6 u_logic/add2/ucin_al_u4809.b[0]
|
||||
u_logic/add2/c3 u_logic/add2/u3_al_u4810.fci
|
||||
u_logic/N5fpw6[4] u_logic/_al_u4753|u_logic/_al_u2604.c[0]
|
||||
u_logic/_al_u2604_o u_logic/_al_u2605|u_logic/Ibqpw6_reg.d[1]
|
||||
u_logic/_al_u2605_o u_logic/_al_u3990|RAMDATA_Interface/reg0_b3.b[0]
|
||||
HADDR[5] FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_r478_c1_m0.d[0]
|
||||
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_i478_004 FM_HW/_al_u3089|FM_HW/_al_u3091.b[0]
|
||||
FM_HW/_al_u3091_o FM_HW/_al_u3090|FM_HW/_al_u3092.c[0]
|
||||
FM_HW/_al_u3092_o FM_HW/_al_u2670|FM_HW/_al_u3093.b[0]
|
||||
FM_HW/_al_u3093_o FM_HW/_al_u1562|FM_HW/_al_u3094.c[0]
|
||||
FM_HW/_al_u3094_o FM_HW/_al_u3115.a[1]
|
||||
FM_HW/_al_u3115_o FM_HW/_al_u1583|FM_HW/FM_Demodulation/reg5_b57.a[0]
|
||||
FM_HW/_al_u3159_o FM_HW/FM_Dump_Data_IQ/reg0_b1|FM_HW/FM_Dump_Data_IQ/reg0_b4.a[0]
|
||||
u_logic/N5fpw6[7] u_logic/_al_u2517|u_logic/_al_u2533.d[1]
|
||||
u_logic/_al_u2517_o u_logic/_al_u2518|u_logic/Vpgbx6_reg.d[1]
|
||||
u_logic/_al_u2518_o RAMDATA_Interface/reg0_b6|RAMDATA_Interface/reg0_b4.b[1]
|
||||
HADDR[8] FM_HW/_al_u3810|FM_HW/_al_u668.c[0]
|
||||
FM_HW/_al_u668_o FM_HW/_al_u2914|FM_HW/_al_u2383.b[1]
|
||||
FM_HW/_al_u2914_o FM_HW/_al_u2919.a[1]
|
||||
FM_HW/_al_u2919_o FM_HW/_al_u2387|FM_HW/_al_u2923.b[0]
|
||||
FM_HW/_al_u2923_o FM_HW/_al_u2944.a[1]
|
||||
FM_HW/_al_u2944_o scan_unit/reg2_b15|scan_unit/reg2_b29.a[1]
|
||||
FM_HW/_al_u2987_o FM_HW/_al_u3394|FM_HW/FM_Dump_Data_IQ/reg0_b5.b[0]
|
||||
|
||||
Timing path: u_logic/P5vpw6_reg.clk->FM_HW/FM_Dump_Data_IQ/reg0_b1|FM_HW/FM_Dump_Data_IQ/reg0_b4
|
||||
u_logic/P5vpw6_reg.clk
|
||||
FM_HW/FM_Dump_Data_IQ/reg0_b1|FM_HW/FM_Dump_Data_IQ/reg0_b4
|
||||
97 -13.826000 19.884000 33.710000 24 24
|
||||
u_logic/P5vpw6 cw_top/wrapper_cwc_top/trigger_inst/HAS_BUS_DETECTOR$BUS_DETECTOR[0]$bus_detector_inst1/reg0_b7|cw_top/wrapper_cwc_top/trigger_inst/HAS_BUS_DETECTOR$BUS_DETECTOR[0]$bus_detector_inst1/reg0_b6.b[0]
|
||||
u_logic/Llaow6_lutinv u_logic/_al_u1671|u_logic/_al_u2549.a[0]
|
||||
u_logic/_al_u2549_o u_logic/_al_u2551|u_logic/Fpnpw6_reg.a[1]
|
||||
u_logic/_al_u2551_o u_logic/_al_u2552.a[0]
|
||||
u_logic/_al_u2552_o u_logic/_al_u2556|u_logic/_al_u1730.a[1]
|
||||
u_logic/_al_u2556_o u_logic/_al_u2563|u_logic/_al_u159.a[1]
|
||||
u_logic/_al_u2563_o u_logic/_al_u2564|u_logic/_al_u4431.d[1]
|
||||
u_logic/_al_u2564_o u_logic/_al_u2565|u_logic/_al_u2892.d[1]
|
||||
u_logic/_al_u2565_o u_logic/_al_u2566|u_logic/_al_u2882.d[1]
|
||||
u_logic/_al_u2566_o u_logic/_al_u2641|u_logic/_al_u2759.d[1]
|
||||
u_logic/Vtzhu6 u_logic/_al_u2643.d[0]
|
||||
u_logic/R0ghu6 u_logic/add2/ucin_al_u4809.b[0]
|
||||
u_logic/add2/c3 u_logic/add2/u3_al_u4810.fci
|
||||
u_logic/N5fpw6[4] u_logic/_al_u4753|u_logic/_al_u2604.c[0]
|
||||
u_logic/_al_u2604_o u_logic/_al_u2605|u_logic/Ibqpw6_reg.d[1]
|
||||
u_logic/_al_u2605_o u_logic/_al_u3990|RAMDATA_Interface/reg0_b3.b[0]
|
||||
HADDR[5] FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_r478_c1_m0.d[0]
|
||||
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_i478_004 FM_HW/_al_u3089|FM_HW/_al_u3091.b[0]
|
||||
FM_HW/_al_u3091_o FM_HW/_al_u3090|FM_HW/_al_u3092.c[0]
|
||||
FM_HW/_al_u3092_o FM_HW/_al_u2670|FM_HW/_al_u3093.b[0]
|
||||
FM_HW/_al_u3093_o FM_HW/_al_u1562|FM_HW/_al_u3094.c[0]
|
||||
FM_HW/_al_u3094_o FM_HW/_al_u3115.a[1]
|
||||
FM_HW/_al_u3115_o FM_HW/_al_u1583|FM_HW/FM_Demodulation/reg5_b57.a[0]
|
||||
FM_HW/_al_u3159_o FM_HW/FM_Dump_Data_IQ/reg0_b1|FM_HW/FM_Dump_Data_IQ/reg0_b4.a[0]
|
||||
|
||||
Timing path: u_logic/P5vpw6_reg.clk->FM_HW/FM_Dump_Data_IQ/reg0_b1|FM_HW/FM_Dump_Data_IQ/reg0_b4
|
||||
u_logic/P5vpw6_reg.clk
|
||||
FM_HW/FM_Dump_Data_IQ/reg0_b1|FM_HW/FM_Dump_Data_IQ/reg0_b4
|
||||
170 -13.826000 19.884000 33.710000 24 24
|
||||
u_logic/P5vpw6 cw_top/wrapper_cwc_top/trigger_inst/HAS_BUS_DETECTOR$BUS_DETECTOR[0]$bus_detector_inst1/reg0_b7|cw_top/wrapper_cwc_top/trigger_inst/HAS_BUS_DETECTOR$BUS_DETECTOR[0]$bus_detector_inst1/reg0_b6.b[0]
|
||||
u_logic/Llaow6_lutinv u_logic/_al_u1671|u_logic/_al_u2549.a[0]
|
||||
u_logic/_al_u2549_o u_logic/_al_u2551|u_logic/Fpnpw6_reg.a[1]
|
||||
Timing path: u_logic/Wkipw6_reg|u_logic/U9ypw6_reg.clk->FM_HW/_al_u3394|FM_HW/FM_Dump_Data_IQ/reg0_b5
|
||||
u_logic/Wkipw6_reg|u_logic/U9ypw6_reg.clk
|
||||
FM_HW/_al_u3394|FM_HW/FM_Dump_Data_IQ/reg0_b5
|
||||
95 -10.123000 19.884000 30.007000 23 23
|
||||
u_logic/U9ypw6 u_logic/_al_u708|u_logic/_al_u2324.c[1]
|
||||
u_logic/Ya1ju6_lutinv u_logic/_al_u2451|u_logic/_al_u2549.b[0]
|
||||
u_logic/_al_u2549_o u_logic/_al_u2551|u_logic/R3vpw6_reg.a[1]
|
||||
u_logic/_al_u2551_o u_logic/_al_u2552.a[1]
|
||||
u_logic/_al_u2552_o u_logic/_al_u2556|u_logic/_al_u1730.a[1]
|
||||
u_logic/_al_u2556_o u_logic/_al_u2563|u_logic/_al_u159.a[1]
|
||||
u_logic/_al_u2563_o u_logic/_al_u2564|u_logic/_al_u4431.d[1]
|
||||
u_logic/_al_u2564_o u_logic/_al_u2565|u_logic/_al_u2892.d[1]
|
||||
u_logic/_al_u2565_o u_logic/_al_u2566|u_logic/_al_u2882.d[1]
|
||||
u_logic/_al_u2566_o u_logic/_al_u2641|u_logic/_al_u2759.d[1]
|
||||
u_logic/Vtzhu6 u_logic/_al_u2643.d[0]
|
||||
u_logic/_al_u2552_o u_logic/_al_u2556|u_logic/_al_u2555.a[1]
|
||||
u_logic/_al_u2556_o u_logic/_al_u2563|u_logic/_al_u641.a[1]
|
||||
u_logic/_al_u2563_o u_logic/_al_u2564|u_logic/_al_u411.d[1]
|
||||
u_logic/_al_u2564_o u_logic/_al_u2565|u_logic/_al_u2847.d[1]
|
||||
u_logic/_al_u2565_o u_logic/_al_u2566|u_logic/J0iax6_reg.d[1]
|
||||
u_logic/_al_u2566_o u_logic/_al_u2641|u_logic/_al_u4457.d[1]
|
||||
u_logic/Vtzhu6 u_logic/_al_u2643|u_logic/_al_u954.d[1]
|
||||
u_logic/R0ghu6 u_logic/add2/ucin_al_u4809.b[0]
|
||||
u_logic/add2/c3 u_logic/add2/u3_al_u4810.fci
|
||||
u_logic/N5fpw6[4] u_logic/_al_u4753|u_logic/_al_u2604.c[0]
|
||||
u_logic/_al_u2604_o u_logic/_al_u2605|u_logic/Ibqpw6_reg.d[1]
|
||||
u_logic/_al_u2605_o u_logic/_al_u3990|RAMDATA_Interface/reg0_b3.b[0]
|
||||
HADDR[5] FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_r478_c1_m0.d[0]
|
||||
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_i478_004 FM_HW/_al_u3089|FM_HW/_al_u3091.b[0]
|
||||
FM_HW/_al_u3091_o FM_HW/_al_u3090|FM_HW/_al_u3092.c[0]
|
||||
FM_HW/_al_u3092_o FM_HW/_al_u2670|FM_HW/_al_u3093.b[0]
|
||||
FM_HW/_al_u3093_o FM_HW/_al_u1562|FM_HW/_al_u3094.c[0]
|
||||
FM_HW/_al_u3094_o FM_HW/_al_u3115.a[0]
|
||||
FM_HW/_al_u3115_o FM_HW/_al_u1583|FM_HW/FM_Demodulation/reg5_b57.a[0]
|
||||
FM_HW/_al_u3159_o FM_HW/FM_Dump_Data_IQ/reg0_b1|FM_HW/FM_Dump_Data_IQ/reg0_b4.a[0]
|
||||
u_logic/N5fpw6[7] u_logic/_al_u2517|u_logic/_al_u2533.d[1]
|
||||
u_logic/_al_u2517_o u_logic/_al_u2518|u_logic/Vpgbx6_reg.d[1]
|
||||
u_logic/_al_u2518_o RAMDATA_Interface/reg0_b6|RAMDATA_Interface/reg0_b4.b[1]
|
||||
HADDR[8] FM_HW/_al_u3810|FM_HW/_al_u668.c[0]
|
||||
FM_HW/_al_u668_o FM_HW/_al_u2914|FM_HW/_al_u2383.b[1]
|
||||
FM_HW/_al_u2914_o FM_HW/_al_u2919.a[0]
|
||||
FM_HW/_al_u2919_o FM_HW/_al_u2387|FM_HW/_al_u2923.b[0]
|
||||
FM_HW/_al_u2923_o FM_HW/_al_u2944.a[1]
|
||||
FM_HW/_al_u2944_o scan_unit/reg2_b15|scan_unit/reg2_b29.a[1]
|
||||
FM_HW/_al_u2987_o FM_HW/_al_u3394|FM_HW/FM_Dump_Data_IQ/reg0_b5.b[0]
|
||||
|
||||
|
||||
Endpoint: FM_HW/_al_u3650|FM_HW/FM_Dump_Data_IQ/reg0_b7
|
||||
243 -13.737000 33724860 3
|
||||
Timing path: u_logic/P5vpw6_reg.clk->FM_HW/_al_u3650|FM_HW/FM_Dump_Data_IQ/reg0_b7
|
||||
u_logic/P5vpw6_reg.clk
|
||||
FM_HW/_al_u3650|FM_HW/FM_Dump_Data_IQ/reg0_b7
|
||||
245 -13.737000 19.884000 33.621000 24 24
|
||||
u_logic/P5vpw6 cw_top/wrapper_cwc_top/trigger_inst/HAS_BUS_DETECTOR$BUS_DETECTOR[0]$bus_detector_inst1/reg0_b7|cw_top/wrapper_cwc_top/trigger_inst/HAS_BUS_DETECTOR$BUS_DETECTOR[0]$bus_detector_inst1/reg0_b6.b[0]
|
||||
u_logic/Llaow6_lutinv u_logic/_al_u1671|u_logic/_al_u2549.a[0]
|
||||
u_logic/_al_u2549_o u_logic/_al_u2551|u_logic/Fpnpw6_reg.a[1]
|
||||
Timing path: u_logic/Wkipw6_reg|u_logic/U9ypw6_reg.clk->FM_HW/_al_u3394|FM_HW/FM_Dump_Data_IQ/reg0_b5
|
||||
u_logic/Wkipw6_reg|u_logic/U9ypw6_reg.clk
|
||||
FM_HW/_al_u3394|FM_HW/FM_Dump_Data_IQ/reg0_b5
|
||||
166 -10.123000 19.884000 30.007000 23 23
|
||||
u_logic/U9ypw6 u_logic/_al_u708|u_logic/_al_u2324.c[1]
|
||||
u_logic/Ya1ju6_lutinv u_logic/_al_u2451|u_logic/_al_u2549.b[0]
|
||||
u_logic/_al_u2549_o u_logic/_al_u2551|u_logic/R3vpw6_reg.a[1]
|
||||
u_logic/_al_u2551_o u_logic/_al_u2552.a[1]
|
||||
u_logic/_al_u2552_o u_logic/_al_u2556|u_logic/_al_u1730.a[1]
|
||||
u_logic/_al_u2556_o u_logic/_al_u2563|u_logic/_al_u159.a[1]
|
||||
u_logic/_al_u2563_o u_logic/_al_u2564|u_logic/_al_u4431.d[1]
|
||||
u_logic/_al_u2564_o u_logic/_al_u2565|u_logic/_al_u2892.d[1]
|
||||
u_logic/_al_u2565_o u_logic/_al_u2566|u_logic/_al_u2882.d[1]
|
||||
u_logic/_al_u2566_o u_logic/_al_u2641|u_logic/_al_u2759.d[1]
|
||||
u_logic/Vtzhu6 u_logic/_al_u2643.d[0]
|
||||
u_logic/_al_u2552_o u_logic/_al_u2556|u_logic/_al_u2555.a[1]
|
||||
u_logic/_al_u2556_o u_logic/_al_u2563|u_logic/_al_u641.a[1]
|
||||
u_logic/_al_u2563_o u_logic/_al_u2564|u_logic/_al_u411.d[1]
|
||||
u_logic/_al_u2564_o u_logic/_al_u2565|u_logic/_al_u2847.d[1]
|
||||
u_logic/_al_u2565_o u_logic/_al_u2566|u_logic/J0iax6_reg.d[1]
|
||||
u_logic/_al_u2566_o u_logic/_al_u2641|u_logic/_al_u4457.d[1]
|
||||
u_logic/Vtzhu6 u_logic/_al_u2643|u_logic/_al_u954.d[1]
|
||||
u_logic/R0ghu6 u_logic/add2/ucin_al_u4809.b[0]
|
||||
u_logic/add2/c3 u_logic/add2/u3_al_u4810.fci
|
||||
u_logic/N5fpw6[4] u_logic/_al_u4753|u_logic/_al_u2604.c[0]
|
||||
u_logic/_al_u2604_o u_logic/_al_u2605|u_logic/Ibqpw6_reg.d[1]
|
||||
u_logic/_al_u2605_o u_logic/_al_u3990|RAMDATA_Interface/reg0_b3.b[0]
|
||||
HADDR[5] FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_r399_c1_m1.d[1]
|
||||
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_i399_007 FM_HW/_al_u2331|FM_HW/_al_u2330.b[0]
|
||||
FM_HW/_al_u2330_o FM_HW/_al_u2331|FM_HW/_al_u2330.c[1]
|
||||
FM_HW/_al_u2331_o FM_HW/FM_Demodulation/reg5_b19|FM_HW/FM_Demodulation/reg5_b18.b[1]
|
||||
FM_HW/_al_u2334_o FM_HW/_al_u2338.b[1]
|
||||
FM_HW/_al_u2338_o FM_HW/FM_Demodulation/reg5_b53|FM_HW/FM_Demodulation/reg5_b59.b[1]
|
||||
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_mux_b7/B6_3 FM_HW/_al_u2380|FM_HW/_al_u850.b[1]
|
||||
FM_HW/_al_u2380_o FM_HW/_al_u3650|FM_HW/FM_Dump_Data_IQ/reg0_b7.c[0]
|
||||
u_logic/N5fpw6[7] u_logic/_al_u2517|u_logic/_al_u2533.d[1]
|
||||
u_logic/_al_u2517_o u_logic/_al_u2518|u_logic/Vpgbx6_reg.d[1]
|
||||
u_logic/_al_u2518_o RAMDATA_Interface/reg0_b6|RAMDATA_Interface/reg0_b4.b[1]
|
||||
HADDR[8] FM_HW/_al_u3810|FM_HW/_al_u668.c[0]
|
||||
FM_HW/_al_u668_o FM_HW/_al_u2914|FM_HW/_al_u2383.b[1]
|
||||
FM_HW/_al_u2914_o FM_HW/_al_u2919.a[1]
|
||||
FM_HW/_al_u2919_o FM_HW/_al_u2387|FM_HW/_al_u2923.b[0]
|
||||
FM_HW/_al_u2923_o FM_HW/_al_u2944.a[0]
|
||||
FM_HW/_al_u2944_o scan_unit/reg2_b15|scan_unit/reg2_b29.a[1]
|
||||
FM_HW/_al_u2987_o FM_HW/_al_u3394|FM_HW/FM_Dump_Data_IQ/reg0_b5.b[0]
|
||||
|
||||
Timing path: u_logic/P5vpw6_reg.clk->FM_HW/_al_u3650|FM_HW/FM_Dump_Data_IQ/reg0_b7
|
||||
u_logic/P5vpw6_reg.clk
|
||||
FM_HW/_al_u3650|FM_HW/FM_Dump_Data_IQ/reg0_b7
|
||||
318 -13.737000 19.884000 33.621000 24 24
|
||||
u_logic/P5vpw6 cw_top/wrapper_cwc_top/trigger_inst/HAS_BUS_DETECTOR$BUS_DETECTOR[0]$bus_detector_inst1/reg0_b7|cw_top/wrapper_cwc_top/trigger_inst/HAS_BUS_DETECTOR$BUS_DETECTOR[0]$bus_detector_inst1/reg0_b6.b[0]
|
||||
u_logic/Llaow6_lutinv u_logic/_al_u1671|u_logic/_al_u2549.a[0]
|
||||
u_logic/_al_u2549_o u_logic/_al_u2551|u_logic/Fpnpw6_reg.a[1]
|
||||
u_logic/_al_u2551_o u_logic/_al_u2552.a[0]
|
||||
u_logic/_al_u2552_o u_logic/_al_u2556|u_logic/_al_u1730.a[1]
|
||||
u_logic/_al_u2556_o u_logic/_al_u2563|u_logic/_al_u159.a[1]
|
||||
u_logic/_al_u2563_o u_logic/_al_u2564|u_logic/_al_u4431.d[1]
|
||||
u_logic/_al_u2564_o u_logic/_al_u2565|u_logic/_al_u2892.d[1]
|
||||
u_logic/_al_u2565_o u_logic/_al_u2566|u_logic/_al_u2882.d[1]
|
||||
u_logic/_al_u2566_o u_logic/_al_u2641|u_logic/_al_u2759.d[1]
|
||||
u_logic/Vtzhu6 u_logic/_al_u2643.d[0]
|
||||
u_logic/R0ghu6 u_logic/add2/ucin_al_u4809.b[0]
|
||||
u_logic/add2/c3 u_logic/add2/u3_al_u4810.fci
|
||||
u_logic/N5fpw6[4] u_logic/_al_u4753|u_logic/_al_u2604.c[0]
|
||||
u_logic/_al_u2604_o u_logic/_al_u2605|u_logic/Ibqpw6_reg.d[1]
|
||||
u_logic/_al_u2605_o u_logic/_al_u3990|RAMDATA_Interface/reg0_b3.b[0]
|
||||
HADDR[5] FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_r399_c1_m1.d[1]
|
||||
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_i399_007 FM_HW/_al_u2331|FM_HW/_al_u2330.b[0]
|
||||
FM_HW/_al_u2330_o FM_HW/_al_u2331|FM_HW/_al_u2330.c[1]
|
||||
FM_HW/_al_u2331_o FM_HW/FM_Demodulation/reg5_b19|FM_HW/FM_Demodulation/reg5_b18.b[1]
|
||||
FM_HW/_al_u2334_o FM_HW/_al_u2338.b[1]
|
||||
FM_HW/_al_u2338_o FM_HW/FM_Demodulation/reg5_b53|FM_HW/FM_Demodulation/reg5_b59.b[1]
|
||||
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_mux_b7/B6_3 FM_HW/_al_u2380|FM_HW/_al_u850.b[1]
|
||||
FM_HW/_al_u2380_o FM_HW/_al_u3650|FM_HW/FM_Dump_Data_IQ/reg0_b7.c[0]
|
||||
|
||||
Timing path: u_logic/P5vpw6_reg.clk->FM_HW/_al_u3650|FM_HW/FM_Dump_Data_IQ/reg0_b7
|
||||
u_logic/P5vpw6_reg.clk
|
||||
FM_HW/_al_u3650|FM_HW/FM_Dump_Data_IQ/reg0_b7
|
||||
391 -13.737000 19.884000 33.621000 24 24
|
||||
u_logic/P5vpw6 cw_top/wrapper_cwc_top/trigger_inst/HAS_BUS_DETECTOR$BUS_DETECTOR[0]$bus_detector_inst1/reg0_b7|cw_top/wrapper_cwc_top/trigger_inst/HAS_BUS_DETECTOR$BUS_DETECTOR[0]$bus_detector_inst1/reg0_b6.b[0]
|
||||
u_logic/Llaow6_lutinv u_logic/_al_u1671|u_logic/_al_u2549.a[0]
|
||||
u_logic/_al_u2549_o u_logic/_al_u2551|u_logic/Fpnpw6_reg.a[1]
|
||||
Endpoint: FM_HW/_al_u3595|FM_HW/FM_Dump_Data_IQ/reg0_b7
|
||||
237 -9.884000 41516211 3
|
||||
Timing path: u_logic/Wkipw6_reg|u_logic/U9ypw6_reg.clk->FM_HW/_al_u3595|FM_HW/FM_Dump_Data_IQ/reg0_b7
|
||||
u_logic/Wkipw6_reg|u_logic/U9ypw6_reg.clk
|
||||
FM_HW/_al_u3595|FM_HW/FM_Dump_Data_IQ/reg0_b7
|
||||
239 -9.884000 19.884000 29.768000 23 23
|
||||
u_logic/U9ypw6 u_logic/_al_u708|u_logic/_al_u2324.c[1]
|
||||
u_logic/Ya1ju6_lutinv u_logic/_al_u2451|u_logic/_al_u2549.b[0]
|
||||
u_logic/_al_u2549_o u_logic/_al_u2551|u_logic/R3vpw6_reg.a[1]
|
||||
u_logic/_al_u2551_o u_logic/_al_u2552.a[1]
|
||||
u_logic/_al_u2552_o u_logic/_al_u2556|u_logic/_al_u1730.a[1]
|
||||
u_logic/_al_u2556_o u_logic/_al_u2563|u_logic/_al_u159.a[1]
|
||||
u_logic/_al_u2563_o u_logic/_al_u2564|u_logic/_al_u4431.d[1]
|
||||
u_logic/_al_u2564_o u_logic/_al_u2565|u_logic/_al_u2892.d[1]
|
||||
u_logic/_al_u2565_o u_logic/_al_u2566|u_logic/_al_u2882.d[1]
|
||||
u_logic/_al_u2566_o u_logic/_al_u2641|u_logic/_al_u2759.d[1]
|
||||
u_logic/Vtzhu6 u_logic/_al_u2643.d[0]
|
||||
u_logic/_al_u2552_o u_logic/_al_u2556|u_logic/_al_u2555.a[1]
|
||||
u_logic/_al_u2556_o u_logic/_al_u2563|u_logic/_al_u641.a[1]
|
||||
u_logic/_al_u2563_o u_logic/_al_u2564|u_logic/_al_u411.d[1]
|
||||
u_logic/_al_u2564_o u_logic/_al_u2565|u_logic/_al_u2847.d[1]
|
||||
u_logic/_al_u2565_o u_logic/_al_u2566|u_logic/J0iax6_reg.d[1]
|
||||
u_logic/_al_u2566_o u_logic/_al_u2641|u_logic/_al_u4457.d[1]
|
||||
u_logic/Vtzhu6 u_logic/_al_u2643|u_logic/_al_u954.d[1]
|
||||
u_logic/R0ghu6 u_logic/add2/ucin_al_u4809.b[0]
|
||||
u_logic/add2/c3 u_logic/add2/u3_al_u4810.fci
|
||||
u_logic/N5fpw6[4] u_logic/_al_u4753|u_logic/_al_u2604.c[0]
|
||||
u_logic/_al_u2604_o u_logic/_al_u2605|u_logic/Ibqpw6_reg.d[1]
|
||||
u_logic/_al_u2605_o u_logic/_al_u3990|RAMDATA_Interface/reg0_b3.b[0]
|
||||
HADDR[5] FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_r399_c1_m1.d[1]
|
||||
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_i399_007 FM_HW/_al_u2331|FM_HW/_al_u2330.b[0]
|
||||
FM_HW/_al_u2330_o FM_HW/_al_u2331|FM_HW/_al_u2330.c[1]
|
||||
FM_HW/_al_u2331_o FM_HW/FM_Demodulation/reg5_b19|FM_HW/FM_Demodulation/reg5_b18.b[1]
|
||||
FM_HW/_al_u2334_o FM_HW/_al_u2338.b[0]
|
||||
FM_HW/_al_u2338_o FM_HW/FM_Demodulation/reg5_b53|FM_HW/FM_Demodulation/reg5_b59.b[1]
|
||||
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_mux_b7/B6_3 FM_HW/_al_u2380|FM_HW/_al_u850.b[1]
|
||||
FM_HW/_al_u2380_o FM_HW/_al_u3650|FM_HW/FM_Dump_Data_IQ/reg0_b7.c[0]
|
||||
u_logic/N5fpw6[7] u_logic/_al_u2517|u_logic/_al_u2533.d[1]
|
||||
u_logic/_al_u2517_o u_logic/_al_u2518|u_logic/Vpgbx6_reg.d[1]
|
||||
u_logic/_al_u2518_o RAMDATA_Interface/reg0_b6|RAMDATA_Interface/reg0_b4.b[1]
|
||||
HADDR[8] FM_HW/_al_u3810|FM_HW/_al_u668.c[0]
|
||||
FM_HW/_al_u668_o FM_HW/_al_u2046|FM_HW/_al_u3360.b[1]
|
||||
FM_HW/_al_u2046_o FM_HW/_al_u2051|FM_HW/_al_u3361.a[1]
|
||||
FM_HW/_al_u2051_o FM_HW/_al_u2058.b[1]
|
||||
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_mux_b7/B4_8 FM_HW/_al_u2079.a[1]
|
||||
FM_HW/_al_u2079_o scan_unit/reg2_b15|scan_unit/reg2_b29.a[0]
|
||||
FM_HW/_al_u2123_o FM_HW/_al_u3595|FM_HW/FM_Dump_Data_IQ/reg0_b7.a[0]
|
||||
|
||||
|
||||
Endpoint: FM_HW/_al_u3584|FM_HW/FM_Dump_Data_IQ/reg0_b5
|
||||
464 -13.686000 37671203 3
|
||||
Timing path: u_logic/P5vpw6_reg.clk->FM_HW/_al_u3584|FM_HW/FM_Dump_Data_IQ/reg0_b5
|
||||
u_logic/P5vpw6_reg.clk
|
||||
FM_HW/_al_u3584|FM_HW/FM_Dump_Data_IQ/reg0_b5
|
||||
466 -13.686000 19.884000 33.570000 24 24
|
||||
u_logic/P5vpw6 cw_top/wrapper_cwc_top/trigger_inst/HAS_BUS_DETECTOR$BUS_DETECTOR[0]$bus_detector_inst1/reg0_b7|cw_top/wrapper_cwc_top/trigger_inst/HAS_BUS_DETECTOR$BUS_DETECTOR[0]$bus_detector_inst1/reg0_b6.b[0]
|
||||
u_logic/Llaow6_lutinv u_logic/_al_u1671|u_logic/_al_u2549.a[0]
|
||||
u_logic/_al_u2549_o u_logic/_al_u2551|u_logic/Fpnpw6_reg.a[1]
|
||||
Timing path: u_logic/Wkipw6_reg|u_logic/U9ypw6_reg.clk->FM_HW/_al_u3595|FM_HW/FM_Dump_Data_IQ/reg0_b7
|
||||
u_logic/Wkipw6_reg|u_logic/U9ypw6_reg.clk
|
||||
FM_HW/_al_u3595|FM_HW/FM_Dump_Data_IQ/reg0_b7
|
||||
310 -9.884000 19.884000 29.768000 23 23
|
||||
u_logic/U9ypw6 u_logic/_al_u708|u_logic/_al_u2324.c[1]
|
||||
u_logic/Ya1ju6_lutinv u_logic/_al_u2451|u_logic/_al_u2549.b[0]
|
||||
u_logic/_al_u2549_o u_logic/_al_u2551|u_logic/R3vpw6_reg.a[1]
|
||||
u_logic/_al_u2551_o u_logic/_al_u2552.a[1]
|
||||
u_logic/_al_u2552_o u_logic/_al_u2556|u_logic/_al_u1730.a[1]
|
||||
u_logic/_al_u2556_o u_logic/_al_u2563|u_logic/_al_u159.a[1]
|
||||
u_logic/_al_u2563_o u_logic/_al_u2564|u_logic/_al_u4431.d[1]
|
||||
u_logic/_al_u2564_o u_logic/_al_u2565|u_logic/_al_u2892.d[1]
|
||||
u_logic/_al_u2565_o u_logic/_al_u2566|u_logic/_al_u2882.d[1]
|
||||
u_logic/_al_u2566_o u_logic/_al_u2641|u_logic/_al_u2759.d[1]
|
||||
u_logic/Vtzhu6 u_logic/_al_u2643.d[0]
|
||||
u_logic/_al_u2552_o u_logic/_al_u2556|u_logic/_al_u2555.a[1]
|
||||
u_logic/_al_u2556_o u_logic/_al_u2563|u_logic/_al_u641.a[1]
|
||||
u_logic/_al_u2563_o u_logic/_al_u2564|u_logic/_al_u411.d[1]
|
||||
u_logic/_al_u2564_o u_logic/_al_u2565|u_logic/_al_u2847.d[1]
|
||||
u_logic/_al_u2565_o u_logic/_al_u2566|u_logic/J0iax6_reg.d[1]
|
||||
u_logic/_al_u2566_o u_logic/_al_u2641|u_logic/_al_u4457.d[1]
|
||||
u_logic/Vtzhu6 u_logic/_al_u2643|u_logic/_al_u954.d[1]
|
||||
u_logic/R0ghu6 u_logic/add2/ucin_al_u4809.b[0]
|
||||
u_logic/add2/c3 u_logic/add2/u3_al_u4810.fci
|
||||
u_logic/N5fpw6[4] u_logic/_al_u4753|u_logic/_al_u2604.c[0]
|
||||
u_logic/_al_u2604_o u_logic/_al_u2605|u_logic/Ibqpw6_reg.d[1]
|
||||
u_logic/_al_u2605_o u_logic/_al_u3990|RAMDATA_Interface/reg0_b3.b[0]
|
||||
HADDR[5] FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_r475_c1_m0.d[1]
|
||||
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_i475_005 FM_HW/_al_u2351|FM_HW/_al_u3012.b[0]
|
||||
FM_HW/_al_u3012_o FM_HW/_al_u3013|FM_HW/_al_u2666.c[1]
|
||||
FM_HW/_al_u3013_o FM_HW/_al_u3016.b[1]
|
||||
FM_HW/_al_u3016_o FM_HW/_al_u1918|FM_HW/_al_u3019.a[0]
|
||||
FM_HW/_al_u3019_o FM_HW/_al_u3030|FM_HW/_al_u795.b[1]
|
||||
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_mux_b5/B5_7 FM_HW/_al_u3158|FM_HW/FM_Demodulation/reg5_b52.a[0]
|
||||
FM_HW/_al_u3072_o FM_HW/_al_u3584|FM_HW/FM_Dump_Data_IQ/reg0_b5.c[0]
|
||||
u_logic/N5fpw6[7] u_logic/_al_u2517|u_logic/_al_u2533.d[1]
|
||||
u_logic/_al_u2517_o u_logic/_al_u2518|u_logic/Vpgbx6_reg.d[1]
|
||||
u_logic/_al_u2518_o RAMDATA_Interface/reg0_b6|RAMDATA_Interface/reg0_b4.b[1]
|
||||
HADDR[8] FM_HW/_al_u3810|FM_HW/_al_u668.c[0]
|
||||
FM_HW/_al_u668_o FM_HW/_al_u2046|FM_HW/_al_u3360.b[1]
|
||||
FM_HW/_al_u2046_o FM_HW/_al_u2051|FM_HW/_al_u3361.a[1]
|
||||
FM_HW/_al_u2051_o FM_HW/_al_u2058.b[0]
|
||||
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_mux_b7/B4_8 FM_HW/_al_u2079.a[1]
|
||||
FM_HW/_al_u2079_o scan_unit/reg2_b15|scan_unit/reg2_b29.a[0]
|
||||
FM_HW/_al_u2123_o FM_HW/_al_u3595|FM_HW/FM_Dump_Data_IQ/reg0_b7.a[0]
|
||||
|
||||
Timing path: u_logic/P5vpw6_reg.clk->FM_HW/_al_u3584|FM_HW/FM_Dump_Data_IQ/reg0_b5
|
||||
u_logic/P5vpw6_reg.clk
|
||||
FM_HW/_al_u3584|FM_HW/FM_Dump_Data_IQ/reg0_b5
|
||||
539 -13.686000 19.884000 33.570000 24 24
|
||||
u_logic/P5vpw6 cw_top/wrapper_cwc_top/trigger_inst/HAS_BUS_DETECTOR$BUS_DETECTOR[0]$bus_detector_inst1/reg0_b7|cw_top/wrapper_cwc_top/trigger_inst/HAS_BUS_DETECTOR$BUS_DETECTOR[0]$bus_detector_inst1/reg0_b6.b[0]
|
||||
u_logic/Llaow6_lutinv u_logic/_al_u1671|u_logic/_al_u2549.a[0]
|
||||
u_logic/_al_u2549_o u_logic/_al_u2551|u_logic/Fpnpw6_reg.a[1]
|
||||
u_logic/_al_u2551_o u_logic/_al_u2552.a[0]
|
||||
u_logic/_al_u2552_o u_logic/_al_u2556|u_logic/_al_u1730.a[1]
|
||||
u_logic/_al_u2556_o u_logic/_al_u2563|u_logic/_al_u159.a[1]
|
||||
u_logic/_al_u2563_o u_logic/_al_u2564|u_logic/_al_u4431.d[1]
|
||||
u_logic/_al_u2564_o u_logic/_al_u2565|u_logic/_al_u2892.d[1]
|
||||
u_logic/_al_u2565_o u_logic/_al_u2566|u_logic/_al_u2882.d[1]
|
||||
u_logic/_al_u2566_o u_logic/_al_u2641|u_logic/_al_u2759.d[1]
|
||||
u_logic/Vtzhu6 u_logic/_al_u2643.d[0]
|
||||
u_logic/R0ghu6 u_logic/add2/ucin_al_u4809.b[0]
|
||||
u_logic/add2/c3 u_logic/add2/u3_al_u4810.fci
|
||||
u_logic/N5fpw6[4] u_logic/_al_u4753|u_logic/_al_u2604.c[0]
|
||||
u_logic/_al_u2604_o u_logic/_al_u2605|u_logic/Ibqpw6_reg.d[1]
|
||||
u_logic/_al_u2605_o u_logic/_al_u3990|RAMDATA_Interface/reg0_b3.b[0]
|
||||
HADDR[5] FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_r475_c1_m0.d[1]
|
||||
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_i475_005 FM_HW/_al_u2351|FM_HW/_al_u3012.b[0]
|
||||
FM_HW/_al_u3012_o FM_HW/_al_u3013|FM_HW/_al_u2666.c[1]
|
||||
FM_HW/_al_u3013_o FM_HW/_al_u3016.b[1]
|
||||
FM_HW/_al_u3016_o FM_HW/_al_u1918|FM_HW/_al_u3019.a[0]
|
||||
FM_HW/_al_u3019_o FM_HW/_al_u3030|FM_HW/_al_u795.b[1]
|
||||
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_mux_b5/B5_7 FM_HW/_al_u3158|FM_HW/FM_Demodulation/reg5_b52.a[0]
|
||||
FM_HW/_al_u3072_o FM_HW/_al_u3584|FM_HW/FM_Dump_Data_IQ/reg0_b5.c[0]
|
||||
|
||||
Timing path: u_logic/P5vpw6_reg.clk->FM_HW/_al_u3584|FM_HW/FM_Dump_Data_IQ/reg0_b5
|
||||
u_logic/P5vpw6_reg.clk
|
||||
FM_HW/_al_u3584|FM_HW/FM_Dump_Data_IQ/reg0_b5
|
||||
612 -13.686000 19.884000 33.570000 24 24
|
||||
u_logic/P5vpw6 cw_top/wrapper_cwc_top/trigger_inst/HAS_BUS_DETECTOR$BUS_DETECTOR[0]$bus_detector_inst1/reg0_b7|cw_top/wrapper_cwc_top/trigger_inst/HAS_BUS_DETECTOR$BUS_DETECTOR[0]$bus_detector_inst1/reg0_b6.b[0]
|
||||
u_logic/Llaow6_lutinv u_logic/_al_u1671|u_logic/_al_u2549.a[0]
|
||||
u_logic/_al_u2549_o u_logic/_al_u2551|u_logic/Fpnpw6_reg.a[1]
|
||||
Timing path: u_logic/Wkipw6_reg|u_logic/U9ypw6_reg.clk->FM_HW/_al_u3595|FM_HW/FM_Dump_Data_IQ/reg0_b7
|
||||
u_logic/Wkipw6_reg|u_logic/U9ypw6_reg.clk
|
||||
FM_HW/_al_u3595|FM_HW/FM_Dump_Data_IQ/reg0_b7
|
||||
381 -9.884000 19.884000 29.768000 23 23
|
||||
u_logic/U9ypw6 u_logic/_al_u708|u_logic/_al_u2324.c[1]
|
||||
u_logic/Ya1ju6_lutinv u_logic/_al_u2451|u_logic/_al_u2549.b[0]
|
||||
u_logic/_al_u2549_o u_logic/_al_u2551|u_logic/R3vpw6_reg.a[1]
|
||||
u_logic/_al_u2551_o u_logic/_al_u2552.a[1]
|
||||
u_logic/_al_u2552_o u_logic/_al_u2556|u_logic/_al_u1730.a[1]
|
||||
u_logic/_al_u2556_o u_logic/_al_u2563|u_logic/_al_u159.a[1]
|
||||
u_logic/_al_u2563_o u_logic/_al_u2564|u_logic/_al_u4431.d[1]
|
||||
u_logic/_al_u2564_o u_logic/_al_u2565|u_logic/_al_u2892.d[1]
|
||||
u_logic/_al_u2565_o u_logic/_al_u2566|u_logic/_al_u2882.d[1]
|
||||
u_logic/_al_u2566_o u_logic/_al_u2641|u_logic/_al_u2759.d[1]
|
||||
u_logic/Vtzhu6 u_logic/_al_u2643.d[0]
|
||||
u_logic/_al_u2552_o u_logic/_al_u2556|u_logic/_al_u2555.a[1]
|
||||
u_logic/_al_u2556_o u_logic/_al_u2563|u_logic/_al_u641.a[1]
|
||||
u_logic/_al_u2563_o u_logic/_al_u2564|u_logic/_al_u411.d[1]
|
||||
u_logic/_al_u2564_o u_logic/_al_u2565|u_logic/_al_u2847.d[1]
|
||||
u_logic/_al_u2565_o u_logic/_al_u2566|u_logic/J0iax6_reg.d[1]
|
||||
u_logic/_al_u2566_o u_logic/_al_u2641|u_logic/_al_u4457.d[1]
|
||||
u_logic/Vtzhu6 u_logic/_al_u2643|u_logic/_al_u954.d[1]
|
||||
u_logic/R0ghu6 u_logic/add2/ucin_al_u4809.b[0]
|
||||
u_logic/add2/c3 u_logic/add2/u3_al_u4810.fci
|
||||
u_logic/N5fpw6[4] u_logic/_al_u4753|u_logic/_al_u2604.c[0]
|
||||
u_logic/_al_u2604_o u_logic/_al_u2605|u_logic/Ibqpw6_reg.d[1]
|
||||
u_logic/_al_u2605_o u_logic/_al_u3990|RAMDATA_Interface/reg0_b3.b[0]
|
||||
HADDR[5] FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_r475_c1_m0.d[1]
|
||||
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_i475_005 FM_HW/_al_u2351|FM_HW/_al_u3012.b[0]
|
||||
FM_HW/_al_u3012_o FM_HW/_al_u3013|FM_HW/_al_u2666.c[1]
|
||||
FM_HW/_al_u3013_o FM_HW/_al_u3016.b[0]
|
||||
FM_HW/_al_u3016_o FM_HW/_al_u1918|FM_HW/_al_u3019.a[0]
|
||||
FM_HW/_al_u3019_o FM_HW/_al_u3030|FM_HW/_al_u795.b[1]
|
||||
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_mux_b5/B5_7 FM_HW/_al_u3158|FM_HW/FM_Demodulation/reg5_b52.a[0]
|
||||
FM_HW/_al_u3072_o FM_HW/_al_u3584|FM_HW/FM_Dump_Data_IQ/reg0_b5.c[0]
|
||||
u_logic/N5fpw6[7] u_logic/_al_u2517|u_logic/_al_u2533.d[1]
|
||||
u_logic/_al_u2517_o u_logic/_al_u2518|u_logic/Vpgbx6_reg.d[1]
|
||||
u_logic/_al_u2518_o RAMDATA_Interface/reg0_b6|RAMDATA_Interface/reg0_b4.b[1]
|
||||
HADDR[8] FM_HW/_al_u3810|FM_HW/_al_u668.c[0]
|
||||
FM_HW/_al_u668_o FM_HW/_al_u2046|FM_HW/_al_u3360.b[1]
|
||||
FM_HW/_al_u2046_o FM_HW/_al_u2051|FM_HW/_al_u3361.a[1]
|
||||
FM_HW/_al_u2051_o FM_HW/_al_u2058.b[1]
|
||||
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_mux_b7/B4_8 FM_HW/_al_u2079.a[0]
|
||||
FM_HW/_al_u2079_o scan_unit/reg2_b15|scan_unit/reg2_b29.a[0]
|
||||
FM_HW/_al_u2123_o FM_HW/_al_u3595|FM_HW/FM_Dump_Data_IQ/reg0_b7.a[0]
|
||||
|
||||
|
||||
Endpoint: FM_HW/_al_u1512|FM_HW/FM_Dump_Data_IQ/reg0_b0
|
||||
452 -9.343000 45834844 3
|
||||
Timing path: u_logic/Wkipw6_reg|u_logic/U9ypw6_reg.clk->FM_HW/_al_u1512|FM_HW/FM_Dump_Data_IQ/reg0_b0
|
||||
u_logic/Wkipw6_reg|u_logic/U9ypw6_reg.clk
|
||||
FM_HW/_al_u1512|FM_HW/FM_Dump_Data_IQ/reg0_b0
|
||||
454 -9.343000 19.884000 29.227000 23 23
|
||||
u_logic/U9ypw6 u_logic/_al_u708|u_logic/_al_u2324.c[1]
|
||||
u_logic/Ya1ju6_lutinv u_logic/_al_u2451|u_logic/_al_u2549.b[0]
|
||||
u_logic/_al_u2549_o u_logic/_al_u2551|u_logic/R3vpw6_reg.a[1]
|
||||
u_logic/_al_u2551_o u_logic/_al_u2552.a[1]
|
||||
u_logic/_al_u2552_o u_logic/_al_u2556|u_logic/_al_u2555.a[1]
|
||||
u_logic/_al_u2556_o u_logic/_al_u2563|u_logic/_al_u641.a[1]
|
||||
u_logic/_al_u2563_o u_logic/_al_u2564|u_logic/_al_u411.d[1]
|
||||
u_logic/_al_u2564_o u_logic/_al_u2565|u_logic/_al_u2847.d[1]
|
||||
u_logic/_al_u2565_o u_logic/_al_u2566|u_logic/J0iax6_reg.d[1]
|
||||
u_logic/_al_u2566_o u_logic/_al_u2641|u_logic/_al_u4457.d[1]
|
||||
u_logic/Vtzhu6 u_logic/_al_u2643|u_logic/_al_u954.d[1]
|
||||
u_logic/R0ghu6 u_logic/add2/ucin_al_u4809.b[0]
|
||||
u_logic/N5fpw6[3] u_logic/_al_u2521|u_logic/_al_u2614.d[0]
|
||||
u_logic/_al_u2614_o u_logic/_al_u2615|u_logic/_al_u2597.d[1]
|
||||
u_logic/_al_u2615_o u_logic/_al_u4348|RAMDATA_Interface/reg0_b2.b[0]
|
||||
HADDR[4] FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_r443_c0_m0.c[0]
|
||||
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_i443_000 FM_HW/_al_u3138|FM_HW/_al_u1898.b[0]
|
||||
FM_HW/_al_u1898_o FM_HW/_al_u1899|FM_HW/_al_u2369.c[1]
|
||||
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_mux_b0/B1_110 FM_HW/_al_u1902|FM_HW/_al_u1577.a[1]
|
||||
FM_HW/_al_u1902_o FM_HW/_al_u3146|FM_HW/_al_u1907.a[0]
|
||||
FM_HW/_al_u1907_o FM_HW/_al_u1908.c[1]
|
||||
FM_HW/_al_u1908_o FM_HW/_al_u1950.a[1]
|
||||
FM_HW/_al_u1950_o FM_HW/_al_u1512|FM_HW/FM_Dump_Data_IQ/reg0_b0.c[0]
|
||||
|
||||
Timing path: u_logic/Wkipw6_reg|u_logic/U9ypw6_reg.clk->FM_HW/_al_u1512|FM_HW/FM_Dump_Data_IQ/reg0_b0
|
||||
u_logic/Wkipw6_reg|u_logic/U9ypw6_reg.clk
|
||||
FM_HW/_al_u1512|FM_HW/FM_Dump_Data_IQ/reg0_b0
|
||||
525 -9.343000 19.884000 29.227000 23 23
|
||||
u_logic/U9ypw6 u_logic/_al_u708|u_logic/_al_u2324.c[1]
|
||||
u_logic/Ya1ju6_lutinv u_logic/_al_u2451|u_logic/_al_u2549.b[0]
|
||||
u_logic/_al_u2549_o u_logic/_al_u2551|u_logic/R3vpw6_reg.a[1]
|
||||
u_logic/_al_u2551_o u_logic/_al_u2552.a[1]
|
||||
u_logic/_al_u2552_o u_logic/_al_u2556|u_logic/_al_u2555.a[1]
|
||||
u_logic/_al_u2556_o u_logic/_al_u2563|u_logic/_al_u641.a[1]
|
||||
u_logic/_al_u2563_o u_logic/_al_u2564|u_logic/_al_u411.d[1]
|
||||
u_logic/_al_u2564_o u_logic/_al_u2565|u_logic/_al_u2847.d[1]
|
||||
u_logic/_al_u2565_o u_logic/_al_u2566|u_logic/J0iax6_reg.d[1]
|
||||
u_logic/_al_u2566_o u_logic/_al_u2641|u_logic/_al_u4457.d[1]
|
||||
u_logic/Vtzhu6 u_logic/_al_u2643|u_logic/_al_u954.d[1]
|
||||
u_logic/R0ghu6 u_logic/add2/ucin_al_u4809.b[0]
|
||||
u_logic/N5fpw6[3] u_logic/_al_u2521|u_logic/_al_u2614.d[0]
|
||||
u_logic/_al_u2614_o u_logic/_al_u2615|u_logic/_al_u2597.d[1]
|
||||
u_logic/_al_u2615_o u_logic/_al_u4348|RAMDATA_Interface/reg0_b2.b[0]
|
||||
HADDR[4] FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_r443_c0_m0.c[0]
|
||||
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_i443_000 FM_HW/_al_u3138|FM_HW/_al_u1898.b[0]
|
||||
FM_HW/_al_u1898_o FM_HW/_al_u1899|FM_HW/_al_u2369.c[1]
|
||||
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_mux_b0/B1_110 FM_HW/_al_u1902|FM_HW/_al_u1577.a[1]
|
||||
FM_HW/_al_u1902_o FM_HW/_al_u3146|FM_HW/_al_u1907.a[0]
|
||||
FM_HW/_al_u1907_o FM_HW/_al_u1908.c[0]
|
||||
FM_HW/_al_u1908_o FM_HW/_al_u1950.a[1]
|
||||
FM_HW/_al_u1950_o FM_HW/_al_u1512|FM_HW/FM_Dump_Data_IQ/reg0_b0.c[0]
|
||||
|
||||
Timing path: u_logic/Wkipw6_reg|u_logic/U9ypw6_reg.clk->FM_HW/_al_u1512|FM_HW/FM_Dump_Data_IQ/reg0_b0
|
||||
u_logic/Wkipw6_reg|u_logic/U9ypw6_reg.clk
|
||||
FM_HW/_al_u1512|FM_HW/FM_Dump_Data_IQ/reg0_b0
|
||||
596 -9.343000 19.884000 29.227000 23 23
|
||||
u_logic/U9ypw6 u_logic/_al_u708|u_logic/_al_u2324.c[1]
|
||||
u_logic/Ya1ju6_lutinv u_logic/_al_u2451|u_logic/_al_u2549.b[0]
|
||||
u_logic/_al_u2549_o u_logic/_al_u2551|u_logic/R3vpw6_reg.a[1]
|
||||
u_logic/_al_u2551_o u_logic/_al_u2552.a[1]
|
||||
u_logic/_al_u2552_o u_logic/_al_u2556|u_logic/_al_u2555.a[1]
|
||||
u_logic/_al_u2556_o u_logic/_al_u2563|u_logic/_al_u641.a[1]
|
||||
u_logic/_al_u2563_o u_logic/_al_u2564|u_logic/_al_u411.d[1]
|
||||
u_logic/_al_u2564_o u_logic/_al_u2565|u_logic/_al_u2847.d[1]
|
||||
u_logic/_al_u2565_o u_logic/_al_u2566|u_logic/J0iax6_reg.d[1]
|
||||
u_logic/_al_u2566_o u_logic/_al_u2641|u_logic/_al_u4457.d[1]
|
||||
u_logic/Vtzhu6 u_logic/_al_u2643|u_logic/_al_u954.d[1]
|
||||
u_logic/R0ghu6 u_logic/add2/ucin_al_u4809.b[0]
|
||||
u_logic/N5fpw6[3] u_logic/_al_u2521|u_logic/_al_u2614.d[0]
|
||||
u_logic/_al_u2614_o u_logic/_al_u2615|u_logic/_al_u2597.d[1]
|
||||
u_logic/_al_u2615_o u_logic/_al_u4348|RAMDATA_Interface/reg0_b2.b[0]
|
||||
HADDR[4] FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_r443_c0_m0.c[0]
|
||||
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_i443_000 FM_HW/_al_u3138|FM_HW/_al_u1898.b[0]
|
||||
FM_HW/_al_u1898_o FM_HW/_al_u1899|FM_HW/_al_u2369.c[1]
|
||||
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_mux_b0/B1_110 FM_HW/_al_u1902|FM_HW/_al_u1577.a[1]
|
||||
FM_HW/_al_u1902_o FM_HW/_al_u3146|FM_HW/_al_u1907.a[0]
|
||||
FM_HW/_al_u1907_o FM_HW/_al_u1908.c[1]
|
||||
FM_HW/_al_u1908_o FM_HW/_al_u1950.a[0]
|
||||
FM_HW/_al_u1950_o FM_HW/_al_u1512|FM_HW/FM_Dump_Data_IQ/reg0_b0.c[0]
|
||||
|
||||
|
||||
|
||||
Hold check
|
||||
685 3
|
||||
Endpoint: SPI_TX/FIFO_SPI/al_ram_mem_r1_c1_l
|
||||
687 0.304000 94 3
|
||||
Timing path: _al_u270|SPI_TX/FIFO_SPI/reg1_b0.clk->SPI_TX/FIFO_SPI/al_ram_mem_r1_c1_l
|
||||
_al_u270|SPI_TX/FIFO_SPI/reg1_b0.clk
|
||||
SPI_TX/FIFO_SPI/al_ram_mem_r1_c1_l
|
||||
689 0.304000 0.134000 0.438000 1 1
|
||||
SPI_TX/FIFO_SPI/wp[0] SPI_TX/FIFO_SPI/al_ram_mem_r1_c1_l.a[0]
|
||||
667 3
|
||||
Endpoint: UART_TX/FIFO/al_ram_mem_c1_l
|
||||
669 0.284000 95 3
|
||||
Timing path: UART_TX/FIFO/reg1_b1|UART_TX/FIFO/reg1_b3.clk->UART_TX/FIFO/al_ram_mem_c1_l
|
||||
UART_TX/FIFO/reg1_b1|UART_TX/FIFO/reg1_b3.clk
|
||||
UART_TX/FIFO/al_ram_mem_c1_l
|
||||
671 0.284000 0.134000 0.418000 1 1
|
||||
UART_TX/FIFO/wp[3] UART_TX/FIFO/al_ram_mem_c1_l.d[0]
|
||||
|
||||
Timing path: UART_Interface/rd_en_reg_reg|SPI_Interface/wr_en_reg_reg.clk->SPI_TX/FIFO_SPI/al_ram_mem_r1_c1_l
|
||||
UART_Interface/rd_en_reg_reg|SPI_Interface/wr_en_reg_reg.clk
|
||||
SPI_TX/FIFO_SPI/al_ram_mem_r1_c1_l
|
||||
716 1.596000 0.134000 1.730000 2 2
|
||||
SPI_Interface/wr_en_reg _al_u128|_al_u130.d[1]
|
||||
SPI_TX_Data[4] SPI_TX/FIFO_SPI/al_ram_mem_r1_c1_l.a[1]
|
||||
Timing path: _al_u240|UART_Interface/wr_en_reg_reg.clk->UART_TX/FIFO/al_ram_mem_c1_l
|
||||
_al_u240|UART_Interface/wr_en_reg_reg.clk
|
||||
UART_TX/FIFO/al_ram_mem_c1_l
|
||||
698 1.092000 0.134000 1.226000 2 2
|
||||
UART_Interface/wr_en_reg _al_u121|UART_RX/counter_en_reg.d[1]
|
||||
UART_TX_data[7] UART_TX/FIFO/al_ram_mem_c1_l.d[1]
|
||||
|
||||
Timing path: u_logic/_al_u3978|u_logic/Wvgax6_reg.clk->SPI_TX/FIFO_SPI/al_ram_mem_r1_c1_l
|
||||
u_logic/_al_u3978|u_logic/Wvgax6_reg.clk
|
||||
SPI_TX/FIFO_SPI/al_ram_mem_r1_c1_l
|
||||
745 3.696000 0.134000 3.830000 3 3
|
||||
u_logic/Wvgax6 u_logic/_al_u3342|u_logic/Kqhbx6_reg.d[0]
|
||||
HWDATA[4] _al_u128|_al_u130.c[1]
|
||||
SPI_TX_Data[4] SPI_TX/FIFO_SPI/al_ram_mem_r1_c1_l.a[1]
|
||||
Timing path: u_logic/_al_u3982|u_logic/Wvgax6_reg.clk->UART_TX/FIFO/al_ram_mem_c1_l
|
||||
u_logic/_al_u3982|u_logic/Wvgax6_reg.clk
|
||||
UART_TX/FIFO/al_ram_mem_c1_l
|
||||
727 3.031000 0.134000 3.165000 3 3
|
||||
u_logic/Wvgax6 u_logic/_al_u4365|u_logic/Yqzax6_reg.c[0]
|
||||
HWDATA[7] _al_u121|UART_RX/counter_en_reg.c[1]
|
||||
UART_TX_data[7] UART_TX/FIFO/al_ram_mem_c1_l.d[1]
|
||||
|
||||
|
||||
Endpoint: FM_HW/FM_Demodulation/mult7_
|
||||
776 0.308000 10 3
|
||||
Timing path: FM_HW/FM_RSSI_SCAN/add2/ucin_al_u4000.clk->FM_HW/FM_Demodulation/mult7_
|
||||
FM_HW/FM_RSSI_SCAN/add2/ucin_al_u4000.clk
|
||||
FM_HW/FM_Demodulation/mult7_
|
||||
778 0.308000 0.100000 0.408000 0 1
|
||||
FM_HW/FM_Demodulation/dmd_data_filter[16][3] FM_HW/FM_Demodulation/mult7_.a[3]
|
||||
Endpoint: RAM_DATA/ram_mem_unify_al_u30_4096x8_sub_000000_006
|
||||
758 0.293000 12 3
|
||||
Timing path: RAMDATA_Interface/reg0_b6|RAMDATA_Interface/reg0_b4.clk->RAM_DATA/ram_mem_unify_al_u30_4096x8_sub_000000_006
|
||||
RAMDATA_Interface/reg0_b6|RAMDATA_Interface/reg0_b4.clk
|
||||
RAM_DATA/ram_mem_unify_al_u30_4096x8_sub_000000_006
|
||||
760 0.293000 0.200000 0.493000 0 1
|
||||
RAMDATA_WADDR[6] RAM_DATA/ram_mem_unify_al_u30_4096x8_sub_000000_006.addra[7]
|
||||
|
||||
Timing path: FM_HW/FM_Demodulation/reg5_b160|FM_HW/FM_Demodulation/reg5_b162.clk->FM_HW/FM_Demodulation/mult7_
|
||||
FM_HW/FM_Demodulation/reg5_b160|FM_HW/FM_Demodulation/reg5_b162.clk
|
||||
FM_HW/FM_Demodulation/mult7_
|
||||
805 0.320000 0.100000 0.420000 0 1
|
||||
FM_HW/FM_Demodulation/dmd_data_filter[16][2] FM_HW/FM_Demodulation/mult7_.a[2]
|
||||
Timing path: u_logic/_al_u2784|RAMDATA_Interface/reg0_b8.clk->RAM_DATA/ram_mem_unify_al_u30_4096x8_sub_000000_006
|
||||
u_logic/_al_u2784|RAMDATA_Interface/reg0_b8.clk
|
||||
RAM_DATA/ram_mem_unify_al_u30_4096x8_sub_000000_006
|
||||
787 0.351000 0.200000 0.551000 0 1
|
||||
RAMDATA_WADDR[8] RAM_DATA/ram_mem_unify_al_u30_4096x8_sub_000000_006.addra[9]
|
||||
|
||||
Timing path: FM_HW/FM_Demodulation/sub0_2/u0|sub0_2/ucin.clk->FM_HW/FM_Demodulation/mult7_
|
||||
FM_HW/FM_Demodulation/sub0_2/u0|sub0_2/ucin.clk
|
||||
FM_HW/FM_Demodulation/mult7_
|
||||
832 0.466000 0.100000 0.566000 0 1
|
||||
FM_HW/FM_Demodulation/dmd_data_filter[16][8] FM_HW/FM_Demodulation/mult7_.a[8]
|
||||
Timing path: RAMDATA_Interface/reg0_b6|RAMDATA_Interface/reg0_b4.clk->RAM_DATA/ram_mem_unify_al_u30_4096x8_sub_000000_006
|
||||
RAMDATA_Interface/reg0_b6|RAMDATA_Interface/reg0_b4.clk
|
||||
RAM_DATA/ram_mem_unify_al_u30_4096x8_sub_000000_006
|
||||
814 0.414000 0.200000 0.614000 0 1
|
||||
RAMDATA_WADDR[4] RAM_DATA/ram_mem_unify_al_u30_4096x8_sub_000000_006.addra[5]
|
||||
|
||||
|
||||
Endpoint: RAM_CODE/ram_mem_unify_al_u10_4096x8_sub_000000_006
|
||||
859 0.313000 12 3
|
||||
Timing path: RAMCODE_Interface/reg0_b9|RAMCODE_Interface/reg0_b8.clk->RAM_CODE/ram_mem_unify_al_u10_4096x8_sub_000000_006
|
||||
RAMCODE_Interface/reg0_b9|RAMCODE_Interface/reg0_b8.clk
|
||||
RAM_CODE/ram_mem_unify_al_u10_4096x8_sub_000000_006
|
||||
861 0.313000 0.200000 0.513000 0 1
|
||||
RAMCODE_WADDR[8] RAM_CODE/ram_mem_unify_al_u10_4096x8_sub_000000_006.addra[9]
|
||||
Endpoint: UART_TX/FIFO/al_ram_mem_c1_l
|
||||
841 0.295000 94 3
|
||||
Timing path: UART_TX/FIFO/reg1_b0|UART_TX/FIFO/reg1_b2.clk->UART_TX/FIFO/al_ram_mem_c1_l
|
||||
UART_TX/FIFO/reg1_b0|UART_TX/FIFO/reg1_b2.clk
|
||||
UART_TX/FIFO/al_ram_mem_c1_l
|
||||
843 0.295000 0.134000 0.429000 1 1
|
||||
UART_TX/FIFO/wp[2] UART_TX/FIFO/al_ram_mem_c1_l.c[0]
|
||||
|
||||
Timing path: RAMCODE_Interface/reg0_b9|RAMCODE_Interface/reg0_b8.clk->RAM_CODE/ram_mem_unify_al_u10_4096x8_sub_000000_006
|
||||
RAMCODE_Interface/reg0_b9|RAMCODE_Interface/reg0_b8.clk
|
||||
RAM_CODE/ram_mem_unify_al_u10_4096x8_sub_000000_006
|
||||
888 0.579000 0.200000 0.779000 0 1
|
||||
RAMCODE_WADDR[9] RAM_CODE/ram_mem_unify_al_u10_4096x8_sub_000000_006.addra[10]
|
||||
Timing path: _al_u240|UART_Interface/wr_en_reg_reg.clk->UART_TX/FIFO/al_ram_mem_c1_l
|
||||
_al_u240|UART_Interface/wr_en_reg_reg.clk
|
||||
UART_TX/FIFO/al_ram_mem_c1_l
|
||||
870 1.299000 0.134000 1.433000 2 2
|
||||
UART_Interface/wr_en_reg _al_u123|UART_RX/reg2_b5.d[1]
|
||||
UART_TX_data[6] UART_TX/FIFO/al_ram_mem_c1_l.c[1]
|
||||
|
||||
Timing path: RAMCODE_Interface/reg0_b11|RAMCODE_Interface/reg0_b10.clk->RAM_CODE/ram_mem_unify_al_u10_4096x8_sub_000000_006
|
||||
RAMCODE_Interface/reg0_b11|RAMCODE_Interface/reg0_b10.clk
|
||||
RAM_CODE/ram_mem_unify_al_u10_4096x8_sub_000000_006
|
||||
915 0.582000 0.200000 0.782000 0 1
|
||||
RAMCODE_WADDR[10] RAM_CODE/ram_mem_unify_al_u10_4096x8_sub_000000_006.addra[11]
|
||||
Timing path: u_logic/_al_u3982|u_logic/Wvgax6_reg.clk->UART_TX/FIFO/al_ram_mem_c1_l
|
||||
u_logic/_al_u3982|u_logic/Wvgax6_reg.clk
|
||||
UART_TX/FIFO/al_ram_mem_c1_l
|
||||
899 2.761000 0.134000 2.895000 3 3
|
||||
u_logic/Wvgax6 u_logic/_al_u3441|u_logic/Z9abx6_reg.d[0]
|
||||
HWDATA[6] _al_u123|UART_RX/reg2_b5.c[1]
|
||||
UART_TX_data[6] UART_TX/FIFO/al_ram_mem_c1_l.c[1]
|
||||
|
||||
|
||||
|
||||
Recovery check
|
||||
942 3
|
||||
Endpoint: cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b55|cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b68
|
||||
944 7.068000 1 1
|
||||
Timing path: _al_u570|cw_top/wrapper_cwc_top/cfg_int_inst/tap_inst/rst_reg.clk->cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b55|cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b68
|
||||
_al_u570|cw_top/wrapper_cwc_top/cfg_int_inst/tap_inst/rst_reg.clk
|
||||
cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b55|cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b68
|
||||
946 7.068000 9.700000 2.632000 0 1
|
||||
cw_top/wrapper_cwc_top/cfg_int_inst/rst cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b55|cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b68.sr
|
||||
930 3
|
||||
Endpoint: u_logic/_al_u3646|u_logic/X5ibx6_reg
|
||||
932 16.782000 1 1
|
||||
Timing path: u_logic/_al_u1562|cpuresetn_reg.clk->u_logic/_al_u3646|u_logic/X5ibx6_reg
|
||||
u_logic/_al_u1562|cpuresetn_reg.clk
|
||||
u_logic/_al_u3646|u_logic/X5ibx6_reg
|
||||
934 16.782000 19.700000 2.918000 0 1
|
||||
cpuresetn u_logic/_al_u3646|u_logic/X5ibx6_reg.sr
|
||||
|
||||
|
||||
Endpoint: cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b63|cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b64
|
||||
973 7.068000 1 1
|
||||
Timing path: _al_u570|cw_top/wrapper_cwc_top/cfg_int_inst/tap_inst/rst_reg.clk->cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b63|cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b64
|
||||
_al_u570|cw_top/wrapper_cwc_top/cfg_int_inst/tap_inst/rst_reg.clk
|
||||
cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b63|cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b64
|
||||
975 7.068000 9.700000 2.632000 0 1
|
||||
cw_top/wrapper_cwc_top/cfg_int_inst/rst cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b63|cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b64.sr
|
||||
Endpoint: u_logic/_al_u2354|u_logic/O4hax6_reg
|
||||
961 16.894000 1 1
|
||||
Timing path: u_logic/_al_u1562|cpuresetn_reg.clk->u_logic/_al_u2354|u_logic/O4hax6_reg
|
||||
u_logic/_al_u1562|cpuresetn_reg.clk
|
||||
u_logic/_al_u2354|u_logic/O4hax6_reg
|
||||
963 16.894000 19.700000 2.806000 0 1
|
||||
cpuresetn u_logic/_al_u2354|u_logic/O4hax6_reg.sr
|
||||
|
||||
|
||||
Endpoint: cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b140|cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b141
|
||||
1002 7.197000 1 1
|
||||
Timing path: _al_u570|cw_top/wrapper_cwc_top/cfg_int_inst/tap_inst/rst_reg.clk->cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b140|cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b141
|
||||
_al_u570|cw_top/wrapper_cwc_top/cfg_int_inst/tap_inst/rst_reg.clk
|
||||
cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b140|cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b141
|
||||
1004 7.197000 9.700000 2.503000 0 1
|
||||
cw_top/wrapper_cwc_top/cfg_int_inst/rst cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b140|cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg2_b141.sr
|
||||
Endpoint: u_logic/_al_u4735|u_logic/Knhax6_reg
|
||||
990 16.894000 1 1
|
||||
Timing path: u_logic/_al_u1562|cpuresetn_reg.clk->u_logic/_al_u4735|u_logic/Knhax6_reg
|
||||
u_logic/_al_u1562|cpuresetn_reg.clk
|
||||
u_logic/_al_u4735|u_logic/Knhax6_reg
|
||||
992 16.894000 19.700000 2.806000 0 1
|
||||
cpuresetn u_logic/_al_u4735|u_logic/Knhax6_reg.sr
|
||||
|
||||
|
||||
|
||||
Removal check
|
||||
1031 3
|
||||
Endpoint: u_logic/_al_u2894|u_logic/Wfspw6_reg
|
||||
1033 0.438000 1 1
|
||||
Timing path: u_logic/_al_u2275|cpuresetn_reg.clk->u_logic/_al_u2894|u_logic/Wfspw6_reg
|
||||
u_logic/_al_u2275|cpuresetn_reg.clk
|
||||
u_logic/_al_u2894|u_logic/Wfspw6_reg
|
||||
1035 0.438000 0.300000 0.738000 0 1
|
||||
cpuresetn u_logic/_al_u2894|u_logic/Wfspw6_reg.sr
|
||||
1019 3
|
||||
Endpoint: u_logic/I5xax6_reg|u_logic/R9yax6_reg
|
||||
1021 0.281000 1 1
|
||||
Timing path: u_logic/_al_u1562|cpuresetn_reg.clk->u_logic/I5xax6_reg|u_logic/R9yax6_reg
|
||||
u_logic/_al_u1562|cpuresetn_reg.clk
|
||||
u_logic/I5xax6_reg|u_logic/R9yax6_reg
|
||||
1023 0.281000 0.300000 0.581000 0 1
|
||||
cpuresetn u_logic/I5xax6_reg|u_logic/R9yax6_reg.sr
|
||||
|
||||
|
||||
Endpoint: u_logic/_al_u3144|u_logic/Kojpw6_reg
|
||||
1062 0.465000 1 1
|
||||
Timing path: u_logic/_al_u2275|cpuresetn_reg.clk->u_logic/_al_u3144|u_logic/Kojpw6_reg
|
||||
u_logic/_al_u2275|cpuresetn_reg.clk
|
||||
u_logic/_al_u3144|u_logic/Kojpw6_reg
|
||||
1064 0.465000 0.300000 0.765000 0 1
|
||||
cpuresetn u_logic/_al_u3144|u_logic/Kojpw6_reg.sr
|
||||
Endpoint: u_logic/_al_u2275|u_logic/Yzspw6_reg
|
||||
1050 0.314000 1 1
|
||||
Timing path: u_logic/_al_u1562|cpuresetn_reg.clk->u_logic/_al_u2275|u_logic/Yzspw6_reg
|
||||
u_logic/_al_u1562|cpuresetn_reg.clk
|
||||
u_logic/_al_u2275|u_logic/Yzspw6_reg
|
||||
1052 0.314000 0.300000 0.614000 0 1
|
||||
cpuresetn u_logic/_al_u2275|u_logic/Yzspw6_reg.sr
|
||||
|
||||
|
||||
Endpoint: cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg1_b5|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg1_b6
|
||||
1091 0.475000 1 1
|
||||
Timing path: cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg1_b0.clk->cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg1_b5|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg1_b6
|
||||
cw_top/wrapper_cwc_top/cfg_int_inst/reg_inst/reg1_b0.clk
|
||||
cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg1_b5|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg1_b6
|
||||
1093 0.475000 0.300000 0.775000 0 1
|
||||
cw_top/wrapper_cwc_top/control[0] cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg1_b5|cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_inst/reg1_b6.sr
|
||||
Endpoint: u_logic/_al_u3169|u_logic/C1wpw6_reg
|
||||
1079 0.461000 1 1
|
||||
Timing path: u_logic/_al_u1562|cpuresetn_reg.clk->u_logic/_al_u3169|u_logic/C1wpw6_reg
|
||||
u_logic/_al_u1562|cpuresetn_reg.clk
|
||||
u_logic/_al_u3169|u_logic/C1wpw6_reg
|
||||
1081 0.461000 0.300000 0.761000 0 1
|
||||
cpuresetn u_logic/_al_u3169|u_logic/C1wpw6_reg.sr
|
||||
|
||||
|
||||
|
||||
@ -410,11 +404,11 @@ cw_top/wrapper_cwc_top/control[0] cw_top/wrapper_cwc_top/trigger_inst/emb_ctrl_i
|
||||
Timing group statistics:
|
||||
Clock constraints:
|
||||
Clock Name Min Period Max Freq Skew Fanout TNS
|
||||
DeriveClock (50.0MHz) 33.826ns 29MHz 0.000ns 2795 -2264.715ns
|
||||
DeriveClock (50.0MHz) 30.123ns 33MHz 0.000ns 2544 -630.003ns
|
||||
Minimum input arrival time before clock: no constraint path
|
||||
Maximum output required time after clock: no constraint path
|
||||
Maximum combinational path delay: no constraint path
|
||||
Warning: No clock constraint on 14 clock net(s):
|
||||
Warning: No clock constraint on 13 clock net(s):
|
||||
CW_CLK_MSI
|
||||
FM_Display/clk_1KHz
|
||||
FM_HW/ADC_CLK
|
||||
@ -426,7 +420,6 @@ Warning: No clock constraint on 14 clock net(s):
|
||||
FM_HW/clk_fm_demo_sampling
|
||||
MSI_REFCLK_pad
|
||||
clk_pad
|
||||
jtck
|
||||
scan_unit/scan_clk
|
||||
u_logic/SWCLKTCK_pad
|
||||
|
||||
|
||||
@ -8,17 +8,17 @@ IO Statistics
|
||||
#inout 1
|
||||
|
||||
Utilization Statistics
|
||||
#lut 16581 out of 19600 84.60%
|
||||
#reg 2517 out of 19600 12.84%
|
||||
#le 16834
|
||||
#lut only 14317 out of 16834 85.05%
|
||||
#reg only 253 out of 16834 1.50%
|
||||
#lut® 2264 out of 16834 13.45%
|
||||
#lut 16271 out of 19600 83.02%
|
||||
#reg 2074 out of 19600 10.58%
|
||||
#le 16397
|
||||
#lut only 14323 out of 16397 87.35%
|
||||
#reg only 126 out of 16397 0.77%
|
||||
#lut® 1948 out of 16397 11.88%
|
||||
#dsp 26 out of 29 89.66%
|
||||
#bram 32 out of 64 50.00%
|
||||
#bram9k 32
|
||||
#fifo9k 0
|
||||
#bram32k 6 out of 16 37.50%
|
||||
#bram32k 0 out of 16 0.00%
|
||||
#adc 1 out of 1 100.00%
|
||||
#pad 39 out of 186 20.97%
|
||||
#ireg 0
|
||||
@ -74,5 +74,5 @@ Report Hierarchy Area:
|
||||
+----------------------------------------------------------------------+
|
||||
|Instance |Module |le |lut |ripple |seq |bram |dsp |
|
||||
+----------------------------------------------------------------------+
|
||||
|top |CortexM0_SoC |16834 |16108 |473 |2517 |38 |26 |
|
||||
|top |CortexM0_SoC |16397 |15898 |373 |2074 |32 |26 |
|
||||
+----------------------------------------------------------------------+
|
||||
|
||||
@ -1,13 +1,12 @@
|
||||
module CW_TOP_WRAPPER(jtdi, jtck, jrstn, jscan, jshift, jupdate, jtdo, non_bus_din, bus_din, trig_clk, wt_ce, wt_en, wt_addr);
|
||||
localparam DEFAULT_CTRL_REG_LEN = 223;
|
||||
localparam DEFAULT_CTRL_REG_LEN = 156;
|
||||
localparam DEFAULT_STAT_REG_LEN = 18;
|
||||
localparam DEFAULT_STOP_LEN = 2730;
|
||||
localparam DEFAULT_STOP_LEN = 5461;
|
||||
localparam DEFAULT_NON_BUS_NODE_NUM = 0;
|
||||
localparam DEFAULT_BUS_NODE_NUM = 48;
|
||||
localparam DEFAULT_BUS_NUM = 3;
|
||||
localparam DEFAULT_BUS1_WIDTH = 16;
|
||||
localparam DEFAULT_BUS2_WIDTH = 16;
|
||||
localparam DEFAULT_BUS3_WIDTH = 16;
|
||||
localparam DEFAULT_BUS_NODE_NUM = 17;
|
||||
localparam DEFAULT_BUS_NUM = 2;
|
||||
localparam DEFAULT_BUS1_WIDTH = 14;
|
||||
localparam DEFAULT_BUS2_WIDTH = 3;
|
||||
input jtdi;
|
||||
input jtck;
|
||||
input jrstn;
|
||||
@ -22,7 +21,7 @@ module CW_TOP_WRAPPER(jtdi, jtck, jrstn, jscan, jshift, jupdate, jtdo, non_bus_d
|
||||
output wt_en;
|
||||
output [15:0] wt_addr;
|
||||
|
||||
cwc_top #(.BUS1_WIDTH(DEFAULT_BUS1_WIDTH), .BUS2_WIDTH(DEFAULT_BUS2_WIDTH), .BUS3_WIDTH(DEFAULT_BUS3_WIDTH), .CTRL_REG_LEN(DEFAULT_CTRL_REG_LEN), .STAT_REG_LEN(DEFAULT_STAT_REG_LEN), .STOP_LEN(DEFAULT_STOP_LEN), .NON_BUS_NODE_NUM(DEFAULT_NON_BUS_NODE_NUM), .BUS_NODE_NUM(DEFAULT_BUS_NODE_NUM), .BUS_NUM(DEFAULT_BUS_NUM))
|
||||
cwc_top #(.BUS1_WIDTH(DEFAULT_BUS1_WIDTH), .BUS2_WIDTH(DEFAULT_BUS2_WIDTH), .CTRL_REG_LEN(DEFAULT_CTRL_REG_LEN), .STAT_REG_LEN(DEFAULT_STAT_REG_LEN), .STOP_LEN(DEFAULT_STOP_LEN), .NON_BUS_NODE_NUM(DEFAULT_NON_BUS_NODE_NUM), .BUS_NODE_NUM(DEFAULT_BUS_NODE_NUM), .BUS_NUM(DEFAULT_BUS_NUM))
|
||||
wrapper_cwc_top(
|
||||
.jtdi(jtdi),
|
||||
.jtck(jtck),
|
||||
|
||||
BIN
project/bitfile/MMC_20K_20M.bit
Normal file
BIN
project/bitfile/MMC_20K_20M.bit
Normal file
Binary file not shown.
BIN
project/bitfile/MMC_20K_40M.bit
Normal file
BIN
project/bitfile/MMC_20K_40M.bit
Normal file
Binary file not shown.
BIN
project/bitfile/MMC_40K_20M(good).bit
Normal file
BIN
project/bitfile/MMC_40K_20M(good).bit
Normal file
Binary file not shown.
BIN
project/bitfile/MMC_40K_40M.bit
Normal file
BIN
project/bitfile/MMC_40K_40M.bit
Normal file
Binary file not shown.
172
project/debug_rssi.cwc
Normal file
172
project/debug_rssi.cwc
Normal file
@ -0,0 +1,172 @@
|
||||
<chipwatcher project_name="MMC" bit_file="MMC.bit" bid_file="MMC_inst.bid" chip_name="EG4S20BG256">
|
||||
<instance name="auto_chipwatcher_0" id="0" enabled="yes">
|
||||
<clock clk_name="clk" polarity="posedge"/>
|
||||
<config bram_name="auto_chipwatcher_0_logicbram" sample_depth="8192"/>
|
||||
<signal_vec>
|
||||
<trigger_nets>
|
||||
<net name="FM_HW_state[1]"/>
|
||||
<net name="FM_HW_state[2]"/>
|
||||
<net name="FM_HW_state[3]"/>
|
||||
<net name="SPI_TX/counter[0]"/>
|
||||
<net name="SPI_TX/counter[10]"/>
|
||||
<net name="SPI_TX/counter[11]"/>
|
||||
<net name="SPI_TX/counter[12]"/>
|
||||
<net name="SPI_TX/counter[13]"/>
|
||||
<net name="SPI_TX/counter[1]"/>
|
||||
<net name="SPI_TX/counter[2]"/>
|
||||
<net name="SPI_TX/counter[3]"/>
|
||||
<net name="SPI_TX/counter[4]"/>
|
||||
<net name="SPI_TX/counter[5]"/>
|
||||
<net name="SPI_TX/counter[6]"/>
|
||||
<net name="SPI_TX/counter[7]"/>
|
||||
<net name="SPI_TX/counter[8]"/>
|
||||
<net name="SPI_TX/counter[9]"/>
|
||||
</trigger_nets>
|
||||
<data_nets>
|
||||
<net name="FM_HW/FM_RSSI_SCAN/RSSI_SUM[0]"/>
|
||||
<net name="FM_HW/FM_RSSI_SCAN/RSSI_SUM[10]"/>
|
||||
<net name="FM_HW/FM_RSSI_SCAN/RSSI_SUM[11]"/>
|
||||
<net name="FM_HW/FM_RSSI_SCAN/RSSI_SUM[12]"/>
|
||||
<net name="FM_HW/FM_RSSI_SCAN/RSSI_SUM[13]"/>
|
||||
<net name="FM_HW/FM_RSSI_SCAN/RSSI_SUM[14]"/>
|
||||
<net name="FM_HW/FM_RSSI_SCAN/RSSI_SUM[15]"/>
|
||||
<net name="FM_HW/FM_RSSI_SCAN/RSSI_SUM[16]"/>
|
||||
<net name="FM_HW/FM_RSSI_SCAN/RSSI_SUM[17]"/>
|
||||
<net name="FM_HW/FM_RSSI_SCAN/RSSI_SUM[18]"/>
|
||||
<net name="FM_HW/FM_RSSI_SCAN/RSSI_SUM[19]"/>
|
||||
<net name="FM_HW/FM_RSSI_SCAN/RSSI_SUM[1]"/>
|
||||
<net name="FM_HW/FM_RSSI_SCAN/RSSI_SUM[20]"/>
|
||||
<net name="FM_HW/FM_RSSI_SCAN/RSSI_SUM[21]"/>
|
||||
<net name="FM_HW/FM_RSSI_SCAN/RSSI_SUM[22]"/>
|
||||
<net name="FM_HW/FM_RSSI_SCAN/RSSI_SUM[23]"/>
|
||||
<net name="FM_HW/FM_RSSI_SCAN/RSSI_SUM[24]"/>
|
||||
<net name="FM_HW/FM_RSSI_SCAN/RSSI_SUM[25]"/>
|
||||
<net name="FM_HW/FM_RSSI_SCAN/RSSI_SUM[26]"/>
|
||||
<net name="FM_HW/FM_RSSI_SCAN/RSSI_SUM[2]"/>
|
||||
<net name="FM_HW/FM_RSSI_SCAN/RSSI_SUM[3]"/>
|
||||
<net name="FM_HW/FM_RSSI_SCAN/RSSI_SUM[4]"/>
|
||||
<net name="FM_HW/FM_RSSI_SCAN/RSSI_SUM[5]"/>
|
||||
<net name="FM_HW/FM_RSSI_SCAN/RSSI_SUM[6]"/>
|
||||
<net name="FM_HW/FM_RSSI_SCAN/RSSI_SUM[7]"/>
|
||||
<net name="FM_HW/FM_RSSI_SCAN/RSSI_SUM[8]"/>
|
||||
<net name="FM_HW/FM_RSSI_SCAN/RSSI_SUM[9]"/>
|
||||
<net name="FM_HW/FM_RSSI_SCAN/counter[0]"/>
|
||||
<net name="FM_HW/FM_RSSI_SCAN/counter[10]"/>
|
||||
<net name="FM_HW/FM_RSSI_SCAN/counter[11]"/>
|
||||
<net name="FM_HW/FM_RSSI_SCAN/counter[12]"/>
|
||||
<net name="FM_HW/FM_RSSI_SCAN/counter[1]"/>
|
||||
<net name="FM_HW/FM_RSSI_SCAN/counter[2]"/>
|
||||
<net name="FM_HW/FM_RSSI_SCAN/counter[3]"/>
|
||||
<net name="FM_HW/FM_RSSI_SCAN/counter[4]"/>
|
||||
<net name="FM_HW/FM_RSSI_SCAN/counter[5]"/>
|
||||
<net name="FM_HW/FM_RSSI_SCAN/counter[6]"/>
|
||||
<net name="FM_HW/FM_RSSI_SCAN/counter[7]"/>
|
||||
<net name="FM_HW/FM_RSSI_SCAN/counter[8]"/>
|
||||
<net name="FM_HW/FM_RSSI_SCAN/counter[9]"/>
|
||||
<net name="FM_HW_state[1]"/>
|
||||
<net name="FM_HW_state[2]"/>
|
||||
<net name="FM_HW_state[3]"/>
|
||||
<net name="HSEL_P4"/>
|
||||
<net name="HSEL_P5"/>
|
||||
<net name="MSI_CS"/>
|
||||
<net name="MSI_REFCLK"/>
|
||||
<net name="MSI_SCLK"/>
|
||||
<net name="MSI_SDATA"/>
|
||||
<net name="SPI_TX/counter[0]"/>
|
||||
<net name="SPI_TX/counter[10]"/>
|
||||
<net name="SPI_TX/counter[11]"/>
|
||||
<net name="SPI_TX/counter[12]"/>
|
||||
<net name="SPI_TX/counter[13]"/>
|
||||
<net name="SPI_TX/counter[1]"/>
|
||||
<net name="SPI_TX/counter[2]"/>
|
||||
<net name="SPI_TX/counter[3]"/>
|
||||
<net name="SPI_TX/counter[4]"/>
|
||||
<net name="SPI_TX/counter[5]"/>
|
||||
<net name="SPI_TX/counter[6]"/>
|
||||
<net name="SPI_TX/counter[7]"/>
|
||||
<net name="SPI_TX/counter[8]"/>
|
||||
<net name="SPI_TX/counter[9]"/>
|
||||
</data_nets>
|
||||
<watcher_nodes>
|
||||
<net name="MSI_CS" op="equal"/>
|
||||
<net name="MSI_REFCLK" op="equal"/>
|
||||
<net name="MSI_SCLK" op="equal"/>
|
||||
<net name="MSI_SDATA" op="equal"/>
|
||||
<net name="HSEL_P4" op="equal"/>
|
||||
<net name="HSEL_P5" op="equal"/>
|
||||
<bus name="FM_HW_state" radix="bin" state="collapse" op="equal">
|
||||
<net name="FM_HW_state[3]"/>
|
||||
<net name="FM_HW_state[2]"/>
|
||||
<net name="FM_HW_state[1]"/>
|
||||
</bus>
|
||||
<bus name="SPI_TX/counter" radix="hex" state="collapse" op="equal">
|
||||
<net name="SPI_TX/counter[13]"/>
|
||||
<net name="SPI_TX/counter[12]"/>
|
||||
<net name="SPI_TX/counter[11]"/>
|
||||
<net name="SPI_TX/counter[10]"/>
|
||||
<net name="SPI_TX/counter[9]"/>
|
||||
<net name="SPI_TX/counter[8]"/>
|
||||
<net name="SPI_TX/counter[7]"/>
|
||||
<net name="SPI_TX/counter[6]"/>
|
||||
<net name="SPI_TX/counter[5]"/>
|
||||
<net name="SPI_TX/counter[4]"/>
|
||||
<net name="SPI_TX/counter[3]"/>
|
||||
<net name="SPI_TX/counter[2]"/>
|
||||
<net name="SPI_TX/counter[1]"/>
|
||||
<net name="SPI_TX/counter[0]"/>
|
||||
</bus>
|
||||
<bus name="FM_HW/FM_RSSI_SCAN/RSSI_SUM" radix="bin" state="collapse" op="dont_care">
|
||||
<net name="FM_HW/FM_RSSI_SCAN/RSSI_SUM[26]"/>
|
||||
<net name="FM_HW/FM_RSSI_SCAN/RSSI_SUM[25]"/>
|
||||
<net name="FM_HW/FM_RSSI_SCAN/RSSI_SUM[24]"/>
|
||||
<net name="FM_HW/FM_RSSI_SCAN/RSSI_SUM[23]"/>
|
||||
<net name="FM_HW/FM_RSSI_SCAN/RSSI_SUM[22]"/>
|
||||
<net name="FM_HW/FM_RSSI_SCAN/RSSI_SUM[21]"/>
|
||||
<net name="FM_HW/FM_RSSI_SCAN/RSSI_SUM[20]"/>
|
||||
<net name="FM_HW/FM_RSSI_SCAN/RSSI_SUM[19]"/>
|
||||
<net name="FM_HW/FM_RSSI_SCAN/RSSI_SUM[18]"/>
|
||||
<net name="FM_HW/FM_RSSI_SCAN/RSSI_SUM[17]"/>
|
||||
<net name="FM_HW/FM_RSSI_SCAN/RSSI_SUM[16]"/>
|
||||
<net name="FM_HW/FM_RSSI_SCAN/RSSI_SUM[15]"/>
|
||||
<net name="FM_HW/FM_RSSI_SCAN/RSSI_SUM[14]"/>
|
||||
<net name="FM_HW/FM_RSSI_SCAN/RSSI_SUM[13]"/>
|
||||
<net name="FM_HW/FM_RSSI_SCAN/RSSI_SUM[12]"/>
|
||||
<net name="FM_HW/FM_RSSI_SCAN/RSSI_SUM[11]"/>
|
||||
<net name="FM_HW/FM_RSSI_SCAN/RSSI_SUM[10]"/>
|
||||
<net name="FM_HW/FM_RSSI_SCAN/RSSI_SUM[9]"/>
|
||||
<net name="FM_HW/FM_RSSI_SCAN/RSSI_SUM[8]"/>
|
||||
<net name="FM_HW/FM_RSSI_SCAN/RSSI_SUM[7]"/>
|
||||
<net name="FM_HW/FM_RSSI_SCAN/RSSI_SUM[6]"/>
|
||||
<net name="FM_HW/FM_RSSI_SCAN/RSSI_SUM[5]"/>
|
||||
<net name="FM_HW/FM_RSSI_SCAN/RSSI_SUM[4]"/>
|
||||
<net name="FM_HW/FM_RSSI_SCAN/RSSI_SUM[3]"/>
|
||||
<net name="FM_HW/FM_RSSI_SCAN/RSSI_SUM[2]"/>
|
||||
<net name="FM_HW/FM_RSSI_SCAN/RSSI_SUM[1]"/>
|
||||
<net name="FM_HW/FM_RSSI_SCAN/RSSI_SUM[0]"/>
|
||||
</bus>
|
||||
<bus name="FM_HW/FM_RSSI_SCAN/counter" radix="bin" state="collapse" op="dont_care">
|
||||
<net name="FM_HW/FM_RSSI_SCAN/counter[12]"/>
|
||||
<net name="FM_HW/FM_RSSI_SCAN/counter[11]"/>
|
||||
<net name="FM_HW/FM_RSSI_SCAN/counter[10]"/>
|
||||
<net name="FM_HW/FM_RSSI_SCAN/counter[9]"/>
|
||||
<net name="FM_HW/FM_RSSI_SCAN/counter[8]"/>
|
||||
<net name="FM_HW/FM_RSSI_SCAN/counter[7]"/>
|
||||
<net name="FM_HW/FM_RSSI_SCAN/counter[6]"/>
|
||||
<net name="FM_HW/FM_RSSI_SCAN/counter[5]"/>
|
||||
<net name="FM_HW/FM_RSSI_SCAN/counter[4]"/>
|
||||
<net name="FM_HW/FM_RSSI_SCAN/counter[3]"/>
|
||||
<net name="FM_HW/FM_RSSI_SCAN/counter[2]"/>
|
||||
<net name="FM_HW/FM_RSSI_SCAN/counter[1]"/>
|
||||
<net name="FM_HW/FM_RSSI_SCAN/counter[0]"/>
|
||||
</bus>
|
||||
</watcher_nodes>
|
||||
</signal_vec>
|
||||
<trigger name="auto_chipwatcher_0_trigger" position="pre">
|
||||
<condition level="1" enabled="yes" type="basic_or">
|
||||
FM_HW_state[1] == low && FM_HW_state[2] == high && FM_HW_state[3] == low && SPI_TX/counter[0] == high && SPI_TX/counter[10] == low && SPI_TX/counter[11] == low && SPI_TX/counter[12] == low && SPI_TX/counter[13] == low && SPI_TX/counter[1] == low && SPI_TX/counter[2] == low && SPI_TX/counter[3] == low && SPI_TX/counter[4] == low && SPI_TX/counter[5] == low && SPI_TX/counter[6] == low && SPI_TX/counter[7] == low && SPI_TX/counter[8] == low && SPI_TX/counter[9] == low
|
||||
</condition>
|
||||
<log>
|
||||
</log>
|
||||
</trigger>
|
||||
</instance>
|
||||
</chipwatcher>
|
||||
207
project/rssi.cwc
207
project/rssi.cwc
File diff suppressed because one or more lines are too long
257748
project/simulation/MMC.sdf
257748
project/simulation/MMC.sdf
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because one or more lines are too long
@ -34,31 +34,6 @@ parameter fir_18 = 8'h39;
|
||||
parameter fir_19 = 8'h22;
|
||||
parameter fir_20 = 8'h11;
|
||||
|
||||
/*
|
||||
parameter fir_1 = 8'h15;
|
||||
parameter fir_2 = 8'h27;
|
||||
parameter fir_3 = 8'h17;
|
||||
parameter fir_7 = 8'h17;
|
||||
parameter fir_8 = 8'h94;
|
||||
parameter fir_9 = 9'h107;
|
||||
parameter fir_10 = 9'h136;
|
||||
parameter fir_11 = 9'h107;
|
||||
parameter fir_12= 8'h93;
|
||||
parameter fir_13 = 8'h17;
|
||||
parameter fir_17 = 8'h17;
|
||||
parameter fir_18 = 8'h27;
|
||||
parameter fir_19 = 8'h15;
|
||||
|
||||
parameter fir_0 = 8'h09; // negtive
|
||||
parameter fir_4 = 8'h16; //negtive
|
||||
parameter fir_5 = 8'h3e; //negtive
|
||||
parameter fir_6 = 8'h36; //negtive
|
||||
parameter fir_14 = 8'h36; //negtive
|
||||
parameter fir_15 = 8'h3e; //negtive
|
||||
parameter fir_16 = 8'h16; //negtive
|
||||
parameter fir_20 = 8'h9; //negtive
|
||||
*/
|
||||
|
||||
reg [7:0] IdataN_1=8'h0;
|
||||
reg [7:0] IdataN=8'h0;
|
||||
reg [7:0] QdataN_1=8'h0;
|
||||
|
||||
@ -1,236 +1,236 @@
|
||||
`include "../topmodule/header.vh"
|
||||
module FM_HW #(
|
||||
parameter FM_ADDR_WIDTH = 13
|
||||
)(
|
||||
input clk,
|
||||
input ADC_start,
|
||||
input RSTn,
|
||||
output [7:0] LED_Out,
|
||||
|
||||
input [FM_ADDR_WIDTH-1:0] wraddr,
|
||||
input [FM_ADDR_WIDTH-1:0] rdaddr,
|
||||
input [31:0] wdata,
|
||||
input [3:0] wea,
|
||||
output wire [31:0] rdata,
|
||||
output reg [3:0] FM_HW_state,
|
||||
output wire RSSI_interrupt,
|
||||
output wire IQ_Write_Done_interrupt,
|
||||
output wire Demo_Dump_Done_Interrupt,
|
||||
output wire audio_pwm
|
||||
);
|
||||
|
||||
reg adc_Power_down=1'b1; //1: power down, 0?power on
|
||||
wire EOC;
|
||||
wire [31:0] rd_DUMP;
|
||||
wire [31:0] rd_SCAN;
|
||||
|
||||
|
||||
|
||||
reg [4:0] ADC_dump_parameters;
|
||||
|
||||
/*
|
||||
parameter dumpIQ_or_audio: 1'b1: dump IQ data; 1'b0:dump audio data
|
||||
if you want dump IQ data, set the dumpIQ_or_audio = 1'b1
|
||||
then make instance of FM_Dump_Data as FM_Dump_Data_IQ
|
||||
|
||||
if you want dump audio data, set the dumpIQ_or_audio = 1'b0
|
||||
you need make instance of:FM_Dump_Data FM_Dump_Data_Audio
|
||||
*/
|
||||
|
||||
localparam dumpIQ_or_audio = 1'b1;
|
||||
localparam FM_HW_STATE_IDLE = 4'b0000;
|
||||
localparam FM_HW_STATE_RCEV = 4'b0010; //Receiver State, receiver, dump IQ or audio data
|
||||
localparam FM_HW_STATE_RSSI = 4'b0100; //RSSI Scan state
|
||||
localparam FM_HW_STATE_RSSI_DONE = 4'b1000; //Sent from core, marking the end of single RSSI scan
|
||||
|
||||
reg RSSI_Scan_Start;
|
||||
|
||||
always@(posedge clk or negedge RSTn ) begin
|
||||
if (!RSTn) begin
|
||||
FM_HW_state <= FM_HW_STATE_IDLE;
|
||||
adc_Power_down <=1'b1;
|
||||
end
|
||||
else if ((wraddr==15'h004)&&(wdata[7:4]==4'b0001)&&(wea==4'hf)) begin //control to normal FM receiver On
|
||||
FM_HW_state <= FM_HW_STATE_RCEV;
|
||||
adc_Power_down <=1'b0;
|
||||
end
|
||||
else if ((wraddr==15'h004)&&(wdata[7:4]==4'b0010)&&(wea==4'hf)) begin //control to normal FM receiver OFF
|
||||
FM_HW_state <= FM_HW_STATE_IDLE;
|
||||
adc_Power_down <=1'b1;
|
||||
end
|
||||
else if ((wraddr==15'h004)&&(wdata[15:8]==8'h01)&&(wea==4'hf)) begin //RSSI scan start parameters
|
||||
FM_HW_state <= FM_HW_STATE_RSSI;
|
||||
adc_Power_down <=1'b0;
|
||||
end
|
||||
else if ((wraddr==13'h004)&&(wdata[15:8]==8'h02)&&(wea==4'hf)) begin //RSSI scan done parameters
|
||||
FM_HW_state <= FM_HW_STATE_RSSI_DONE;
|
||||
adc_Power_down <=1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
wire CW_CLK; //synthesis keep;
|
||||
wire ADC_CLK;
|
||||
wire CLK_Lock;
|
||||
wire clk_PWM1;
|
||||
wire clk_PWM2;
|
||||
|
||||
`ifndef SIM_PROFILE
|
||||
PLL_Demodulation U1 //use final adc clk 200Khz
|
||||
(
|
||||
.refclk(clk),
|
||||
.reset(1'b0),
|
||||
.stdby(1'b0),
|
||||
.extlock(CLK_Lock),
|
||||
.clk0_out(CW_CLK), //ChipWatcher采样时钟 200M
|
||||
.clk1_out(ADC_CLK), //ADC工作时钟,6.4M
|
||||
.clk2_out(clk_PWM1), //20M
|
||||
.clk4_out(clk_PWM2) //40M
|
||||
);
|
||||
`endif
|
||||
|
||||
//ADC通道4,6轮询
|
||||
reg[2:0] Channel;
|
||||
|
||||
always@(posedge EOC or negedge RSTn ) begin
|
||||
if (!RSTn) Channel <= 3'b100;
|
||||
else if (Channel == 3'b100)
|
||||
Channel <= 3'b110;
|
||||
else
|
||||
Channel <= 3'b100;
|
||||
|
||||
end
|
||||
|
||||
|
||||
|
||||
//ADC输出数据
|
||||
wire [11:0]ADC_Data ; //synthesis keep;
|
||||
|
||||
//CH6-P12 MSI I data, CH4-M12 MSI Q data
|
||||
`ifndef SIM_PROFILE
|
||||
ADC_Sampling U2
|
||||
(
|
||||
.eoc(EOC),
|
||||
.dout(ADC_Data),
|
||||
.clk(ADC_CLK),
|
||||
.pd(adc_Power_down),
|
||||
.s(Channel),
|
||||
.soc(1'b1)
|
||||
);
|
||||
`else
|
||||
|
||||
ADC_Sample_debug ADC_Sample_debug(
|
||||
.eoc(EOC),
|
||||
.dout(ADC_Data),
|
||||
.clk(clk),
|
||||
.RSTn(RSTn),
|
||||
.channel(Channel)
|
||||
);
|
||||
|
||||
reg [2:0] sim_PWM_clk;
|
||||
reg sim_clk_PWM1;
|
||||
always@(posedge clk or negedge RSTn ) begin
|
||||
if (!RSTn) begin sim_clk_PWM1 <= 1'b0; sim_PWM_clk <=3'b000; end
|
||||
else if (sim_PWM_clk == 3'b101) begin
|
||||
sim_clk_PWM1 <= 1'b1;
|
||||
sim_PWM_clk <=3'b000;
|
||||
end
|
||||
else begin
|
||||
sim_clk_PWM1 <= 1'b0;
|
||||
sim_PWM_clk = sim_PWM_clk+1'b1;
|
||||
end
|
||||
end
|
||||
`endif
|
||||
|
||||
|
||||
|
||||
|
||||
wire [9:0] demodulated_signal_downsample;
|
||||
FM_Demodulation FM_Demodulation
|
||||
(
|
||||
|
||||
.EOC(EOC),
|
||||
.Channel(Channel),
|
||||
.FM_HW_state(FM_HW_state),
|
||||
.RSTn(RSTn),
|
||||
.ADC_Data(ADC_Data),
|
||||
.demod_en(adc_Power_down),
|
||||
.demodulated_signal_sample(demodulated_signal_downsample),
|
||||
.clk_fm_demo_sampling(clk_fm_demo_sampling)
|
||||
);
|
||||
|
||||
|
||||
FM_RSSI_SCAN FM_RSSI_SCAN
|
||||
(
|
||||
.clk(clk),
|
||||
.rdaddr(wraddr),
|
||||
.rdata(rd_SCAN),
|
||||
.EOC(EOC),
|
||||
.Channel(Channel),
|
||||
.FM_HW_state(FM_HW_state),
|
||||
.RSTn(RSTn),
|
||||
.ADC_Data(ADC_Data),
|
||||
.RSSI_interrupt(RSSI_interrupt)
|
||||
);
|
||||
|
||||
// select FM_Dump_Data_IQ or FM_Dump_Data_Audio
|
||||
FM_Dump_Data FM_Dump_Data_IQ
|
||||
(
|
||||
.clk(clk),
|
||||
.RSTn(RSTn),
|
||||
.dump_data_clk(EOC),
|
||||
.FM_HW_state(FM_HW_state),
|
||||
.wraddr(wraddr),
|
||||
.rdaddr(rdaddr),
|
||||
.wdata(wdata),
|
||||
.wea(wea),
|
||||
.dump_data(ADC_Data[11:4]),
|
||||
.rdata(rd_DUMP),
|
||||
.Dump_Done_Interrupt(Dump_Done_Interrupt)
|
||||
|
||||
);
|
||||
/*
|
||||
FM_Dump_Data FM_Dump_Data_Audio
|
||||
(
|
||||
.clk(clk),
|
||||
.RSTn(RSTn),
|
||||
.dump_data_clk(clk_fm_demo_sampling),
|
||||
.FM_HW_state(FM_HW_state),
|
||||
|
||||
.wraddr(wraddr),
|
||||
.rdaddr(wraddr),
|
||||
.wdata(wdata),
|
||||
.wea(wea),
|
||||
|
||||
.dump_data(demodulated_signal_downsample[8:1]),
|
||||
|
||||
.rdata(rdata),
|
||||
|
||||
.Dump_Done_Interrupt(Dump_Done_Interrupt)
|
||||
|
||||
);
|
||||
|
||||
*/
|
||||
|
||||
Aduio_PWM Audio_PWM
|
||||
(
|
||||
.clk_fm_demo_sampling(clk_fm_demo_sampling),
|
||||
`ifndef SIM_PROFILE
|
||||
.clk(clk_PWM1), //simulating 20K or 40K * 200KHz ADC sampling clk
|
||||
`else
|
||||
.clk(sim_clk_PWM1), // for Model Simulation ONLY
|
||||
`endif
|
||||
.RSTn(RSTn),
|
||||
.demod_en(adc_Power_down),
|
||||
.demodulated_signal_downsample(demodulated_signal_downsample),
|
||||
.audio_pwm(audio_pwm)
|
||||
|
||||
);
|
||||
|
||||
|
||||
assign LED_Out = {audio_pwm,audio_pwm,audio_pwm,audio_pwm,~audio_pwm,~audio_pwm,~audio_pwm,~audio_pwm};
|
||||
|
||||
assign IQ_Write_Done_interrupt = dumpIQ_or_audio? Dump_Done_Interrupt:1'b0;
|
||||
assign Demo_Dump_Done_Interrupt = (~dumpIQ_or_audio)? Dump_Done_Interrupt:1'b0;
|
||||
assign rdata = (FM_HW_state == FM_HW_STATE_RSSI) ? rd_SCAN:rd_DUMP;
|
||||
|
||||
endmodule
|
||||
`include "../topmodule/header.vh"
|
||||
module FM_HW #(
|
||||
parameter FM_ADDR_WIDTH = 13
|
||||
)(
|
||||
input clk,
|
||||
input ADC_start,
|
||||
input RSTn,
|
||||
output [7:0] LED_Out,
|
||||
|
||||
input [FM_ADDR_WIDTH-1:0] wraddr,
|
||||
input [FM_ADDR_WIDTH-1:0] rdaddr,
|
||||
input [31:0] wdata,
|
||||
input [3:0] wea,
|
||||
output wire [31:0] rdata,
|
||||
output reg [3:0] FM_HW_state,
|
||||
output wire RSSI_interrupt,
|
||||
output wire IQ_Write_Done_interrupt,
|
||||
output wire Demo_Dump_Done_Interrupt,
|
||||
output wire audio_pwm
|
||||
);
|
||||
|
||||
reg adc_Power_down=1'b1; //1: power down, 0?power on
|
||||
wire EOC;
|
||||
wire [31:0] rd_DUMP;
|
||||
wire [31:0] rd_SCAN;
|
||||
|
||||
|
||||
|
||||
reg [4:0] ADC_dump_parameters;
|
||||
|
||||
/*
|
||||
parameter dumpIQ_or_audio: 1'b1: dump IQ data; 1'b0:dump audio data
|
||||
if you want dump IQ data, set the dumpIQ_or_audio = 1'b1
|
||||
then make instance of FM_Dump_Data as FM_Dump_Data_IQ
|
||||
|
||||
if you want dump audio data, set the dumpIQ_or_audio = 1'b0
|
||||
you need make instance of:FM_Dump_Data FM_Dump_Data_Audio
|
||||
*/
|
||||
|
||||
localparam dumpIQ_or_audio = 1'b1;
|
||||
localparam FM_HW_STATE_IDLE = 4'b0000;
|
||||
localparam FM_HW_STATE_RCEV = 4'b0010; //Receiver State, receiver, dump IQ or audio data
|
||||
localparam FM_HW_STATE_RSSI = 4'b0100; //RSSI Scan state
|
||||
localparam FM_HW_STATE_RSSI_DONE = 4'b1000; //Sent from core, marking the end of single RSSI scan
|
||||
|
||||
reg RSSI_Scan_Start;
|
||||
|
||||
always@(posedge clk or negedge RSTn ) begin
|
||||
if (!RSTn) begin
|
||||
FM_HW_state <= FM_HW_STATE_IDLE;
|
||||
adc_Power_down <=1'b1;
|
||||
end
|
||||
else if ((wraddr==15'h004)&&(wdata[7:4]==4'b0001)&&(wea==4'hf)) begin //control to normal FM receiver On
|
||||
FM_HW_state <= FM_HW_STATE_RCEV;
|
||||
adc_Power_down <=1'b0;
|
||||
end
|
||||
else if ((wraddr==15'h004)&&(wdata[7:4]==4'b0010)&&(wea==4'hf)) begin //control to normal FM receiver OFF
|
||||
FM_HW_state <= FM_HW_STATE_IDLE;
|
||||
adc_Power_down <=1'b1;
|
||||
end
|
||||
else if ((wraddr==15'h004)&&(wdata[15:8]==8'h01)&&(wea==4'hf)) begin //RSSI scan start parameters
|
||||
FM_HW_state <= FM_HW_STATE_RSSI;
|
||||
adc_Power_down <=1'b0;
|
||||
end
|
||||
else if ((wraddr==13'h004)&&(wdata[15:8]==8'h02)&&(wea==4'hf)) begin //RSSI scan done parameters
|
||||
FM_HW_state <= FM_HW_STATE_RSSI_DONE;
|
||||
adc_Power_down <=1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
wire CW_CLK; //synthesis keep;
|
||||
wire ADC_CLK;
|
||||
wire CLK_Lock;
|
||||
wire clk_PWM1;
|
||||
wire clk_PWM2;
|
||||
|
||||
`ifndef SIM_PROFILE
|
||||
PLL_Demodulation U1 //use final adc clk 200Khz
|
||||
(
|
||||
.refclk(clk),
|
||||
.reset(1'b0),
|
||||
.stdby(1'b0),
|
||||
.extlock(CLK_Lock),
|
||||
.clk0_out(CW_CLK), //ChipWatcher采样时钟 200M
|
||||
.clk1_out(ADC_CLK), //ADC工作时钟,6.4M
|
||||
.clk2_out(clk_PWM1), //20M
|
||||
.clk4_out(clk_PWM2) //40M
|
||||
);
|
||||
`endif
|
||||
|
||||
//ADC通道4,6轮询
|
||||
reg[2:0] Channel;
|
||||
|
||||
always@(posedge EOC or negedge RSTn ) begin
|
||||
if (!RSTn) Channel <= 3'b100;
|
||||
else if (Channel == 3'b100)
|
||||
Channel <= 3'b110;
|
||||
else
|
||||
Channel <= 3'b100;
|
||||
|
||||
end
|
||||
|
||||
|
||||
|
||||
//ADC输出数据
|
||||
wire [11:0]ADC_Data ; //synthesis keep;
|
||||
|
||||
//CH6-P12 MSI I data, CH4-M12 MSI Q data
|
||||
`ifndef SIM_PROFILE
|
||||
ADC_Sampling U2
|
||||
(
|
||||
.eoc(EOC),
|
||||
.dout(ADC_Data),
|
||||
.clk(ADC_CLK),
|
||||
.pd(adc_Power_down),
|
||||
.s(Channel),
|
||||
.soc(1'b1)
|
||||
);
|
||||
`else
|
||||
|
||||
ADC_Sample_debug ADC_Sample_debug(
|
||||
.eoc(EOC),
|
||||
.dout(ADC_Data),
|
||||
.clk(clk),
|
||||
.RSTn(RSTn),
|
||||
.channel(Channel)
|
||||
);
|
||||
|
||||
reg [2:0] sim_PWM_clk;
|
||||
reg sim_clk_PWM1;
|
||||
always@(posedge clk or negedge RSTn ) begin
|
||||
if (!RSTn) begin sim_clk_PWM1 <= 1'b0; sim_PWM_clk <=3'b000; end
|
||||
else if (sim_PWM_clk == 3'b101) begin
|
||||
sim_clk_PWM1 <= 1'b1;
|
||||
sim_PWM_clk <=3'b000;
|
||||
end
|
||||
else begin
|
||||
sim_clk_PWM1 <= 1'b0;
|
||||
sim_PWM_clk = sim_PWM_clk+1'b1;
|
||||
end
|
||||
end
|
||||
`endif
|
||||
|
||||
|
||||
|
||||
|
||||
wire [9:0] demodulated_signal_downsample;
|
||||
FM_Demodulation FM_Demodulation
|
||||
(
|
||||
|
||||
.EOC(EOC),
|
||||
.Channel(Channel),
|
||||
.FM_HW_state(FM_HW_state),
|
||||
.RSTn(RSTn),
|
||||
.ADC_Data(ADC_Data),
|
||||
.demod_en(adc_Power_down),
|
||||
.demodulated_signal_sample(demodulated_signal_downsample),
|
||||
.clk_fm_demo_sampling(clk_fm_demo_sampling)
|
||||
);
|
||||
|
||||
|
||||
FM_RSSI_SCAN FM_RSSI_SCAN
|
||||
(
|
||||
.clk(clk),
|
||||
.rdaddr(wraddr),
|
||||
.rdata(rd_SCAN),
|
||||
.EOC(EOC),
|
||||
.Channel(Channel),
|
||||
.FM_HW_state(FM_HW_state),
|
||||
.RSTn(RSTn),
|
||||
.ADC_Data(ADC_Data),
|
||||
.RSSI_interrupt(RSSI_interrupt)
|
||||
);
|
||||
|
||||
// select FM_Dump_Data_IQ or FM_Dump_Data_Audio
|
||||
FM_Dump_Data FM_Dump_Data_IQ
|
||||
(
|
||||
.clk(clk),
|
||||
.RSTn(RSTn),
|
||||
.dump_data_clk(EOC),
|
||||
.FM_HW_state(FM_HW_state),
|
||||
.wraddr(wraddr),
|
||||
.rdaddr(rdaddr),
|
||||
.wdata(wdata),
|
||||
.wea(wea),
|
||||
.dump_data(ADC_Data[11:4]),
|
||||
.rdata(rd_DUMP),
|
||||
.Dump_Done_Interrupt(Dump_Done_Interrupt)
|
||||
|
||||
);
|
||||
/*
|
||||
FM_Dump_Data FM_Dump_Data_Audio
|
||||
(
|
||||
.clk(clk),
|
||||
.RSTn(RSTn),
|
||||
.dump_data_clk(clk_fm_demo_sampling),
|
||||
.FM_HW_state(FM_HW_state),
|
||||
|
||||
.wraddr(wraddr),
|
||||
.rdaddr(wraddr),
|
||||
.wdata(wdata),
|
||||
.wea(wea),
|
||||
|
||||
.dump_data(demodulated_signal_downsample[8:1]),
|
||||
|
||||
.rdata(rdata),
|
||||
|
||||
.Dump_Done_Interrupt(Dump_Done_Interrupt)
|
||||
|
||||
);
|
||||
|
||||
*/
|
||||
|
||||
Aduio_PWM Audio_PWM
|
||||
(
|
||||
.clk_fm_demo_sampling(clk_fm_demo_sampling),
|
||||
`ifndef SIM_PROFILE
|
||||
.clk(clk_PWM1), //simulating 20K or 40K * 200KHz ADC sampling clk
|
||||
`else
|
||||
.clk(sim_clk_PWM1), // for Model Simulation ONLY
|
||||
`endif
|
||||
.RSTn(RSTn),
|
||||
.demod_en(adc_Power_down),
|
||||
.demodulated_signal_downsample(demodulated_signal_downsample),
|
||||
.audio_pwm(audio_pwm)
|
||||
|
||||
);
|
||||
|
||||
|
||||
assign LED_Out = {audio_pwm,audio_pwm,audio_pwm,audio_pwm,~audio_pwm,~audio_pwm,~audio_pwm,~audio_pwm};
|
||||
|
||||
assign IQ_Write_Done_interrupt = dumpIQ_or_audio? Dump_Done_Interrupt:1'b0;
|
||||
assign Demo_Dump_Done_Interrupt = (~dumpIQ_or_audio)? Dump_Done_Interrupt:1'b0;
|
||||
assign rdata = (FM_HW_state == FM_HW_STATE_RSSI) ? rd_SCAN:rd_DUMP;
|
||||
|
||||
endmodule
|
||||
|
||||
@ -1,24 +1,24 @@
|
||||
|
||||
module clk_fm_demo_sample_pwm
|
||||
#( parameter BPS_PARA = 10 ) //200Khz/BPS_PARA = audio samping rate. BPS_PARA=10: 20kHz
|
||||
(
|
||||
input FM_demod_en,
|
||||
input EOC,
|
||||
input RSTn,
|
||||
output reg clk_fm_demo_sampling
|
||||
);
|
||||
|
||||
reg [5:0] cnt = 0;
|
||||
always @ (posedge EOC or negedge RSTn) begin
|
||||
if(~RSTn) cnt <= 6'b0;
|
||||
else if (~FM_demod_en) begin
|
||||
if((cnt >= BPS_PARA-1)||(FM_demod_en)) begin
|
||||
cnt <= 6'b0;
|
||||
clk_fm_demo_sampling <= 1'b1;
|
||||
end
|
||||
else begin cnt <= cnt + 1'b1;clk_fm_demo_sampling <= 1'b0; end
|
||||
end
|
||||
else clk_fm_demo_sampling <= 1'b0;
|
||||
end
|
||||
|
||||
|
||||
module clk_fm_demo_sample_pwm
|
||||
#( parameter BPS_PARA = 10 ) //400Khz/BPS_PARA = audio samping rate. BPS_PARA=20: 20kHz
|
||||
(
|
||||
input FM_demod_en,
|
||||
input EOC,
|
||||
input RSTn,
|
||||
output reg clk_fm_demo_sampling
|
||||
);
|
||||
|
||||
reg [5:0] cnt = 0;
|
||||
always @ (posedge EOC or negedge RSTn) begin
|
||||
if(~RSTn) cnt <= 6'b0;
|
||||
else if (~FM_demod_en) begin
|
||||
if((cnt >= BPS_PARA-1)||(FM_demod_en)) begin
|
||||
cnt <= 6'b0;
|
||||
clk_fm_demo_sampling <= 1'b1;
|
||||
end
|
||||
else begin cnt <= cnt + 1'b1;clk_fm_demo_sampling <= 1'b0; end
|
||||
end
|
||||
else clk_fm_demo_sampling <= 1'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
@ -1,32 +1,32 @@
|
||||
`timescale 1 ps/ 1 ps
|
||||
module CortexM0_SoC_vlg_tst();
|
||||
|
||||
reg clk;
|
||||
reg RSTn;
|
||||
reg TXD;
|
||||
reg MSI_SDATA;
|
||||
reg MSI_CS;
|
||||
reg MSI_SCLK;
|
||||
|
||||
|
||||
|
||||
CortexM0_SoC i1 (
|
||||
.clk(clk),
|
||||
.RSTn(RSTn)
|
||||
);
|
||||
|
||||
initial begin
|
||||
clk = 0;
|
||||
RSTn=0;
|
||||
#100
|
||||
RSTn=1;
|
||||
|
||||
end
|
||||
|
||||
always begin
|
||||
#10 clk = ~clk;
|
||||
end
|
||||
|
||||
//glbl glbl();
|
||||
|
||||
endmodule
|
||||
`timescale 1 ps/ 1 ps
|
||||
module CortexM0_SoC_vlg_tst();
|
||||
|
||||
reg clk;
|
||||
reg RSTn;
|
||||
reg TXD;
|
||||
reg MSI_SDATA;
|
||||
reg MSI_CS;
|
||||
reg MSI_SCLK;
|
||||
|
||||
|
||||
|
||||
CortexM0_SoC i1 (
|
||||
.clk(clk),
|
||||
.RSTn(RSTn)
|
||||
);
|
||||
|
||||
initial begin
|
||||
clk = 0;
|
||||
RSTn=0;
|
||||
#100
|
||||
RSTn=1;
|
||||
|
||||
end
|
||||
|
||||
always begin
|
||||
#10 clk = ~clk;
|
||||
end
|
||||
|
||||
//glbl glbl();
|
||||
|
||||
endmodule
|
||||
|
||||
@ -50,6 +50,17 @@ unsigned int REG1=0x0000e201;
|
||||
unsigned int REG2=0x0001f2bc2;
|
||||
unsigned int REG3=0x00000003;
|
||||
ChannelControlType ChannelControlDisplay;
|
||||
ChannelControlType Profile[10];
|
||||
|
||||
void initialize()
|
||||
{
|
||||
int ii;
|
||||
float frequency[10] = {87.9,89.9,90.9,91.4,93.4,94.0,95.5,103.7,105.7,107.7};
|
||||
for (ii=1;ii<=10;ii++){
|
||||
Profile[ii-1].channel_no = ii;
|
||||
Profile[ii-1].freq = frequency[ii-1];
|
||||
}
|
||||
}
|
||||
|
||||
void ChannelSelection_control(unsigned int data)
|
||||
{
|
||||
@ -380,656 +391,54 @@ void ChannelSelection_control(unsigned int data)
|
||||
|
||||
else if(data=='1') // formal FM receiver
|
||||
{
|
||||
MSI_SPI_Data = 0x00043420; //reg 0: 24M clk
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x0028bb85; //reg5: THRESH=3000
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
REG2 = 0x210002; //Reg2: INT=33,FRAC=0 99.0MHz in Shanghai
|
||||
REG2 = 0x210002; //Reg2: INT=33,FRAC=0 99.0MHz in Shanghai
|
||||
REG2 = 0x210002; //Reg2: INT=33,FRAC=0 99.0MHz in Shanghai
|
||||
REG2 = 0x210002; //Reg2: INT=33,FRAC=0 99.0MHz in Shanghai
|
||||
REG2 = 0x210002; //Reg2: INT=33,FRAC=0 99.0MHz in Shanghai
|
||||
REG2 = 0x210002; //Reg2: INT=33,FRAC=0 99.0MHz in Shanghai
|
||||
REG2 = 0x210002; //Reg2: INT=33,FRAC=0 99.0MHz in Shanghai
|
||||
REG2 = 0x210002; //Reg2: INT=33,FRAC=0 99.0MHz in Shanghai
|
||||
REG2 = 0x210002; //Reg2: INT=33,FRAC=0 99.0MHz in Shanghai
|
||||
SPI_RFD(REG2);
|
||||
MSI_SPI_Data = 0x0000e141; //Reg1: BB Gain decrease 20dB LNA Gain redcution: 23dB
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x00200016; //Reg6: DC default value
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x00000004; //Reg4: Aux features
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
REG3 = 0x00000003; //Reg3:AFC = 0
|
||||
SPI_RFD(REG3);
|
||||
|
||||
FM_current_gain=20;
|
||||
FM_current_INT=33;
|
||||
FM_current_FRAC=1700;
|
||||
|
||||
ChannelControlDisplay.channel_no =1;
|
||||
ChannelControlDisplay.freq =99.0;
|
||||
ChannelControlDisplay.INT =FM_current_INT;
|
||||
ChannelControlDisplay.FRAC =FM_current_FRAC;
|
||||
Channel_control(ChannelControlDisplay);
|
||||
|
||||
|
||||
UARTString(" Channel: 99.0MHz ");
|
||||
WriteUART('\n');
|
||||
regWrite(Profile[0].freq);
|
||||
Channel_control(Profile[0]);
|
||||
}
|
||||
else if(data=='2') // formal FM receiver
|
||||
{
|
||||
MSI_SPI_Data = 0x00043420; //reg 0: 24M clk
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x0028bb85; //reg5: THRESH=3000
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
REG2 = 0x1e3842; //Reg2: INT=30,FRAC=900 97.7MHz in Shanghai
|
||||
REG2 = 0x1e3842; //Reg2: INT=30,FRAC=900 97.7MHz in Shanghai
|
||||
REG2 = 0x1e3842; //Reg2: INT=30,FRAC=900 97.7MHz in Shanghai
|
||||
REG2 = 0x1e3842; //Reg2: INT=30,FRAC=900 97.7MHz in Shanghai
|
||||
REG2 = 0x1e3842; //Reg2: INT=30,FRAC=900 97.7MHz in Shanghai
|
||||
REG2 = 0x1e3842; //Reg2: INT=30,FRAC=900 97.7MHz in Shanghai
|
||||
REG2 = 0x1e3842; //Reg2: INT=30,FRAC=900 97.7MHz in Shanghai
|
||||
REG2 = 0x1e3842; //Reg2: INT=30,FRAC=900 97.7MHz in Shanghai
|
||||
REG2 = 0x1e3842; //Reg2: INT=30,FRAC=900 97.7MHz in Shanghai
|
||||
SPI_RFD(REG2);
|
||||
MSI_SPI_Data = 0x0000e141; //Reg1: BB Gain decrease 20dB LNA Gain redcution: 23dB
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x00200016; //Reg6: DC default value
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x00000004; //Reg4: Aux features
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
REG3 = 0x00000003; //Reg3:AFC = 0
|
||||
SPI_RFD(REG3);
|
||||
|
||||
FM_current_gain=20;
|
||||
FM_current_INT=30;
|
||||
FM_current_FRAC=900;
|
||||
|
||||
ChannelControlDisplay.channel_no =2;
|
||||
ChannelControlDisplay.freq =90.9;
|
||||
ChannelControlDisplay.INT =FM_current_INT;
|
||||
ChannelControlDisplay.FRAC =FM_current_FRAC;
|
||||
Channel_control(ChannelControlDisplay);
|
||||
Channel_control(ChannelControlDisplay);
|
||||
Channel_control(ChannelControlDisplay);
|
||||
Channel_control(ChannelControlDisplay);
|
||||
Channel_control(ChannelControlDisplay);
|
||||
Channel_control(ChannelControlDisplay);
|
||||
Channel_control(ChannelControlDisplay);
|
||||
Channel_control(ChannelControlDisplay);
|
||||
Channel_control(ChannelControlDisplay);
|
||||
|
||||
|
||||
UARTString(" Channel: 90.9MHz ");
|
||||
WriteUART('\n');
|
||||
regWrite(Profile[1].freq);
|
||||
Channel_control(Profile[1]);
|
||||
}
|
||||
else if(data=='3') // formal FM receiver
|
||||
{
|
||||
MSI_SPI_Data = 0x00043420; //reg 0: 24M clk
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x0028bb85; //reg5: THRESH=3000
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x1f3e822; //Reg2: INT=31,FRAC=1000 96.8MHz in Shanghai
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x0000e141; //Reg1: BB Gain decrease 20dB LNA Gain redcution: 23dB
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x00200016; //Reg6: DC default value
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x00000004; //Reg4: Aux features
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x00000003; //Reg3:AFC = 0
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
|
||||
FM_current_gain=20;
|
||||
FM_current_INT=31;
|
||||
FM_current_FRAC=1000;
|
||||
|
||||
ChannelControlDisplay.channel_no =3;
|
||||
ChannelControlDisplay.freq =94.0;
|
||||
ChannelControlDisplay.INT =FM_current_INT;
|
||||
ChannelControlDisplay.FRAC =FM_current_FRAC;
|
||||
Channel_control(ChannelControlDisplay);
|
||||
|
||||
UARTString(" Channel: 94.0MHz ");
|
||||
WriteUART('\n');
|
||||
regWrite(Profile[2].freq);
|
||||
Channel_control(Profile[2]);
|
||||
}
|
||||
else if(data=='4') // formal FM receiver
|
||||
{
|
||||
MSI_SPI_Data = 0x00043420; //reg 0: 24M clk
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x0028bb85; //reg5: THRESH=3000
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x1f6a42; //Reg2: INT=31,FRAC=1700 94.7MHz in Shanghai
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x0000e141; //Reg1: BB Gain decrease 20dB LNA Gain redcution: 23dB
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x00200016; //Reg6: DC default value
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x00000004; //Reg4: Aux features
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x00000003; //Reg3:AFC = 0
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
|
||||
FM_current_gain=20;
|
||||
FM_current_INT=31;
|
||||
FM_current_FRAC=1700;
|
||||
ChannelControlDisplay.channel_no =4;
|
||||
ChannelControlDisplay.freq =94.7;
|
||||
ChannelControlDisplay.INT =FM_current_INT;
|
||||
ChannelControlDisplay.FRAC =FM_current_FRAC;
|
||||
Channel_control(ChannelControlDisplay);
|
||||
UARTString(" Channel: 94.7MHz ");
|
||||
WriteUART('\n');
|
||||
regWrite(Profile[3].freq);
|
||||
Channel_control(Profile[3]);
|
||||
}
|
||||
else if(data=='5') // formal FM receiver
|
||||
{
|
||||
MSI_SPI_Data = 0x00043420; //reg 0: 24M clk
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x0028bb85; //reg5: THRESH=3000
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x1f1902; //Reg2: INT=31,FRAC=400 93.4MHz in Shanghai
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x0000e141; //Reg1: BB Gain decrease 20dB LNA Gain redcution: 23dB
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x00200016; //Reg6: DC default value
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x00000004; //Reg4: Aux features
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x00000003; //Reg3:AFC = 0
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
|
||||
FM_current_gain=20;
|
||||
FM_current_INT=31;
|
||||
FM_current_FRAC=400;
|
||||
ChannelControlDisplay.channel_no =5;
|
||||
ChannelControlDisplay.freq =93.4;
|
||||
ChannelControlDisplay.INT =FM_current_INT;
|
||||
ChannelControlDisplay.FRAC =FM_current_FRAC;
|
||||
Channel_control(ChannelControlDisplay);
|
||||
UARTString(" Channel: 93.4MHz Shanghai 990 ");
|
||||
WriteUART('\n');
|
||||
regWrite(Profile[4].freq);
|
||||
Channel_control(Profile[4]);
|
||||
}
|
||||
else if(data=='6') // formal FM receiver
|
||||
{
|
||||
MSI_SPI_Data = 0x00043420; //reg 0: 24M clk
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x0028bb85; //reg5: THRESH=3000
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x1f9c42; //Reg2: INT=30,FRAC=2400 92.4MHz in Shanghai
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x0000e141; //Reg1: BB Gain decrease 20dB LNA Gain redcution: 23dB
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x00200016; //Reg6: DC default value
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x00000004; //Reg4: Aux features
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x00000003; //Reg3:AFC = 0
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
|
||||
FM_current_gain=20;
|
||||
FM_current_INT=30;
|
||||
FM_current_FRAC=2400;
|
||||
|
||||
ChannelControlDisplay.channel_no =6;
|
||||
ChannelControlDisplay.freq =95.5;
|
||||
ChannelControlDisplay.INT =FM_current_INT;
|
||||
ChannelControlDisplay.FRAC =FM_current_FRAC;
|
||||
Channel_control(ChannelControlDisplay);
|
||||
|
||||
UARTString(" Channel: 95.5MHz ");
|
||||
WriteUART('\n');
|
||||
regWrite(Profile[5].freq);
|
||||
Channel_control(Profile[5]);
|
||||
}
|
||||
else if(data=='7') // formal FM receiver
|
||||
{
|
||||
MSI_SPI_Data = 0x00043420; //reg 0: 24M clk
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x0028bb85; //reg5: THRESH=3000
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x1e5782; //Reg2: INT=30,FRAC=1400 91.4MHz in Shanghai
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x0000e141; //Reg1: BB Gain decrease 20dB LNA Gain redcution: 23dB
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x00200016; //Reg6: DC default value
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x00000004; //Reg4: Aux features
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x00000003; //Reg3:AFC = 0
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
|
||||
FM_current_gain=20;
|
||||
FM_current_INT=30;
|
||||
FM_current_FRAC=1400;
|
||||
|
||||
ChannelControlDisplay.channel_no =7;
|
||||
ChannelControlDisplay.freq =91.4;
|
||||
ChannelControlDisplay.INT =FM_current_INT;
|
||||
ChannelControlDisplay.FRAC =FM_current_FRAC;
|
||||
Channel_control(ChannelControlDisplay);
|
||||
|
||||
|
||||
UARTString(" Channel: CNR 91.4MHz Jingji ");
|
||||
WriteUART('\n');
|
||||
regWrite(Profile[6].freq);
|
||||
Channel_control(Profile[6]);
|
||||
}
|
||||
else if(data=='8') // formal FM receiver
|
||||
{
|
||||
MSI_SPI_Data = 0x00043420; //reg 0: 24M clk
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x0028bb85; //reg5: THRESH=3000
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x1db542; //Reg2: INT=29,FRAC=2900 89.9MHz in Shanghai
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x0000e141; //Reg1: BB Gain decrease 20dB LNA Gain redcution: 23dB
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x00200016; //Reg6: DC default value
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x00000004; //Reg4: Aux features
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x00000003; //Reg3:AFC = 0
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
|
||||
FM_current_gain=20;
|
||||
FM_current_INT=29;
|
||||
FM_current_FRAC=2900;
|
||||
|
||||
ChannelControlDisplay.channel_no =8;
|
||||
ChannelControlDisplay.freq =89.9;
|
||||
ChannelControlDisplay.INT =FM_current_INT;
|
||||
ChannelControlDisplay.FRAC =FM_current_FRAC;
|
||||
Channel_control(ChannelControlDisplay);
|
||||
|
||||
UARTString(" Channel: 89.9MHz Dushi 792 ");
|
||||
WriteUART('\n');
|
||||
regWrite(Profile[7].freq);
|
||||
Channel_control(Profile[7]);
|
||||
}
|
||||
else if(data=='9') // formal FM receiver
|
||||
{
|
||||
MSI_SPI_Data = 0x00043420; //reg 0: 24M clk
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x0028bb85; //reg5: THRESH=3000
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x1d3842; //Reg2: INT=29,FRAC=900 97.9MHz in Shanghai
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x0000e141; //Reg1: BB Gain decrease 20dB LNA Gain redcution: 23dB
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x00200016; //Reg6: DC default value
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x00000004; //Reg4: Aux features
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x00000003; //Reg3:AFC = 0
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
|
||||
FM_current_gain=20;
|
||||
FM_current_INT=29;
|
||||
FM_current_FRAC=900;
|
||||
|
||||
ChannelControlDisplay.channel_no =9;
|
||||
ChannelControlDisplay.freq =87.9;
|
||||
ChannelControlDisplay.INT =FM_current_INT;
|
||||
ChannelControlDisplay.FRAC =FM_current_FRAC;
|
||||
Channel_control(ChannelControlDisplay);
|
||||
|
||||
UARTString(" Channel: 87.9MHz CNR 87.9 ");
|
||||
WriteUART('\n');
|
||||
regWrite(Profile[8].freq);
|
||||
Channel_control(Profile[8]);
|
||||
}
|
||||
else if(data=='z') // formal FM receiver
|
||||
else if(data=='0') // formal FM receiver
|
||||
{
|
||||
MSI_SPI_Data = 0x00043420; //reg 0: 24M clk
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x0028bb85; //reg5: THRESH=3000
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x232bc2; //Reg2: INT=35,FRAC=700 105.7MHz in Shanghai
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x0000e141; //Reg1: BB Gain decrease 20dB LNA Gain redcution: 23dB
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x00200016; //Reg6: DC default value
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x00000004; //Reg4: Aux features
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x00000003; //Reg3:AFC = 0
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
|
||||
FM_current_gain=20;
|
||||
FM_current_INT=35;
|
||||
FM_current_FRAC=700;
|
||||
|
||||
ChannelControlDisplay.channel_no =10;
|
||||
ChannelControlDisplay.freq =105.7;
|
||||
ChannelControlDisplay.INT =FM_current_INT;
|
||||
ChannelControlDisplay.FRAC =FM_current_FRAC;
|
||||
Channel_control(ChannelControlDisplay);
|
||||
|
||||
|
||||
UARTString(" Channel: 105.7MHz ");
|
||||
WriteUART('\n');
|
||||
regWrite(Profile[9].freq);
|
||||
Channel_control(Profile[9]);
|
||||
}
|
||||
else if(data=='y') // formal FM receiver
|
||||
{
|
||||
MSI_SPI_Data = 0x00043420; //reg 0: 24M clk
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x0028bb85; //reg5: THRESH=3000
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x204b02; //Reg2: INT=32,FRAC=1200 97.2MHz in Shanghai
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x0000e141; //Reg1: BB Gain decrease 20dB LNA Gain redcution: 23dB
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x00200016; //Reg6: DC default value
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x00000004; //Reg4: Aux features
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x00000003; //Reg3:AFC = 0
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
|
||||
FM_current_gain=20;
|
||||
FM_current_INT=34;
|
||||
FM_current_FRAC=2500;
|
||||
|
||||
ChannelControlDisplay.channel_no =11;
|
||||
ChannelControlDisplay.freq =97.2;
|
||||
ChannelControlDisplay.INT =FM_current_INT;
|
||||
ChannelControlDisplay.FRAC =FM_current_FRAC;
|
||||
Channel_control(ChannelControlDisplay);
|
||||
|
||||
UARTString(" Channel: 97.2MHz ");
|
||||
WriteUART('\n');
|
||||
}
|
||||
else if(data=='x') // formal FM receiver
|
||||
{
|
||||
MSI_SPI_Data = 0x00043420; //reg 0: 24M clk
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x0028bb85; //reg5: THRESH=3000
|
||||
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x21a8c2; //Reg2: INT=33,FRAC=2700 101.7MHz in Shanghai
|
||||
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x0000e141; //Reg1: BB Gain decrease 20dB LNA Gain redcution: 23dB
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x00200016; //Reg6: DC default value
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x00000004; //Reg4: Aux features
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x00000003; //Reg3:AFC = 0
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
|
||||
FM_current_gain=20;
|
||||
FM_current_INT=33;
|
||||
FM_current_FRAC=2700;
|
||||
|
||||
ChannelControlDisplay.channel_no =12;
|
||||
ChannelControlDisplay.freq =101.7;
|
||||
ChannelControlDisplay.INT =FM_current_INT;
|
||||
ChannelControlDisplay.FRAC =FM_current_FRAC;
|
||||
Channel_control(ChannelControlDisplay);
|
||||
|
||||
|
||||
UARTString(" Channel: 101.7MHz Donggan 101.7 ");
|
||||
WriteUART('\n');
|
||||
}
|
||||
else if(data=='v') // formal FM receiver
|
||||
{
|
||||
MSI_SPI_Data = 0x00043420; //reg 0: 24M clk
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x0028bb85; //reg5: THRESH=3000
|
||||
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x208342; //Reg2: INT=32,FRAC=2100 101.7MHz in Shanghai
|
||||
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x0000e141; //Reg1: BB Gain decrease 20dB LNA Gain redcution: 23dB
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x00200016; //Reg6: DC default value
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x00000004; //Reg4: Aux features
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x00000003; //Reg3:AFC = 0
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
|
||||
FM_current_gain=20;
|
||||
FM_current_INT=32;
|
||||
FM_current_FRAC=2100;
|
||||
|
||||
ChannelControlDisplay.channel_no =13;
|
||||
ChannelControlDisplay.freq =98.1;
|
||||
ChannelControlDisplay.INT =FM_current_INT;
|
||||
ChannelControlDisplay.FRAC =FM_current_FRAC;
|
||||
Channel_control(ChannelControlDisplay);
|
||||
|
||||
|
||||
UARTString(" Channel: 98.1MHz ");
|
||||
WriteUART('\n');
|
||||
}
|
||||
else if(data=='w') // formal FM receiver
|
||||
{
|
||||
MSI_SPI_Data = 0x00043420; //reg 0: 24M clk
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x0028bb85; //reg5: THRESH=3000
|
||||
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x2144c2; //Reg2: INT=33,FRAC=1100 100.1MHz in Shanghai
|
||||
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x0000e141; //Reg1: BB Gain decrease 20dB LNA Gain redcution: 23dB
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x00200016; //Reg6: DC default value
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x00000004; //Reg4: Aux features
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x00000003; //Reg3:AFC = 0
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
|
||||
FM_current_gain=20;
|
||||
FM_current_INT=32;
|
||||
FM_current_FRAC=2100;
|
||||
|
||||
ChannelControlDisplay.channel_no =14;
|
||||
ChannelControlDisplay.freq =100.1;
|
||||
ChannelControlDisplay.INT =FM_current_INT;
|
||||
ChannelControlDisplay.FRAC =FM_current_FRAC;
|
||||
Channel_control(ChannelControlDisplay);
|
||||
|
||||
|
||||
UARTString(" Channel: 100.1MHz ");
|
||||
WriteUART('\n');
|
||||
}
|
||||
else if(data=='a') // formal FM receiver
|
||||
{
|
||||
MSI_SPI_Data = 0x00043420; //reg 0: 24M clk
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x0028bb85; //reg5: THRESH=3000
|
||||
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x2176c2; //Reg2: INT=33,FRAC=1900 100.9MHz in Shanghai
|
||||
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x0000e141; //Reg1: BB Gain decrease 20dB LNA Gain redcution: 23dB
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x00200016; //Reg6: DC default value
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x00000004; //Reg4: Aux features
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x00000003; //Reg3:AFC = 0
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
|
||||
FM_current_gain=20;
|
||||
FM_current_INT=33;
|
||||
FM_current_FRAC=1900;
|
||||
|
||||
ChannelControlDisplay.channel_no =15;
|
||||
ChannelControlDisplay.freq =100.9;
|
||||
ChannelControlDisplay.INT =FM_current_INT;
|
||||
ChannelControlDisplay.FRAC =FM_current_FRAC;
|
||||
Channel_control(ChannelControlDisplay);
|
||||
|
||||
|
||||
UARTString(" Channel: 100.9 MHz ");
|
||||
WriteUART('\n');
|
||||
}
|
||||
else if(data=='b') // formal FM receiver
|
||||
{
|
||||
MSI_SPI_Data = 0x00043420; //reg 0: 24M clk
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x0028bb85; //reg5: THRESH=3000
|
||||
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x226a42; //Reg2: INT=34,FRAC=1700 103.7MHz in Shanghai
|
||||
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x0000e141; //Reg1: BB Gain decrease 20dB LNA Gain redcution: 23dB
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x00200016; //Reg6: DC default value
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x00000004; //Reg4: Aux features
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x00000003; //Reg3:AFC = 0
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
|
||||
FM_current_gain=20;
|
||||
FM_current_INT=34;
|
||||
FM_current_FRAC=1700;
|
||||
|
||||
ChannelControlDisplay.channel_no =16;
|
||||
ChannelControlDisplay.freq =103.7;
|
||||
ChannelControlDisplay.INT =FM_current_INT;
|
||||
ChannelControlDisplay.FRAC =FM_current_FRAC;
|
||||
Channel_control(ChannelControlDisplay);
|
||||
|
||||
|
||||
UARTString(" Channel: 103.7 MHz ");
|
||||
WriteUART('\n');
|
||||
}
|
||||
else if(data=='c') // formal FM receiver
|
||||
{
|
||||
MSI_SPI_Data = 0x00043420; //reg 0: 24M clk
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x0028bb85; //reg5: THRESH=3000
|
||||
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x222bc2; //Reg2: INT=34,FRAC=700 102.7MHz in Shanghai
|
||||
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x0000e141; //Reg1: BB Gain decrease 20dB LNA Gain redcution: 23dB
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x00200016; //Reg6: DC default value
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x00000004; //Reg4: Aux features
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x00000003; //Reg3:AFC = 0
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
|
||||
FM_current_gain=20;
|
||||
FM_current_INT=34;
|
||||
FM_current_FRAC=700;
|
||||
|
||||
ChannelControlDisplay.channel_no =17;
|
||||
ChannelControlDisplay.freq =102.7;
|
||||
ChannelControlDisplay.INT =FM_current_INT;
|
||||
ChannelControlDisplay.FRAC =FM_current_FRAC;
|
||||
Channel_control(ChannelControlDisplay);
|
||||
|
||||
|
||||
UARTString(" Channel: 102.7 MHz ");
|
||||
WriteUART('\n');
|
||||
}
|
||||
else if(data=='d') // formal FM receiver
|
||||
{
|
||||
MSI_SPI_Data = 0x00043420; //reg 0: 24M clk
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x0028bb85; //reg5: THRESH=3000
|
||||
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x235dc2; //Reg2: INT=35,FRAC=1500 106.5MHz in Shanghai
|
||||
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x0000e141; //Reg1: BB Gain decrease 20dB LNA Gain redcution: 23dB
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x00200016; //Reg6: DC default value
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x00000004; //Reg4: Aux features
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x00000003; //Reg3:AFC = 0
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
|
||||
FM_current_gain=20;
|
||||
FM_current_INT=35;
|
||||
FM_current_FRAC=1500;
|
||||
|
||||
ChannelControlDisplay.channel_no =18;
|
||||
ChannelControlDisplay.freq =106.5;
|
||||
ChannelControlDisplay.INT =FM_current_INT;
|
||||
ChannelControlDisplay.FRAC =FM_current_FRAC;
|
||||
Channel_control(ChannelControlDisplay);
|
||||
|
||||
|
||||
UARTString(" Channel: 106.5 MHz ");
|
||||
WriteUART('\n');
|
||||
}
|
||||
else if(data=='e') // formal FM receiver
|
||||
{
|
||||
MSI_SPI_Data = 0x00043420; //reg 0: 24M clk
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x0028bb85; //reg5: THRESH=3000
|
||||
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x238982; //Reg2: INT=35,FRAC=2200 107.2MHz in Shanghai
|
||||
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x0000e141; //Reg1: BB Gain decrease 20dB LNA Gain redcution: 23dB
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x00200016; //Reg6: DC default value
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x00000004; //Reg4: Aux features
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x00000003; //Reg3:AFC = 0
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
|
||||
FM_current_gain=20;
|
||||
FM_current_INT=35;
|
||||
FM_current_FRAC=1500;
|
||||
|
||||
ChannelControlDisplay.channel_no =19;
|
||||
ChannelControlDisplay.freq =107.2;
|
||||
ChannelControlDisplay.INT =FM_current_INT;
|
||||
ChannelControlDisplay.FRAC =FM_current_FRAC;
|
||||
Channel_control(ChannelControlDisplay);
|
||||
|
||||
|
||||
UARTString(" Channel: 107.2 MHz ");
|
||||
WriteUART('\n');
|
||||
}
|
||||
else if(data=='h') // formal FM receiver
|
||||
{
|
||||
MSI_SPI_Data = 0x00043420; //reg 0: 24M clk
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x0028bb85; //reg5: THRESH=3000
|
||||
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x23a8c2; //Reg2: INT=35,FRAC=2700 107.7MHz in Shanghai
|
||||
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x0000e141; //Reg1: BB Gain decrease 20dB LNA Gain redcution: 23dB
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x00200016; //Reg6: DC default value
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x00000004; //Reg4: Aux features
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
MSI_SPI_Data = 0x00000003; //Reg3:AFC = 0
|
||||
SPI_RFD(MSI_SPI_Data);
|
||||
|
||||
FM_current_gain=20;
|
||||
FM_current_INT=35;
|
||||
FM_current_FRAC=1500;
|
||||
|
||||
ChannelControlDisplay.channel_no =20;
|
||||
ChannelControlDisplay.freq =107.7;
|
||||
ChannelControlDisplay.INT =FM_current_INT;
|
||||
ChannelControlDisplay.FRAC =FM_current_FRAC;
|
||||
Channel_control(ChannelControlDisplay);
|
||||
|
||||
|
||||
UARTString(" Channel: 107.7 MHz ");
|
||||
WriteUART('\n');
|
||||
}
|
||||
|
||||
else
|
||||
{
|
||||
UARTString(" Wrong command! ");
|
||||
|
||||
@ -13,6 +13,8 @@ float freq_I=87.0;
|
||||
RSSIType rssilist[NUM];
|
||||
int rssi_index=0;
|
||||
ChannelControlType channelcontrollist[OUTNUM];
|
||||
ChannelControlType channelcontrolmax;
|
||||
|
||||
|
||||
/*
|
||||
|
||||
@ -249,7 +251,9 @@ void RSSIScanHandler(void)
|
||||
#endif
|
||||
RSSIScanscreen();
|
||||
UARTString("Scan done!\n");
|
||||
|
||||
Start_FM_command();
|
||||
regWrite(channelcontrolmax.freq);
|
||||
Channel_control(channelcontrolmax);
|
||||
}
|
||||
}
|
||||
|
||||
@ -260,20 +264,26 @@ void RSSIScanscreen()
|
||||
freq = 87;
|
||||
i = 0;
|
||||
n = 1;
|
||||
for (k = 0; k < OUTNUM ; k++)
|
||||
{
|
||||
channelcontrollist[k].freq = 87.9;
|
||||
channelcontrollist[k].INT = channelcontrollist[i].freq / 3;
|
||||
channelcontrollist[k].FRAC = (channelcontrollist[i].freq / 3 - channelcontrollist[i].INT) * 3000;
|
||||
}
|
||||
for (j = 0; freq += STEP, j < (NUM - 10); j++)
|
||||
{
|
||||
if (rssilist[j].RSSI < Thresh)
|
||||
continue;
|
||||
if ((rssilist[j].RSSI >= rssilist[j - 12].RSSI * 4) && (rssilist[j].RSSI >= rssilist[j + 12].RSSI * 4))
|
||||
{
|
||||
for (k = 0; (k <= i) && (k < 16); k++)
|
||||
for (k = i-1; k >= 0; k--)
|
||||
if ((freq - channelcontrollist[k].freq) < 0.2)
|
||||
{
|
||||
channelcontrollist[k].freq = (channelcontrollist[k].freq * n + freq) / (n + 1);
|
||||
n += 1;
|
||||
break;
|
||||
}
|
||||
if ((k <= i) && (k < 16))
|
||||
if (k>=0)
|
||||
continue;
|
||||
else if (i == 0)
|
||||
{
|
||||
@ -281,17 +291,17 @@ void RSSIScanscreen()
|
||||
rssi[i] = rssilist[j].RSSI;
|
||||
i += 1;
|
||||
}
|
||||
else if (i < OUTNUM)
|
||||
else if (i < OUTNUM - 1)
|
||||
{
|
||||
channelcontrollist[i].freq = freq;
|
||||
rssi[i] = rssilist[j].RSSI;
|
||||
if (rssilist[j].RSSI < rssi[0])
|
||||
{
|
||||
rssi[i] = rssi[0];
|
||||
rssi[0] = rssilist[j].RSSI;
|
||||
channelcontrollist[i].freq = channelcontrollist[0].freq;
|
||||
channelcontrollist[0].freq = freq;
|
||||
i += 1;
|
||||
}
|
||||
else if (i == OUTNUM - 1)
|
||||
{
|
||||
channelcontrollist[i].freq = freq;
|
||||
rssi[i] = rssilist[j].RSSI;
|
||||
Bubbling(rssi);
|
||||
i += 1;
|
||||
}
|
||||
else if (rssilist[j].RSSI > rssi[0])
|
||||
@ -306,6 +316,7 @@ void RSSIScanscreen()
|
||||
}
|
||||
|
||||
}
|
||||
channelcontrolmax.freq = ((float)((int)((channelcontrollist[OUTNUM - 1].freq + 0.05) * 10))) / 10;
|
||||
for (i = 0; i < OUTNUM; i++)
|
||||
for (j = 1; j < (OUTNUM - i); j++)
|
||||
{
|
||||
@ -318,13 +329,74 @@ void RSSIScanscreen()
|
||||
}
|
||||
for (i = 0; i < OUTNUM; i++)
|
||||
{
|
||||
channelcontrollist[i].INT = floor(channelcontrollist[i].freq / 3);
|
||||
channelcontrollist[i].freq = ((float)((int)((channelcontrollist[i].freq + 0.05) * 10))) / 10;
|
||||
channelcontrollist[i].INT = channelcontrollist[i].freq / 3;
|
||||
channelcontrollist[i].FRAC = (channelcontrollist[i].freq / 3 - channelcontrollist[i].INT) * 3000;
|
||||
channelcontrollist[i].channel_no = i+1;
|
||||
if (channelcontrollist[i].freq == channelcontrolmax.freq)
|
||||
channelcontrolmax.channel_no = channelcontrollist[i].channel_no;
|
||||
}
|
||||
channelcontrolmax.INT = channelcontrolmax.freq / 3;
|
||||
channelcontrolmax.FRAC = (channelcontrolmax.freq / 3 - channelcontrolmax.INT) * 3000;
|
||||
}
|
||||
|
||||
int Bubbling(int* rssi)
|
||||
void RSSIScanbyfilter()
|
||||
{
|
||||
int temp;
|
||||
int i,j;
|
||||
int k = 0;
|
||||
int sum[200];
|
||||
int rssi[200];
|
||||
ChannelControlType satisfied_channelcontrollist[200];
|
||||
RSSIType satisfied_rssilist[200];
|
||||
for (i = 5, j = 0; i < 1045; i = i+5, j++){
|
||||
sum[j] = rssilist[i-4].RSSI+rssilist[i-3].RSSI+rssilist[i-2].RSSI+rssilist[i-1].RSSI+rssilist[i].RSSI+rssilist[i+1].RSSI+rssilist[i+2].RSSI+rssilist[i+3].RSSI+rssilist[i+4].RSSI;
|
||||
}
|
||||
for (j = 1; j < 199; j++){
|
||||
if(( sum[j] > Thresh*9 ) && ( sum[j-1] < sum[j] ) && ( sum[j+1] < sum[j] )){
|
||||
satisfied_rssilist[k].RSSI = rssilist[j*5+5].RSSI;
|
||||
rssi[k] = rssilist[j*5+5].RSSI;
|
||||
satisfied_rssilist[k].index = j*5 + 5;
|
||||
k++;
|
||||
}
|
||||
}
|
||||
for (k = 0; k < 200; k++){
|
||||
satisfied_channelcontrollist[k].freq = ((float)((int)((87 + (satisfied_rssilist[k].index-1) * 0.02 + 0.05) * 10))) / 10 ;
|
||||
}
|
||||
for (i = 0; i < 200; i++)
|
||||
{
|
||||
for (j = 1; j < 199; j++)
|
||||
{
|
||||
if (rssi[j] < rssi[j - 1])
|
||||
{
|
||||
temp = rssi[j];
|
||||
rssi[j] = rssi[j - 1];
|
||||
rssi[j - 1] = temp;
|
||||
temp = satisfied_channelcontrollist[j].freq;
|
||||
satisfied_channelcontrollist[j].freq = satisfied_channelcontrollist[j - 1].freq;
|
||||
satisfied_channelcontrollist[j - 1].freq = temp;
|
||||
}
|
||||
}
|
||||
}
|
||||
for (k = 0; k < 15 ; k++){
|
||||
channelcontrollist[k].freq = satisfied_channelcontrollist[k].freq ;
|
||||
channelcontrollist[k].INT = channelcontrollist[k].freq / 3;
|
||||
channelcontrollist[k].FRAC = (channelcontrollist[k].freq / 3 - channelcontrollist[k].INT) * 3000;
|
||||
channelcontrollist[k].channel_no = k+1;
|
||||
}
|
||||
for (i = 0; i < OUTNUM; i++)
|
||||
for (j = 1; j < (OUTNUM - i); j++)
|
||||
{
|
||||
if (channelcontrollist[j].freq < channelcontrollist[j - 1].freq)
|
||||
{
|
||||
temp = channelcontrollist[j].freq;
|
||||
channelcontrollist[j].freq = channelcontrollist[j - 1].freq;
|
||||
channelcontrollist[j - 1].freq = temp;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
int Bubbling(int* rssi)
|
||||
{
|
||||
int i, j, k;
|
||||
float temp;
|
||||
|
||||
@ -73,6 +73,7 @@ void RSSI_scan_cmd(void);
|
||||
void RSSIScanscreen(void);
|
||||
int Bubbling(int* rssi);
|
||||
void regWrite(float freq);
|
||||
void initialize(void);
|
||||
|
||||
//Key interrupt handlers
|
||||
void KEY0(void);
|
||||
|
||||
@ -7,7 +7,6 @@
|
||||
|
||||
int main()
|
||||
{
|
||||
NVIC_CTRL_ADDR = 0xFFFFF; //enable lowest 2 interrupts
|
||||
/*
|
||||
char string[32] = {0};
|
||||
|
||||
@ -46,9 +45,9 @@ int main()
|
||||
Start_FM_command();
|
||||
IQ_Dump_data();
|
||||
*/
|
||||
|
||||
NVIC_CTRL_ADDR = 0xFFFFF; //enable lowest 2 interrupts
|
||||
initialize();
|
||||
|
||||
|
||||
|
||||
while(1)
|
||||
{
|
||||
|
||||
75
设计需求.md
Normal file
75
设计需求.md
Normal file
@ -0,0 +1,75 @@
|
||||
# 设计需求文档
|
||||
|
||||
## RSSI 扫频算法设计
|
||||
|
||||
### RSSI分布描述
|
||||
|
||||
<img src="docs/pic/image.png"/>
|
||||
|
||||
该图为频率范围$f\in[87MHz,108MHz]$下的RSSI的对数坐标分布$RSSI_{log}=10\times\log{RSSI}$。
|
||||
|
||||
此设计的目的是**利用编写的接口函数，筛选出图中标出的频点**。
|
||||
|
||||
### 需求描述
|
||||
|
||||
#### 输入
|
||||
|
||||
##### RSSIType
|
||||
|
||||
上图中对应的RSSI数据存放在下述定义的数据结构中：
|
||||
|
||||
```c
|
||||
typedef struct{
|
||||
int index; //存放每个采样点的索引值
|
||||
int RSSI; //存放RSSI的值
|
||||
}RSSIType;
|
||||
```
|
||||
|
||||
❤**注意此处的RSSI不是图中所示的对数形式，请不要对RSSI的值进行Log运算（尽量不要进行任何运算，因为数据量大，延迟很高）。**
|
||||
|
||||
构成结构数组定义如下：
|
||||
|
||||
```C
|
||||
#define NUM 1060
|
||||
#define STEP 0.02
|
||||
RSSIType rssilist[NUM];
|
||||
```
|
||||
|
||||
不推荐更改`NUM`（数组长度设定为1060）和`STEP`（扫频步长设定为0.02MHz）的数值。由于不可名状的BUG，在第一次运行扫频函数时，`rssilist[0]`的RSSI值为0。因此可以使用的数据为`rssilist[1]`~`rssilist[1050]`共1050个RSSIType数据结构。（由于C的浮点数特性，导致频率为108时仍然可以运行扫频程序，因此会比期望的数量多一个）
|
||||
|
||||
##### 门限值Thresh
|
||||
|
||||
`RSSI>Thresh`时对应的频率才可能成为频点，**但若该门限过低，导致输出的频点多于16个时，仅输出最高的16个。**
|
||||
|
||||
#### 输出
|
||||
|
||||
观察数据规律，输出RSSI值最高的频点（**精度要求为0.1MHz**），将所有频点的频率**从小到大**存放在以下数据结构中。
|
||||
|
||||
```C
|
||||
typedef struct{
|
||||
unsigned int channel_no; //存放频道号，从1开始递增编号
|
||||
float freq; //存放频点频率
|
||||
unsigned int INT; //存放整数部分
|
||||
unsigned int FRAC; //存放小数部分
|
||||
}ChannelControlType;
|
||||
```
|
||||
|
||||
其中`INT`和`FRAC`与频率的转换公式如下：
|
||||
|
||||
```C
|
||||
int INT=floor(freq/3);
|
||||
int FRAC=(freq/3-INT)*3000;
|
||||
```
|
||||
|
||||
**可以使用提供的数据在x86平台进行测试，测试完毕后需要按照注释的位置插入相应的代码，并Build确认无报错**。
|
||||
|
||||
需要插入的部分包括：
|
||||
|
||||
`code_def.h`第73行声明函数名；
|
||||
|
||||
`code_def.c`第13行创建ChannelControlType数组（含有16个元素）全局变量；
|
||||
|
||||
`code_def.c`第239行调用函数；
|
||||
|
||||
`code_def.c`第246行完成函数构建。
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user