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update: stable version

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JefferyLi0903 2023-05-13 12:10:21 +08:00
parent ceb507a0e3
commit 9c0e1a6197
15 changed files with 1198270 additions and 734402 deletions
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19
constraints/FM_SOC.adc
View File

@ -37,3 +37,22 @@ set_pin_assignment { row[0] } { LOCATION = E10; IOSTANDARD = LVTTL33; }
set_pin_assignment { row[1] } { LOCATION = C10; IOSTANDARD = LVTTL33; }
set_pin_assignment { row[2] } { LOCATION = F9; IOSTANDARD = LVTTL33; }
set_pin_assignment { row[3] } { LOCATION = D9; IOSTANDARD = LVTTL33; }
set_pin_assignment { I2S_BCLK } { LOCATION = D14; IOSTANDARD = LVCMOS33; }
set_pin_assignment { I2S_LRCLK } { LOCATION = E15; IOSTANDARD = LVCMOS33; }
set_pin_assignment { I2S_SDATA } { LOCATION = F14; IOSTANDARD = LVCMOS33; }
set_pin_assignment { e_mdc } { LOCATION = F4; IOSTANDARD = LVCMOS33; }
set_pin_assignment { e_mdio } { LOCATION = F3; IOSTANDARD = LVCMOS33; }
set_pin_assignment { rgmii_rxc } { LOCATION = K6; IOSTANDARD = LVCMOS33; }
set_pin_assignment { rgmii_rxctl } { LOCATION = L4; IOSTANDARD = LVCMOS33; }
set_pin_assignment { rgmii_rxd[0] } { LOCATION = L3; IOSTANDARD = LVCMOS33; }
set_pin_assignment { rgmii_rxd[1] } { LOCATION = J6; IOSTANDARD = LVCMOS33; }
set_pin_assignment { rgmii_rxd[2] } { LOCATION = K3; IOSTANDARD = LVCMOS33; }
set_pin_assignment { rgmii_rxd[3] } { LOCATION = K5; IOSTANDARD = LVCMOS33; }
set_pin_assignment { rgmii_txc } { LOCATION = H3; IOSTANDARD = LVCMOS33; }
set_pin_assignment { rgmii_txctl } { LOCATION = G3; IOSTANDARD = LVCMOS33; }
set_pin_assignment { rgmii_txd[0] } { LOCATION = H5; IOSTANDARD = LVCMOS33; }
set_pin_assignment { rgmii_txd[1] } { LOCATION = G6; IOSTANDARD = LVCMOS33; }
set_pin_assignment { rgmii_txd[2] } { LOCATION = H4; IOSTANDARD = LVCMOS33; }
set_pin_assignment { rgmii_txd[3] } { LOCATION = G5; IOSTANDARD = LVCMOS33; }

6
project/MMC.al
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@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8"?>
<Project Version="1" Path="/home/jefferyli/Desktop/MMC_Temp/project">
<Project Version="1" Path="/home/jefferyli/Downloads/MMC/project">
<Project_Created_Time></Project_Created_Time>
<TD_Version>5.0.43066</TD_Version>
<UCode>11011111</UCode>
@ -82,7 +82,7 @@
<Attr Name="CompileOrder" Val="9"/>
</FileInfo>
</File>
<File Path="al_ip/PLL_PWM.v">
<File Path="../../../Desktop/MMC_Temp/project/al_ip/PLL_PWM.v">
<FileInfo>
<Attr Name="UsedInSyn" Val="true"/>
<Attr Name="UsedInP&R" Val="true"/>
@ -597,7 +597,7 @@
<Configurations>
</Configurations>
<Project_Settings>
<Step_Last_Change>2023-05-13 11:40:17.548</Step_Last_Change>
<Step_Last_Change>2023-05-13 12:09:22.435</Step_Last_Change>
<Current_Step>60</Current_Step>
<Step_Status>true</Step_Status>
</Project_Settings>

BIN
project/MMC.bit
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Binary file not shown.

52
project/MMC_gate.area
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@ -2,43 +2,47 @@ standard
***Report Model: CortexM0_SoC***
IO Statistics
#IO 39
#input 8
#output 30
#inout 1
#IO 56
#input 14
#output 40
#inout 2
LUT Statistics
#Total_luts 9828
#lut4 7291
#lut5 1581
#Total_luts 15947
#lut4 10679
#lut5 2549
#lut6 0
#lut5_mx41 0
#lut4_alu1b 956
#lut4_alu1b 2719
Utilization Statistics
#lut 9828 out of 19600 50.14%
#reg 2074 out of 19600 10.58%
#lut 15947 out of 19600 81.36%
#reg 11134 out of 19600 56.81%
#le 0
#dsp 26 out of 29 89.66%
#bram 32 out of 64 50.00%
#bram9k 32
#fifo9k 0
#dsp 13 out of 29 44.83%
#bram 39 out of 64 60.94%
#bram9k 35
#fifo9k 4
#bram32k 0 out of 16 0.00%
#dram 1040
#dram 16
#adc 1 out of 1 100.00%
#pad 39 out of 186 20.97%
#ireg 0
#oreg 0
#pad 56 out of 186 30.11%
#ireg 5
#oreg 6
#treg 0
#pll 2 out of 4 50.00%
#pll 3 out of 4 75.00%
Report Hierarchy Area:
+------------------------------------------------------------------------------+
|Instance |Module |lut |ripple |seq |bram |dsp |
+------------------------------------------------------------------------------+
|top |CortexM0_SoC |8872 |956 |2074 |32 |26 |
| FM_Display |FM_Display |180 |90 |81 |0 |0 |
| FM_HW |FM_HW |3473 |595 |391 |0 |23 |
| FM_Demodulation |FM_Demodulation |12 |422 |268 |0 |22 |
| u_logic |cortexm0ds_logic |4791 |173 |1317 |0 |3 |
|top |CortexM0_SoC |13228 |2719 |11145 |39 |13 |
| FM_HW |FM_HW |685 |1206 |693 |0 |10 |
| FM_Demodulation |FM_Demodulation |568 |1069 |593 |0 |9 |
| ethernet_i0 |ethernet_test |7140 |1152 |8777 |7 |0 |
| mac_test0 |mac_test |7015 |1105 |8675 |7 |0 |
| mac_top0 |mac_top |2377 |1066 |2192 |7 |0 |
| mac_rx0 |mac_rx_top |541 |143 |775 |0 |0 |
| mac_tx0 |mac_tx_top |1251 |604 |951 |6 |0 |
| u_logic |cortexm0ds_logic |4813 |173 |1316 |0 |3 |
+------------------------------------------------------------------------------+

95
project/MMC_inst.bid
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@ -1,6 +1,6 @@
<?xml version="1.0" encoding="UTF-8"?>
<All_Bram_Infos>
<Ucode>11100000</Ucode>
<Ucode>11011111</Ucode>
<AL_PHY_BRAM>
<INST_1>
<rid>0X0004</rid>
@ -994,5 +994,98 @@
</working_mode>
</sub_bid_info>
</INST_32>
<INST_33>
<rid>0X0024</rid>
<wid>0X0024</wid>
<is_debuggable>n</is_debuggable>
<is_initialize>n</is_initialize>
<model_type>AL_PHY_BRAM</model_type>
<name>ethernet_i0/mac_test0/mac_top0/icmp0/icmp_receive_ram/inst_256x8_sub_000000_000</name>
<width_a>9</width_a>
<width_b>9</width_b>
<logic_name>ethernet_i0/mac_test0/mac_top0/icmp0/icmp_receive_ram/inst</logic_name>
<logic_width>8</logic_width>
<logic_depth>256</logic_depth>
<sub_bid_info>
<address_offset>0</address_offset>
<data_offset>0</data_offset>
<depth>256</depth>
<width>8</width>
<num_section>1</num_section>
<section_size>8</section_size>
<width_per_section>8</width_per_section>
<bytes_in_per_section>1</bytes_in_per_section>
<working_mode>
<address_step>1</address_step>
<depth>1024</depth>
<mode_type>110</mode_type>
<width>9</width>
<num_byte>1</num_byte>
<ecc>0</ecc>
</working_mode>
</sub_bid_info>
</INST_33>
<INST_34>
<rid>0X0025</rid>
<wid>0X0025</wid>
<is_debuggable>n</is_debuggable>
<is_initialize>y</is_initialize>
<model_type>AL_PHY_BRAM</model_type>
<name>ethernet_i0/mac_test0/mac_top0/mac_tx0/udp0/udp_tx_checksum/fifo_bram_16x32_sub_000000_000</name>
<width_a>18</width_a>
<width_b>18</width_b>
<logic_name>N/A</logic_name>
<logic_width>-1</logic_width>
<logic_depth>-1</logic_depth>
<sub_bid_info>
<address_offset>-1</address_offset>
<data_offset>-1</data_offset>
<depth>-1</depth>
<width>-1</width>
<num_section>-1</num_section>
<section_size>-1</section_size>
<width_per_section>-1</width_per_section>
<bytes_in_per_section>1</bytes_in_per_section>
<working_mode>
<address_step>-1</address_step>
<depth>-1</depth>
<mode_type>110</mode_type>
<width>-1</width>
<num_byte>-1</num_byte>
<ecc>1</ecc>
</working_mode>
</sub_bid_info>
</INST_34>
<INST_35>
<rid>0X0026</rid>
<wid>0X0026</wid>
<is_debuggable>n</is_debuggable>
<is_initialize>y</is_initialize>
<model_type>AL_PHY_BRAM</model_type>
<name>ethernet_i0/mac_test0/mac_top0/mac_tx0/udp0/udp_tx_checksum/fifo_bram_16x32_sub_000000_018</name>
<width_a>18</width_a>
<width_b>18</width_b>
<logic_name>N/A</logic_name>
<logic_width>-1</logic_width>
<logic_depth>-1</logic_depth>
<sub_bid_info>
<address_offset>-1</address_offset>
<data_offset>-1</data_offset>
<depth>-1</depth>
<width>-1</width>
<num_section>-1</num_section>
<section_size>-1</section_size>
<width_per_section>-1</width_per_section>
<bytes_in_per_section>1</bytes_in_per_section>
<working_mode>
<address_step>-1</address_step>
<depth>-1</depth>
<mode_type>110</mode_type>
<width>-1</width>
<num_byte>-1</num_byte>
<ecc>1</ecc>
</working_mode>
</sub_bid_info>
</INST_35>
</AL_PHY_BRAM>
</All_Bram_Infos>

205
project/MMC_phy.area
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@ -1,94 +1,111 @@
standard
***Report Model: CortexM0_SoC***
IO Statistics
#IO 39
#input 8
#output 30
#inout 1
Utilization Statistics
#lut 17019 out of 19600 86.83%
#reg 2074 out of 19600 10.58%
#le 17133
#lut only 15059 out of 17133 87.89%
#reg only 114 out of 17133 0.67%
#lut&reg 1960 out of 17133 11.44%
#dsp 26 out of 29 89.66%
#bram 32 out of 64 50.00%
#bram9k 32
#fifo9k 0
#bram32k 0 out of 16 0.00%
#adc 1 out of 1 100.00%
#pad 39 out of 186 20.97%
#ireg 0
#oreg 0
#treg 0
#pll 2 out of 4 50.00%
#gclk 13 out of 16 81.25%
Detailed IO Report
Name Direction Location IOStandard DriveStrength PullType PackReg
RSTn INPUT A14 LVCMOS33 N/A PULLUP NONE
RXD INPUT F12 LVCMOS33 N/A PULLUP NONE
SWCLK INPUT R2 LVCMOS33 N/A PULLUP NONE
clk INPUT R7 LVCMOS33 N/A PULLUP NONE
col[3] INPUT F10 LVTTL33 N/A PULLUP NONE
col[2] INPUT C11 LVTTL33 N/A PULLUP NONE
col[1] INPUT D11 LVTTL33 N/A PULLUP NONE
col[0] INPUT E11 LVTTL33 N/A PULLUP NONE
LED[7] OUTPUT F16 LVCMOS33 8 NONE NONE
LED[6] OUTPUT E16 LVCMOS33 8 NONE NONE
LED[5] OUTPUT E13 LVCMOS33 8 NONE NONE
LED[4] OUTPUT C16 LVCMOS33 8 NONE NONE
LED[3] OUTPUT C15 LVCMOS33 8 NONE NONE
LED[2] OUTPUT B16 LVCMOS33 8 NONE NONE
LED[1] OUTPUT B15 LVCMOS33 8 NONE NONE
LED[0] OUTPUT B14 LVCMOS33 8 NONE NONE
MSI_CS OUTPUT P9 LVCMOS33 8 NONE NONE
MSI_REFCLK OUTPUT R15 LVCMOS33 8 NONE NONE
MSI_SCLK OUTPUT M9 LVCMOS33 8 NONE NONE
MSI_SDATA OUTPUT N9 LVCMOS33 8 NONE NONE
TXD OUTPUT D12 LVCMOS33 8 NONE NONE
audio_pwm OUTPUT N8 LVCMOS33 8 NONE NONE
row[3] OUTPUT D9 LVTTL33 8 NONE NONE
row[2] OUTPUT F9 LVTTL33 8 NONE NONE
row[1] OUTPUT C10 LVTTL33 8 NONE NONE
row[0] OUTPUT E10 LVTTL33 8 NONE NONE
seg[7] OUTPUT C8 LVCMOS33 8 NONE NONE
seg[6] OUTPUT A8 LVCMOS33 8 NONE NONE
seg[5] OUTPUT B5 LVCMOS33 8 NONE NONE
seg[4] OUTPUT A7 LVCMOS33 8 NONE NONE
seg[3] OUTPUT E8 LVCMOS33 8 NONE NONE
seg[2] OUTPUT B8 LVCMOS33 8 NONE NONE
seg[1] OUTPUT A6 LVCMOS33 8 NONE NONE
seg[0] OUTPUT A4 LVCMOS33 8 NONE NONE
sel[3] OUTPUT A3 LVCMOS33 8 NONE NONE
sel[2] OUTPUT A5 LVCMOS33 8 NONE NONE
sel[1] OUTPUT B6 LVCMOS33 8 NONE NONE
sel[0] OUTPUT C9 LVCMOS33 8 NONE NONE
SWDIO INOUT P2 LVCMOS33 8 PULLUP NONE
Report Hierarchy Area:
+----------------------------------------------------------------------+
|Instance |Module |le |lut |ripple |seq |bram |dsp |
+----------------------------------------------------------------------+
|top |CortexM0_SoC |17133 |16646 |373 |2074 |32 |26 |
+----------------------------------------------------------------------+
DataNet Average Fanout:
Index Fanout Nets
#1 1 15257
#2 2 10084
#3 3 525
#4 4 510
#5 5-10 633
#6 11-50 463
#7 51-100 35
#8 101-500 7
#9 >500 18
Average 3.11
standard
***Report Model: CortexM0_SoC***
IO Statistics
#IO 56
#input 14
#output 40
#inout 2
Utilization Statistics
#lut 18023 out of 19600 91.95%
#reg 11125 out of 19600 56.76%
#le 19018
#lut only 7893 out of 19018 41.50%
#reg only 995 out of 19018 5.23%
#lut&reg 10130 out of 19018 53.27%
#dsp 13 out of 29 44.83%
#bram 39 out of 64 60.94%
#bram9k 35
#fifo9k 4
#bram32k 0 out of 16 0.00%
#adc 1 out of 1 100.00%
#pad 56 out of 186 30.11%
#ireg 5
#oreg 6
#treg 0
#pll 3 out of 4 75.00%
#gclk 16 out of 16 100.00%
Detailed IO Report
Name Direction Location IOStandard DriveStrength PullType PackReg
RSTn INPUT A14 LVCMOS33 N/A PULLUP NONE
RXD INPUT F12 LVCMOS33 N/A PULLUP NONE
SWCLK INPUT R2 LVCMOS33 N/A PULLUP NONE
clk INPUT R7 LVCMOS33 N/A PULLUP NONE
col[3] INPUT F10 LVTTL33 N/A PULLUP NONE
col[2] INPUT C11 LVTTL33 N/A PULLUP NONE
col[1] INPUT D11 LVTTL33 N/A PULLUP NONE
col[0] INPUT E11 LVTTL33 N/A PULLUP NONE
rgmii_rxc INPUT K6 LVCMOS33 N/A PULLUP NONE
rgmii_rxctl INPUT L4 LVCMOS33 N/A PULLUP IDDRX1
rgmii_rxd[3] INPUT K5 LVCMOS33 N/A PULLUP IDDRX1
rgmii_rxd[2] INPUT K3 LVCMOS33 N/A PULLUP IDDRX1
rgmii_rxd[1] INPUT J6 LVCMOS33 N/A PULLUP IDDRX1
rgmii_rxd[0] INPUT L3 LVCMOS33 N/A PULLUP IDDRX1
I2S_BCLK OUTPUT D14 LVCMOS33 8 NONE NONE
I2S_LRCLK OUTPUT E15 LVCMOS33 8 NONE NONE
I2S_SDATA OUTPUT F14 LVCMOS33 8 NONE NONE
LED[7] OUTPUT F16 LVCMOS33 8 NONE NONE
LED[6] OUTPUT E16 LVCMOS33 8 NONE NONE
LED[5] OUTPUT E13 LVCMOS33 8 NONE NONE
LED[4] OUTPUT C16 LVCMOS33 8 NONE NONE
LED[3] OUTPUT C15 LVCMOS33 8 NONE NONE
LED[2] OUTPUT B16 LVCMOS33 8 NONE NONE
LED[1] OUTPUT B15 LVCMOS33 8 NONE NONE
LED[0] OUTPUT B14 LVCMOS33 8 NONE NONE
MSI_CS OUTPUT P9 LVCMOS33 8 NONE NONE
MSI_REFCLK OUTPUT R15 LVCMOS33 8 NONE NONE
MSI_SCLK OUTPUT M9 LVCMOS33 8 NONE NONE
MSI_SDATA OUTPUT N9 LVCMOS33 8 NONE NONE
TXD OUTPUT D12 LVCMOS33 8 NONE NONE
audio_pwm OUTPUT N8 LVCMOS33 8 NONE NONE
e_mdc OUTPUT F4 LVCMOS33 8 NONE NONE
rgmii_txc OUTPUT H3 LVCMOS33 8 NONE ODDRX1
rgmii_txctl OUTPUT G3 LVCMOS33 8 NONE ODDRX1
rgmii_txd[3] OUTPUT G5 LVCMOS33 8 NONE ODDRX1
rgmii_txd[2] OUTPUT H4 LVCMOS33 8 NONE ODDRX1
rgmii_txd[1] OUTPUT G6 LVCMOS33 8 NONE ODDRX1
rgmii_txd[0] OUTPUT H5 LVCMOS33 8 NONE ODDRX1
row[3] OUTPUT D9 LVTTL33 8 NONE NONE
row[2] OUTPUT F9 LVTTL33 8 NONE NONE
row[1] OUTPUT C10 LVTTL33 8 NONE NONE
row[0] OUTPUT E10 LVTTL33 8 NONE NONE
seg[7] OUTPUT C8 LVCMOS33 8 NONE NONE
seg[6] OUTPUT A8 LVCMOS33 8 NONE NONE
seg[5] OUTPUT B5 LVCMOS33 8 NONE NONE
seg[4] OUTPUT A7 LVCMOS33 8 NONE NONE
seg[3] OUTPUT E8 LVCMOS33 8 NONE NONE
seg[2] OUTPUT B8 LVCMOS33 8 NONE NONE
seg[1] OUTPUT A6 LVCMOS33 8 NONE NONE
seg[0] OUTPUT A4 LVCMOS33 8 NONE NONE
sel[3] OUTPUT A3 LVCMOS33 8 NONE NONE
sel[2] OUTPUT A5 LVCMOS33 8 NONE NONE
sel[1] OUTPUT B6 LVCMOS33 8 NONE NONE
sel[0] OUTPUT C9 LVCMOS33 8 NONE NONE
SWDIO INOUT P2 LVCMOS33 8 PULLUP NONE
e_mdio INOUT F3 LVCMOS33 8 PULLUP NONE
Report Hierarchy Area:
+----------------------------------------------------------------------+
|Instance |Module |le |lut |ripple |seq |bram |dsp |
+----------------------------------------------------------------------+
|top |CortexM0_SoC |19018 |16958 |1065 |11136 |39 |13 |
+----------------------------------------------------------------------+
DataNet Average Fanout:
Index Fanout Nets
#1 1 18736
#2 2 3732
#3 3 972
#4 4 741
#5 5-10 1038
#6 11-50 794
#7 51-100 43
#8 101-500 43
#9 >500 5
Average 3.00

2207
project/MMC_phy.timing
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File diff suppressed because it is too large Load Diff

826
project/MMC_phy.tsm
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@ -1,425 +1,401 @@
eagle_s20
12 22 1021 17132 932245162 9 0
-10.123 0.281 CortexM0_SoC eagle_s20 BG256 Detail 8 1
clock: DeriveClock
12 932245162 17132 4
Setup check
22 3
Endpoint: FM_HW/_al_u3394|FM_HW/FM_Dump_Data_IQ/reg0_b5
22 -10.123000 48096076 3
Timing path: u_logic/Wkipw6_reg|u_logic/U9ypw6_reg.clk->FM_HW/_al_u3394|FM_HW/FM_Dump_Data_IQ/reg0_b5
u_logic/Wkipw6_reg|u_logic/U9ypw6_reg.clk
FM_HW/_al_u3394|FM_HW/FM_Dump_Data_IQ/reg0_b5
24 -10.123000 19.884000 30.007000 23 23
u_logic/U9ypw6 u_logic/_al_u708|u_logic/_al_u2324.c[1]
u_logic/Ya1ju6_lutinv u_logic/_al_u2451|u_logic/_al_u2549.b[0]
u_logic/_al_u2549_o u_logic/_al_u2551|u_logic/R3vpw6_reg.a[1]
u_logic/_al_u2551_o u_logic/_al_u2552.a[1]
u_logic/_al_u2552_o u_logic/_al_u2556|u_logic/_al_u2555.a[1]
u_logic/_al_u2556_o u_logic/_al_u2563|u_logic/_al_u641.a[1]
u_logic/_al_u2563_o u_logic/_al_u2564|u_logic/_al_u411.d[1]
u_logic/_al_u2564_o u_logic/_al_u2565|u_logic/_al_u2847.d[1]
u_logic/_al_u2565_o u_logic/_al_u2566|u_logic/J0iax6_reg.d[1]
u_logic/_al_u2566_o u_logic/_al_u2641|u_logic/_al_u4457.d[1]
u_logic/Vtzhu6 u_logic/_al_u2643|u_logic/_al_u954.d[1]
u_logic/R0ghu6 u_logic/add2/ucin_al_u4809.b[0]
u_logic/add2/c3 u_logic/add2/u3_al_u4810.fci
u_logic/N5fpw6[7] u_logic/_al_u2517|u_logic/_al_u2533.d[1]
u_logic/_al_u2517_o u_logic/_al_u2518|u_logic/Vpgbx6_reg.d[1]
u_logic/_al_u2518_o RAMDATA_Interface/reg0_b6|RAMDATA_Interface/reg0_b4.b[1]
HADDR[8] FM_HW/_al_u3810|FM_HW/_al_u668.c[0]
FM_HW/_al_u668_o FM_HW/_al_u2914|FM_HW/_al_u2383.b[1]
FM_HW/_al_u2914_o FM_HW/_al_u2919.a[1]
FM_HW/_al_u2919_o FM_HW/_al_u2387|FM_HW/_al_u2923.b[0]
FM_HW/_al_u2923_o FM_HW/_al_u2944.a[1]
FM_HW/_al_u2944_o scan_unit/reg2_b15|scan_unit/reg2_b29.a[1]
FM_HW/_al_u2987_o FM_HW/_al_u3394|FM_HW/FM_Dump_Data_IQ/reg0_b5.b[0]
Timing path: u_logic/Wkipw6_reg|u_logic/U9ypw6_reg.clk->FM_HW/_al_u3394|FM_HW/FM_Dump_Data_IQ/reg0_b5
u_logic/Wkipw6_reg|u_logic/U9ypw6_reg.clk
FM_HW/_al_u3394|FM_HW/FM_Dump_Data_IQ/reg0_b5
95 -10.123000 19.884000 30.007000 23 23
u_logic/U9ypw6 u_logic/_al_u708|u_logic/_al_u2324.c[1]
u_logic/Ya1ju6_lutinv u_logic/_al_u2451|u_logic/_al_u2549.b[0]
u_logic/_al_u2549_o u_logic/_al_u2551|u_logic/R3vpw6_reg.a[1]
u_logic/_al_u2551_o u_logic/_al_u2552.a[1]
u_logic/_al_u2552_o u_logic/_al_u2556|u_logic/_al_u2555.a[1]
u_logic/_al_u2556_o u_logic/_al_u2563|u_logic/_al_u641.a[1]
u_logic/_al_u2563_o u_logic/_al_u2564|u_logic/_al_u411.d[1]
u_logic/_al_u2564_o u_logic/_al_u2565|u_logic/_al_u2847.d[1]
u_logic/_al_u2565_o u_logic/_al_u2566|u_logic/J0iax6_reg.d[1]
u_logic/_al_u2566_o u_logic/_al_u2641|u_logic/_al_u4457.d[1]
u_logic/Vtzhu6 u_logic/_al_u2643|u_logic/_al_u954.d[1]
u_logic/R0ghu6 u_logic/add2/ucin_al_u4809.b[0]
u_logic/add2/c3 u_logic/add2/u3_al_u4810.fci
u_logic/N5fpw6[7] u_logic/_al_u2517|u_logic/_al_u2533.d[1]
u_logic/_al_u2517_o u_logic/_al_u2518|u_logic/Vpgbx6_reg.d[1]
u_logic/_al_u2518_o RAMDATA_Interface/reg0_b6|RAMDATA_Interface/reg0_b4.b[1]
HADDR[8] FM_HW/_al_u3810|FM_HW/_al_u668.c[0]
FM_HW/_al_u668_o FM_HW/_al_u2914|FM_HW/_al_u2383.b[1]
FM_HW/_al_u2914_o FM_HW/_al_u2919.a[0]
FM_HW/_al_u2919_o FM_HW/_al_u2387|FM_HW/_al_u2923.b[0]
FM_HW/_al_u2923_o FM_HW/_al_u2944.a[1]
FM_HW/_al_u2944_o scan_unit/reg2_b15|scan_unit/reg2_b29.a[1]
FM_HW/_al_u2987_o FM_HW/_al_u3394|FM_HW/FM_Dump_Data_IQ/reg0_b5.b[0]
Timing path: u_logic/Wkipw6_reg|u_logic/U9ypw6_reg.clk->FM_HW/_al_u3394|FM_HW/FM_Dump_Data_IQ/reg0_b5
u_logic/Wkipw6_reg|u_logic/U9ypw6_reg.clk
FM_HW/_al_u3394|FM_HW/FM_Dump_Data_IQ/reg0_b5
166 -10.123000 19.884000 30.007000 23 23
u_logic/U9ypw6 u_logic/_al_u708|u_logic/_al_u2324.c[1]
u_logic/Ya1ju6_lutinv u_logic/_al_u2451|u_logic/_al_u2549.b[0]
u_logic/_al_u2549_o u_logic/_al_u2551|u_logic/R3vpw6_reg.a[1]
u_logic/_al_u2551_o u_logic/_al_u2552.a[1]
u_logic/_al_u2552_o u_logic/_al_u2556|u_logic/_al_u2555.a[1]
u_logic/_al_u2556_o u_logic/_al_u2563|u_logic/_al_u641.a[1]
u_logic/_al_u2563_o u_logic/_al_u2564|u_logic/_al_u411.d[1]
u_logic/_al_u2564_o u_logic/_al_u2565|u_logic/_al_u2847.d[1]
u_logic/_al_u2565_o u_logic/_al_u2566|u_logic/J0iax6_reg.d[1]
u_logic/_al_u2566_o u_logic/_al_u2641|u_logic/_al_u4457.d[1]
u_logic/Vtzhu6 u_logic/_al_u2643|u_logic/_al_u954.d[1]
u_logic/R0ghu6 u_logic/add2/ucin_al_u4809.b[0]
u_logic/add2/c3 u_logic/add2/u3_al_u4810.fci
u_logic/N5fpw6[7] u_logic/_al_u2517|u_logic/_al_u2533.d[1]
u_logic/_al_u2517_o u_logic/_al_u2518|u_logic/Vpgbx6_reg.d[1]
u_logic/_al_u2518_o RAMDATA_Interface/reg0_b6|RAMDATA_Interface/reg0_b4.b[1]
HADDR[8] FM_HW/_al_u3810|FM_HW/_al_u668.c[0]
FM_HW/_al_u668_o FM_HW/_al_u2914|FM_HW/_al_u2383.b[1]
FM_HW/_al_u2914_o FM_HW/_al_u2919.a[1]
FM_HW/_al_u2919_o FM_HW/_al_u2387|FM_HW/_al_u2923.b[0]
FM_HW/_al_u2923_o FM_HW/_al_u2944.a[0]
FM_HW/_al_u2944_o scan_unit/reg2_b15|scan_unit/reg2_b29.a[1]
FM_HW/_al_u2987_o FM_HW/_al_u3394|FM_HW/FM_Dump_Data_IQ/reg0_b5.b[0]
Endpoint: FM_HW/_al_u3595|FM_HW/FM_Dump_Data_IQ/reg0_b7
237 -9.884000 41516211 3
Timing path: u_logic/Wkipw6_reg|u_logic/U9ypw6_reg.clk->FM_HW/_al_u3595|FM_HW/FM_Dump_Data_IQ/reg0_b7
u_logic/Wkipw6_reg|u_logic/U9ypw6_reg.clk
FM_HW/_al_u3595|FM_HW/FM_Dump_Data_IQ/reg0_b7
239 -9.884000 19.884000 29.768000 23 23
u_logic/U9ypw6 u_logic/_al_u708|u_logic/_al_u2324.c[1]
u_logic/Ya1ju6_lutinv u_logic/_al_u2451|u_logic/_al_u2549.b[0]
u_logic/_al_u2549_o u_logic/_al_u2551|u_logic/R3vpw6_reg.a[1]
u_logic/_al_u2551_o u_logic/_al_u2552.a[1]
u_logic/_al_u2552_o u_logic/_al_u2556|u_logic/_al_u2555.a[1]
u_logic/_al_u2556_o u_logic/_al_u2563|u_logic/_al_u641.a[1]
u_logic/_al_u2563_o u_logic/_al_u2564|u_logic/_al_u411.d[1]
u_logic/_al_u2564_o u_logic/_al_u2565|u_logic/_al_u2847.d[1]
u_logic/_al_u2565_o u_logic/_al_u2566|u_logic/J0iax6_reg.d[1]
u_logic/_al_u2566_o u_logic/_al_u2641|u_logic/_al_u4457.d[1]
u_logic/Vtzhu6 u_logic/_al_u2643|u_logic/_al_u954.d[1]
u_logic/R0ghu6 u_logic/add2/ucin_al_u4809.b[0]
u_logic/add2/c3 u_logic/add2/u3_al_u4810.fci
u_logic/N5fpw6[7] u_logic/_al_u2517|u_logic/_al_u2533.d[1]
u_logic/_al_u2517_o u_logic/_al_u2518|u_logic/Vpgbx6_reg.d[1]
u_logic/_al_u2518_o RAMDATA_Interface/reg0_b6|RAMDATA_Interface/reg0_b4.b[1]
HADDR[8] FM_HW/_al_u3810|FM_HW/_al_u668.c[0]
FM_HW/_al_u668_o FM_HW/_al_u2046|FM_HW/_al_u3360.b[1]
FM_HW/_al_u2046_o FM_HW/_al_u2051|FM_HW/_al_u3361.a[1]
FM_HW/_al_u2051_o FM_HW/_al_u2058.b[1]
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_mux_b7/B4_8 FM_HW/_al_u2079.a[1]
FM_HW/_al_u2079_o scan_unit/reg2_b15|scan_unit/reg2_b29.a[0]
FM_HW/_al_u2123_o FM_HW/_al_u3595|FM_HW/FM_Dump_Data_IQ/reg0_b7.a[0]
Timing path: u_logic/Wkipw6_reg|u_logic/U9ypw6_reg.clk->FM_HW/_al_u3595|FM_HW/FM_Dump_Data_IQ/reg0_b7
u_logic/Wkipw6_reg|u_logic/U9ypw6_reg.clk
FM_HW/_al_u3595|FM_HW/FM_Dump_Data_IQ/reg0_b7
310 -9.884000 19.884000 29.768000 23 23
u_logic/U9ypw6 u_logic/_al_u708|u_logic/_al_u2324.c[1]
u_logic/Ya1ju6_lutinv u_logic/_al_u2451|u_logic/_al_u2549.b[0]
u_logic/_al_u2549_o u_logic/_al_u2551|u_logic/R3vpw6_reg.a[1]
u_logic/_al_u2551_o u_logic/_al_u2552.a[1]
u_logic/_al_u2552_o u_logic/_al_u2556|u_logic/_al_u2555.a[1]
u_logic/_al_u2556_o u_logic/_al_u2563|u_logic/_al_u641.a[1]
u_logic/_al_u2563_o u_logic/_al_u2564|u_logic/_al_u411.d[1]
u_logic/_al_u2564_o u_logic/_al_u2565|u_logic/_al_u2847.d[1]
u_logic/_al_u2565_o u_logic/_al_u2566|u_logic/J0iax6_reg.d[1]
u_logic/_al_u2566_o u_logic/_al_u2641|u_logic/_al_u4457.d[1]
u_logic/Vtzhu6 u_logic/_al_u2643|u_logic/_al_u954.d[1]
u_logic/R0ghu6 u_logic/add2/ucin_al_u4809.b[0]
u_logic/add2/c3 u_logic/add2/u3_al_u4810.fci
u_logic/N5fpw6[7] u_logic/_al_u2517|u_logic/_al_u2533.d[1]
u_logic/_al_u2517_o u_logic/_al_u2518|u_logic/Vpgbx6_reg.d[1]
u_logic/_al_u2518_o RAMDATA_Interface/reg0_b6|RAMDATA_Interface/reg0_b4.b[1]
HADDR[8] FM_HW/_al_u3810|FM_HW/_al_u668.c[0]
FM_HW/_al_u668_o FM_HW/_al_u2046|FM_HW/_al_u3360.b[1]
FM_HW/_al_u2046_o FM_HW/_al_u2051|FM_HW/_al_u3361.a[1]
FM_HW/_al_u2051_o FM_HW/_al_u2058.b[0]
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_mux_b7/B4_8 FM_HW/_al_u2079.a[1]
FM_HW/_al_u2079_o scan_unit/reg2_b15|scan_unit/reg2_b29.a[0]
FM_HW/_al_u2123_o FM_HW/_al_u3595|FM_HW/FM_Dump_Data_IQ/reg0_b7.a[0]
Timing path: u_logic/Wkipw6_reg|u_logic/U9ypw6_reg.clk->FM_HW/_al_u3595|FM_HW/FM_Dump_Data_IQ/reg0_b7
u_logic/Wkipw6_reg|u_logic/U9ypw6_reg.clk
FM_HW/_al_u3595|FM_HW/FM_Dump_Data_IQ/reg0_b7
381 -9.884000 19.884000 29.768000 23 23
u_logic/U9ypw6 u_logic/_al_u708|u_logic/_al_u2324.c[1]
u_logic/Ya1ju6_lutinv u_logic/_al_u2451|u_logic/_al_u2549.b[0]
u_logic/_al_u2549_o u_logic/_al_u2551|u_logic/R3vpw6_reg.a[1]
u_logic/_al_u2551_o u_logic/_al_u2552.a[1]
u_logic/_al_u2552_o u_logic/_al_u2556|u_logic/_al_u2555.a[1]
u_logic/_al_u2556_o u_logic/_al_u2563|u_logic/_al_u641.a[1]
u_logic/_al_u2563_o u_logic/_al_u2564|u_logic/_al_u411.d[1]
u_logic/_al_u2564_o u_logic/_al_u2565|u_logic/_al_u2847.d[1]
u_logic/_al_u2565_o u_logic/_al_u2566|u_logic/J0iax6_reg.d[1]
u_logic/_al_u2566_o u_logic/_al_u2641|u_logic/_al_u4457.d[1]
u_logic/Vtzhu6 u_logic/_al_u2643|u_logic/_al_u954.d[1]
u_logic/R0ghu6 u_logic/add2/ucin_al_u4809.b[0]
u_logic/add2/c3 u_logic/add2/u3_al_u4810.fci
u_logic/N5fpw6[7] u_logic/_al_u2517|u_logic/_al_u2533.d[1]
u_logic/_al_u2517_o u_logic/_al_u2518|u_logic/Vpgbx6_reg.d[1]
u_logic/_al_u2518_o RAMDATA_Interface/reg0_b6|RAMDATA_Interface/reg0_b4.b[1]
HADDR[8] FM_HW/_al_u3810|FM_HW/_al_u668.c[0]
FM_HW/_al_u668_o FM_HW/_al_u2046|FM_HW/_al_u3360.b[1]
FM_HW/_al_u2046_o FM_HW/_al_u2051|FM_HW/_al_u3361.a[1]
FM_HW/_al_u2051_o FM_HW/_al_u2058.b[1]
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_mux_b7/B4_8 FM_HW/_al_u2079.a[0]
FM_HW/_al_u2079_o scan_unit/reg2_b15|scan_unit/reg2_b29.a[0]
FM_HW/_al_u2123_o FM_HW/_al_u3595|FM_HW/FM_Dump_Data_IQ/reg0_b7.a[0]
Endpoint: FM_HW/_al_u1512|FM_HW/FM_Dump_Data_IQ/reg0_b0
452 -9.343000 45834844 3
Timing path: u_logic/Wkipw6_reg|u_logic/U9ypw6_reg.clk->FM_HW/_al_u1512|FM_HW/FM_Dump_Data_IQ/reg0_b0
u_logic/Wkipw6_reg|u_logic/U9ypw6_reg.clk
FM_HW/_al_u1512|FM_HW/FM_Dump_Data_IQ/reg0_b0
454 -9.343000 19.884000 29.227000 23 23
u_logic/U9ypw6 u_logic/_al_u708|u_logic/_al_u2324.c[1]
u_logic/Ya1ju6_lutinv u_logic/_al_u2451|u_logic/_al_u2549.b[0]
u_logic/_al_u2549_o u_logic/_al_u2551|u_logic/R3vpw6_reg.a[1]
u_logic/_al_u2551_o u_logic/_al_u2552.a[1]
u_logic/_al_u2552_o u_logic/_al_u2556|u_logic/_al_u2555.a[1]
u_logic/_al_u2556_o u_logic/_al_u2563|u_logic/_al_u641.a[1]
u_logic/_al_u2563_o u_logic/_al_u2564|u_logic/_al_u411.d[1]
u_logic/_al_u2564_o u_logic/_al_u2565|u_logic/_al_u2847.d[1]
u_logic/_al_u2565_o u_logic/_al_u2566|u_logic/J0iax6_reg.d[1]
u_logic/_al_u2566_o u_logic/_al_u2641|u_logic/_al_u4457.d[1]
u_logic/Vtzhu6 u_logic/_al_u2643|u_logic/_al_u954.d[1]
u_logic/R0ghu6 u_logic/add2/ucin_al_u4809.b[0]
u_logic/N5fpw6[3] u_logic/_al_u2521|u_logic/_al_u2614.d[0]
u_logic/_al_u2614_o u_logic/_al_u2615|u_logic/_al_u2597.d[1]
u_logic/_al_u2615_o u_logic/_al_u4348|RAMDATA_Interface/reg0_b2.b[0]
HADDR[4] FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_r443_c0_m0.c[0]
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_i443_000 FM_HW/_al_u3138|FM_HW/_al_u1898.b[0]
FM_HW/_al_u1898_o FM_HW/_al_u1899|FM_HW/_al_u2369.c[1]
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_mux_b0/B1_110 FM_HW/_al_u1902|FM_HW/_al_u1577.a[1]
FM_HW/_al_u1902_o FM_HW/_al_u3146|FM_HW/_al_u1907.a[0]
FM_HW/_al_u1907_o FM_HW/_al_u1908.c[1]
FM_HW/_al_u1908_o FM_HW/_al_u1950.a[1]
FM_HW/_al_u1950_o FM_HW/_al_u1512|FM_HW/FM_Dump_Data_IQ/reg0_b0.c[0]
Timing path: u_logic/Wkipw6_reg|u_logic/U9ypw6_reg.clk->FM_HW/_al_u1512|FM_HW/FM_Dump_Data_IQ/reg0_b0
u_logic/Wkipw6_reg|u_logic/U9ypw6_reg.clk
FM_HW/_al_u1512|FM_HW/FM_Dump_Data_IQ/reg0_b0
525 -9.343000 19.884000 29.227000 23 23
u_logic/U9ypw6 u_logic/_al_u708|u_logic/_al_u2324.c[1]
u_logic/Ya1ju6_lutinv u_logic/_al_u2451|u_logic/_al_u2549.b[0]
u_logic/_al_u2549_o u_logic/_al_u2551|u_logic/R3vpw6_reg.a[1]
u_logic/_al_u2551_o u_logic/_al_u2552.a[1]
u_logic/_al_u2552_o u_logic/_al_u2556|u_logic/_al_u2555.a[1]
u_logic/_al_u2556_o u_logic/_al_u2563|u_logic/_al_u641.a[1]
u_logic/_al_u2563_o u_logic/_al_u2564|u_logic/_al_u411.d[1]
u_logic/_al_u2564_o u_logic/_al_u2565|u_logic/_al_u2847.d[1]
u_logic/_al_u2565_o u_logic/_al_u2566|u_logic/J0iax6_reg.d[1]
u_logic/_al_u2566_o u_logic/_al_u2641|u_logic/_al_u4457.d[1]
u_logic/Vtzhu6 u_logic/_al_u2643|u_logic/_al_u954.d[1]
u_logic/R0ghu6 u_logic/add2/ucin_al_u4809.b[0]
u_logic/N5fpw6[3] u_logic/_al_u2521|u_logic/_al_u2614.d[0]
u_logic/_al_u2614_o u_logic/_al_u2615|u_logic/_al_u2597.d[1]
u_logic/_al_u2615_o u_logic/_al_u4348|RAMDATA_Interface/reg0_b2.b[0]
HADDR[4] FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_r443_c0_m0.c[0]
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_i443_000 FM_HW/_al_u3138|FM_HW/_al_u1898.b[0]
FM_HW/_al_u1898_o FM_HW/_al_u1899|FM_HW/_al_u2369.c[1]
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_mux_b0/B1_110 FM_HW/_al_u1902|FM_HW/_al_u1577.a[1]
FM_HW/_al_u1902_o FM_HW/_al_u3146|FM_HW/_al_u1907.a[0]
FM_HW/_al_u1907_o FM_HW/_al_u1908.c[0]
FM_HW/_al_u1908_o FM_HW/_al_u1950.a[1]
FM_HW/_al_u1950_o FM_HW/_al_u1512|FM_HW/FM_Dump_Data_IQ/reg0_b0.c[0]
Timing path: u_logic/Wkipw6_reg|u_logic/U9ypw6_reg.clk->FM_HW/_al_u1512|FM_HW/FM_Dump_Data_IQ/reg0_b0
u_logic/Wkipw6_reg|u_logic/U9ypw6_reg.clk
FM_HW/_al_u1512|FM_HW/FM_Dump_Data_IQ/reg0_b0
596 -9.343000 19.884000 29.227000 23 23
u_logic/U9ypw6 u_logic/_al_u708|u_logic/_al_u2324.c[1]
u_logic/Ya1ju6_lutinv u_logic/_al_u2451|u_logic/_al_u2549.b[0]
u_logic/_al_u2549_o u_logic/_al_u2551|u_logic/R3vpw6_reg.a[1]
u_logic/_al_u2551_o u_logic/_al_u2552.a[1]
u_logic/_al_u2552_o u_logic/_al_u2556|u_logic/_al_u2555.a[1]
u_logic/_al_u2556_o u_logic/_al_u2563|u_logic/_al_u641.a[1]
u_logic/_al_u2563_o u_logic/_al_u2564|u_logic/_al_u411.d[1]
u_logic/_al_u2564_o u_logic/_al_u2565|u_logic/_al_u2847.d[1]
u_logic/_al_u2565_o u_logic/_al_u2566|u_logic/J0iax6_reg.d[1]
u_logic/_al_u2566_o u_logic/_al_u2641|u_logic/_al_u4457.d[1]
u_logic/Vtzhu6 u_logic/_al_u2643|u_logic/_al_u954.d[1]
u_logic/R0ghu6 u_logic/add2/ucin_al_u4809.b[0]
u_logic/N5fpw6[3] u_logic/_al_u2521|u_logic/_al_u2614.d[0]
u_logic/_al_u2614_o u_logic/_al_u2615|u_logic/_al_u2597.d[1]
u_logic/_al_u2615_o u_logic/_al_u4348|RAMDATA_Interface/reg0_b2.b[0]
HADDR[4] FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_r443_c0_m0.c[0]
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_i443_000 FM_HW/_al_u3138|FM_HW/_al_u1898.b[0]
FM_HW/_al_u1898_o FM_HW/_al_u1899|FM_HW/_al_u2369.c[1]
FM_HW/FM_Dump_Data_IQ/al_ram_mem_IQ_do_mux_b0/B1_110 FM_HW/_al_u1902|FM_HW/_al_u1577.a[1]
FM_HW/_al_u1902_o FM_HW/_al_u3146|FM_HW/_al_u1907.a[0]
FM_HW/_al_u1907_o FM_HW/_al_u1908.c[1]
FM_HW/_al_u1908_o FM_HW/_al_u1950.a[0]
FM_HW/_al_u1950_o FM_HW/_al_u1512|FM_HW/FM_Dump_Data_IQ/reg0_b0.c[0]
Hold check
667 3
Endpoint: UART_TX/FIFO/al_ram_mem_c1_l
669 0.284000 95 3
Timing path: UART_TX/FIFO/reg1_b1|UART_TX/FIFO/reg1_b3.clk->UART_TX/FIFO/al_ram_mem_c1_l
UART_TX/FIFO/reg1_b1|UART_TX/FIFO/reg1_b3.clk
UART_TX/FIFO/al_ram_mem_c1_l
671 0.284000 0.134000 0.418000 1 1
UART_TX/FIFO/wp[3] UART_TX/FIFO/al_ram_mem_c1_l.d[0]
Timing path: _al_u240|UART_Interface/wr_en_reg_reg.clk->UART_TX/FIFO/al_ram_mem_c1_l
_al_u240|UART_Interface/wr_en_reg_reg.clk
UART_TX/FIFO/al_ram_mem_c1_l
698 1.092000 0.134000 1.226000 2 2
UART_Interface/wr_en_reg _al_u121|UART_RX/counter_en_reg.d[1]
UART_TX_data[7] UART_TX/FIFO/al_ram_mem_c1_l.d[1]
Timing path: u_logic/_al_u3982|u_logic/Wvgax6_reg.clk->UART_TX/FIFO/al_ram_mem_c1_l
u_logic/_al_u3982|u_logic/Wvgax6_reg.clk
UART_TX/FIFO/al_ram_mem_c1_l
727 3.031000 0.134000 3.165000 3 3
u_logic/Wvgax6 u_logic/_al_u4365|u_logic/Yqzax6_reg.c[0]
HWDATA[7] _al_u121|UART_RX/counter_en_reg.c[1]
UART_TX_data[7] UART_TX/FIFO/al_ram_mem_c1_l.d[1]
Endpoint: RAM_DATA/ram_mem_unify_al_u30_4096x8_sub_000000_006
758 0.293000 12 3
Timing path: RAMDATA_Interface/reg0_b6|RAMDATA_Interface/reg0_b4.clk->RAM_DATA/ram_mem_unify_al_u30_4096x8_sub_000000_006
RAMDATA_Interface/reg0_b6|RAMDATA_Interface/reg0_b4.clk
RAM_DATA/ram_mem_unify_al_u30_4096x8_sub_000000_006
760 0.293000 0.200000 0.493000 0 1
RAMDATA_WADDR[6] RAM_DATA/ram_mem_unify_al_u30_4096x8_sub_000000_006.addra[7]
Timing path: u_logic/_al_u2784|RAMDATA_Interface/reg0_b8.clk->RAM_DATA/ram_mem_unify_al_u30_4096x8_sub_000000_006
u_logic/_al_u2784|RAMDATA_Interface/reg0_b8.clk
RAM_DATA/ram_mem_unify_al_u30_4096x8_sub_000000_006
787 0.351000 0.200000 0.551000 0 1
RAMDATA_WADDR[8] RAM_DATA/ram_mem_unify_al_u30_4096x8_sub_000000_006.addra[9]
Timing path: RAMDATA_Interface/reg0_b6|RAMDATA_Interface/reg0_b4.clk->RAM_DATA/ram_mem_unify_al_u30_4096x8_sub_000000_006
RAMDATA_Interface/reg0_b6|RAMDATA_Interface/reg0_b4.clk
RAM_DATA/ram_mem_unify_al_u30_4096x8_sub_000000_006
814 0.414000 0.200000 0.614000 0 1
RAMDATA_WADDR[4] RAM_DATA/ram_mem_unify_al_u30_4096x8_sub_000000_006.addra[5]
Endpoint: UART_TX/FIFO/al_ram_mem_c1_l
841 0.295000 94 3
Timing path: UART_TX/FIFO/reg1_b0|UART_TX/FIFO/reg1_b2.clk->UART_TX/FIFO/al_ram_mem_c1_l
UART_TX/FIFO/reg1_b0|UART_TX/FIFO/reg1_b2.clk
UART_TX/FIFO/al_ram_mem_c1_l
843 0.295000 0.134000 0.429000 1 1
UART_TX/FIFO/wp[2] UART_TX/FIFO/al_ram_mem_c1_l.c[0]
Timing path: _al_u240|UART_Interface/wr_en_reg_reg.clk->UART_TX/FIFO/al_ram_mem_c1_l
_al_u240|UART_Interface/wr_en_reg_reg.clk
UART_TX/FIFO/al_ram_mem_c1_l
870 1.299000 0.134000 1.433000 2 2
UART_Interface/wr_en_reg _al_u123|UART_RX/reg2_b5.d[1]
UART_TX_data[6] UART_TX/FIFO/al_ram_mem_c1_l.c[1]
Timing path: u_logic/_al_u3982|u_logic/Wvgax6_reg.clk->UART_TX/FIFO/al_ram_mem_c1_l
u_logic/_al_u3982|u_logic/Wvgax6_reg.clk
UART_TX/FIFO/al_ram_mem_c1_l
899 2.761000 0.134000 2.895000 3 3
u_logic/Wvgax6 u_logic/_al_u3441|u_logic/Z9abx6_reg.d[0]
HWDATA[6] _al_u123|UART_RX/reg2_b5.c[1]
UART_TX_data[6] UART_TX/FIFO/al_ram_mem_c1_l.c[1]
Recovery check
930 3
Endpoint: u_logic/_al_u3646|u_logic/X5ibx6_reg
932 16.782000 1 1
Timing path: u_logic/_al_u1562|cpuresetn_reg.clk->u_logic/_al_u3646|u_logic/X5ibx6_reg
u_logic/_al_u1562|cpuresetn_reg.clk
u_logic/_al_u3646|u_logic/X5ibx6_reg
934 16.782000 19.700000 2.918000 0 1
cpuresetn u_logic/_al_u3646|u_logic/X5ibx6_reg.sr
Endpoint: u_logic/_al_u2354|u_logic/O4hax6_reg
961 16.894000 1 1
Timing path: u_logic/_al_u1562|cpuresetn_reg.clk->u_logic/_al_u2354|u_logic/O4hax6_reg
u_logic/_al_u1562|cpuresetn_reg.clk
u_logic/_al_u2354|u_logic/O4hax6_reg
963 16.894000 19.700000 2.806000 0 1
cpuresetn u_logic/_al_u2354|u_logic/O4hax6_reg.sr
Endpoint: u_logic/_al_u4735|u_logic/Knhax6_reg
990 16.894000 1 1
Timing path: u_logic/_al_u1562|cpuresetn_reg.clk->u_logic/_al_u4735|u_logic/Knhax6_reg
u_logic/_al_u1562|cpuresetn_reg.clk
u_logic/_al_u4735|u_logic/Knhax6_reg
992 16.894000 19.700000 2.806000 0 1
cpuresetn u_logic/_al_u4735|u_logic/Knhax6_reg.sr
Removal check
1019 3
Endpoint: u_logic/I5xax6_reg|u_logic/R9yax6_reg
1021 0.281000 1 1
Timing path: u_logic/_al_u1562|cpuresetn_reg.clk->u_logic/I5xax6_reg|u_logic/R9yax6_reg
u_logic/_al_u1562|cpuresetn_reg.clk
u_logic/I5xax6_reg|u_logic/R9yax6_reg
1023 0.281000 0.300000 0.581000 0 1
cpuresetn u_logic/I5xax6_reg|u_logic/R9yax6_reg.sr
Endpoint: u_logic/_al_u2275|u_logic/Yzspw6_reg
1050 0.314000 1 1
Timing path: u_logic/_al_u1562|cpuresetn_reg.clk->u_logic/_al_u2275|u_logic/Yzspw6_reg
u_logic/_al_u1562|cpuresetn_reg.clk
u_logic/_al_u2275|u_logic/Yzspw6_reg
1052 0.314000 0.300000 0.614000 0 1
cpuresetn u_logic/_al_u2275|u_logic/Yzspw6_reg.sr
Endpoint: u_logic/_al_u3169|u_logic/C1wpw6_reg
1079 0.461000 1 1
Timing path: u_logic/_al_u1562|cpuresetn_reg.clk->u_logic/_al_u3169|u_logic/C1wpw6_reg
u_logic/_al_u1562|cpuresetn_reg.clk
u_logic/_al_u3169|u_logic/C1wpw6_reg
1081 0.461000 0.300000 0.761000 0 1
cpuresetn u_logic/_al_u3169|u_logic/C1wpw6_reg.sr
Timing group statistics:
Clock constraints:
Clock Name Min Period Max Freq Skew Fanout TNS
DeriveClock (50.0MHz) 30.123ns 33MHz 0.000ns 2544 -630.003ns
Minimum input arrival time before clock: no constraint path
Maximum output required time after clock: no constraint path
Maximum combinational path delay: no constraint path
Warning: No clock constraint on 13 clock net(s):
CW_CLK_MSI
FM_Display/clk_1KHz
FM_HW/ADC_CLK
FM_HW/CW_CLK
FM_HW/EOC
FM_HW/FM_Demodulation/EOC_Count_Demodulate
FM_HW/FM_RSSI_SCAN/EOC_Count_Demodulate
FM_HW/clk_PWM1
FM_HW/clk_fm_demo_sampling
MSI_REFCLK_pad
clk_pad
scan_unit/scan_clk
u_logic/SWCLKTCK_pad
eagle_s20
12 22 597 34090 1000000000 9 0
-9.076 0.229 CortexM0_SoC eagle_s20 BG256 Detail 8 1
clock: DeriveClock
12 1000000000 34090 5
Setup check
22 3
Endpoint: u_logic/Vgjpw6_reg
22 -9.076000 13863737 3
Timing path: u_logic/M6kax6_reg.clk->u_logic/Vgjpw6_reg
u_logic/M6kax6_reg.clk
u_logic/Vgjpw6_reg
24 -9.076000 19.884000 28.960000 19 19
u_logic/M6kax6 u_logic/_al_u182|u_logic/_al_u192.b[1]
u_logic/Wanow6_lutinv u_logic/_al_u239|u_logic/Ljwax6_reg.a[1]
u_logic/_al_u239_o u_logic/_al_u219|u_logic/Llwax6_reg.c[0]
u_logic/S90iu6 u_logic/_al_u242|u_logic/_al_u272.d[1]
u_logic/Mifpw6[18] u_logic/mult0_1_0_.a[0]
u_logic/mult0_1_0_0 u_logic/u1/u0|u1/ucin.a[1]
u_logic/n135[0] u_logic/u2/u0|u2/ucin.b[1]
u_logic/u2/c1 u_logic/u2/u2|u2/u1.fci
u_logic/n159[1] u_logic/_al_u3820|u_logic/_al_u3738.d[0]
u_logic/_al_u3738_o u_logic/_al_u3739|u_logic/_al_u3824.b[1]
u_logic/_al_u3739_o u_logic/_al_u3740.c[1]
u_logic/Y4miu6 u_logic/_al_u3741|u_logic/W7max6_reg.c[1]
u_logic/_al_u3741_o u_logic/_al_u3746|u_logic/Wdmax6_reg.b[1]
u_logic/_al_u3746_o u_logic/_al_u3773|u_logic/_al_u3816.a[1]
u_logic/_al_u3773_o u_logic/_al_u3866|u_logic/_al_u3823.a[1]
u_logic/_al_u3866_o u_logic/_al_u3681|u_logic/_al_u3941.b[0]
u_logic/_al_u3941_o u_logic/_al_u3942.a[1]
u_logic/_al_u3942_o u_logic/_al_u4026.a[1]
u_logic/_al_u4026_o u_logic/Vgjpw6_reg.a[1]
Timing path: u_logic/M6kax6_reg.clk->u_logic/Vgjpw6_reg
u_logic/M6kax6_reg.clk
u_logic/Vgjpw6_reg
87 -9.076000 19.884000 28.960000 19 19
u_logic/M6kax6 u_logic/_al_u182|u_logic/_al_u192.b[1]
u_logic/Wanow6_lutinv u_logic/_al_u239|u_logic/Ljwax6_reg.a[1]
u_logic/_al_u239_o u_logic/_al_u219|u_logic/Llwax6_reg.c[0]
u_logic/S90iu6 u_logic/_al_u242|u_logic/_al_u272.d[1]
u_logic/Mifpw6[18] u_logic/mult0_1_0_.a[0]
u_logic/mult0_1_0_0 u_logic/u1/u0|u1/ucin.a[1]
u_logic/n135[0] u_logic/u2/u0|u2/ucin.b[1]
u_logic/u2/c1 u_logic/u2/u2|u2/u1.fci
u_logic/n159[1] u_logic/_al_u3820|u_logic/_al_u3738.d[0]
u_logic/_al_u3738_o u_logic/_al_u3739|u_logic/_al_u3824.b[1]
u_logic/_al_u3739_o u_logic/_al_u3740.c[1]
u_logic/Y4miu6 u_logic/_al_u3741|u_logic/W7max6_reg.c[1]
u_logic/_al_u3741_o u_logic/_al_u3746|u_logic/Wdmax6_reg.b[1]
u_logic/_al_u3746_o u_logic/_al_u3773|u_logic/_al_u3816.a[1]
u_logic/_al_u3773_o u_logic/_al_u3866|u_logic/_al_u3823.a[1]
u_logic/_al_u3866_o u_logic/_al_u3681|u_logic/_al_u3941.b[0]
u_logic/_al_u3941_o u_logic/_al_u3942.a[1]
u_logic/_al_u3942_o u_logic/_al_u4026.a[0]
u_logic/_al_u4026_o u_logic/Vgjpw6_reg.a[1]
Timing path: u_logic/M6kax6_reg.clk->u_logic/Vgjpw6_reg
u_logic/M6kax6_reg.clk
u_logic/Vgjpw6_reg
150 -9.076000 19.884000 28.960000 19 19
u_logic/M6kax6 u_logic/_al_u182|u_logic/_al_u192.b[1]
u_logic/Wanow6_lutinv u_logic/_al_u239|u_logic/Ljwax6_reg.a[1]
u_logic/_al_u239_o u_logic/_al_u219|u_logic/Llwax6_reg.c[0]
u_logic/S90iu6 u_logic/_al_u242|u_logic/_al_u272.d[1]
u_logic/Mifpw6[18] u_logic/mult0_1_0_.a[0]
u_logic/mult0_1_0_0 u_logic/u1/u0|u1/ucin.a[1]
u_logic/n135[0] u_logic/u2/u0|u2/ucin.b[1]
u_logic/u2/c1 u_logic/u2/u2|u2/u1.fci
u_logic/n159[1] u_logic/_al_u3820|u_logic/_al_u3738.d[0]
u_logic/_al_u3738_o u_logic/_al_u3739|u_logic/_al_u3824.b[1]
u_logic/_al_u3739_o u_logic/_al_u3740.c[1]
u_logic/Y4miu6 u_logic/_al_u3741|u_logic/W7max6_reg.c[1]
u_logic/_al_u3741_o u_logic/_al_u3746|u_logic/Wdmax6_reg.b[1]
u_logic/_al_u3746_o u_logic/_al_u3773|u_logic/_al_u3816.a[1]
u_logic/_al_u3773_o u_logic/_al_u3866|u_logic/_al_u3823.a[1]
u_logic/_al_u3866_o u_logic/_al_u3681|u_logic/_al_u3941.b[0]
u_logic/_al_u3941_o u_logic/_al_u3942.a[1]
u_logic/_al_u3942_o u_logic/_al_u4026.a[1]
u_logic/_al_u4026_o u_logic/Vgjpw6_reg.a[0]
Endpoint: u_logic/_al_u2303|u_logic/Ydopw6_reg
213 -8.671000 3466379 3
Timing path: u_logic/M6kax6_reg.clk->u_logic/_al_u2303|u_logic/Ydopw6_reg
u_logic/M6kax6_reg.clk
u_logic/_al_u2303|u_logic/Ydopw6_reg
215 -8.671000 19.884000 28.555000 19 19
u_logic/M6kax6 u_logic/_al_u182|u_logic/_al_u192.b[1]
u_logic/Wanow6_lutinv u_logic/_al_u239|u_logic/Ljwax6_reg.a[1]
u_logic/_al_u239_o u_logic/_al_u219|u_logic/Llwax6_reg.c[0]
u_logic/S90iu6 u_logic/_al_u242|u_logic/_al_u272.d[1]
u_logic/Mifpw6[18] u_logic/mult0_1_0_.a[0]
u_logic/mult0_1_0_0 u_logic/u1/u0|u1/ucin.a[1]
u_logic/n135[0] u_logic/u2/u0|u2/ucin.b[1]
u_logic/u2/c1 u_logic/u2/u2|u2/u1.fci
u_logic/n159[1] u_logic/_al_u3820|u_logic/_al_u3738.d[0]
u_logic/_al_u3738_o u_logic/_al_u3739|u_logic/_al_u3824.b[1]
u_logic/_al_u3739_o u_logic/_al_u3740.c[1]
u_logic/Y4miu6 u_logic/_al_u3741|u_logic/W7max6_reg.c[1]
u_logic/_al_u3741_o u_logic/_al_u3746|u_logic/Wdmax6_reg.b[1]
u_logic/_al_u3746_o u_logic/_al_u3773|u_logic/_al_u3816.a[1]
u_logic/_al_u3773_o u_logic/_al_u3866|u_logic/_al_u3823.a[1]
u_logic/_al_u3866_o u_logic/_al_u3681|u_logic/_al_u3941.b[0]
u_logic/_al_u3941_o u_logic/_al_u3942.a[1]
u_logic/_al_u3942_o u_logic/_al_u3977|u_logic/_al_u1507.a[1]
u_logic/_al_u3977_o u_logic/_al_u2303|u_logic/Ydopw6_reg.a[0]
Timing path: u_logic/M6kax6_reg.clk->u_logic/_al_u2303|u_logic/Ydopw6_reg
u_logic/M6kax6_reg.clk
u_logic/_al_u2303|u_logic/Ydopw6_reg
278 -8.671000 19.884000 28.555000 19 19
u_logic/M6kax6 u_logic/_al_u182|u_logic/_al_u192.b[1]
u_logic/Wanow6_lutinv u_logic/_al_u239|u_logic/Ljwax6_reg.a[1]
u_logic/_al_u239_o u_logic/_al_u219|u_logic/Llwax6_reg.c[0]
u_logic/S90iu6 u_logic/_al_u242|u_logic/_al_u272.d[1]
u_logic/Mifpw6[18] u_logic/mult0_1_0_.a[0]
u_logic/mult0_1_0_0 u_logic/u1/u0|u1/ucin.a[1]
u_logic/n135[0] u_logic/u2/u0|u2/ucin.b[1]
u_logic/u2/c1 u_logic/u2/u2|u2/u1.fci
u_logic/n159[1] u_logic/_al_u3820|u_logic/_al_u3738.d[0]
u_logic/_al_u3738_o u_logic/_al_u3739|u_logic/_al_u3824.b[1]
u_logic/_al_u3739_o u_logic/_al_u3740.c[0]
u_logic/Y4miu6 u_logic/_al_u3741|u_logic/W7max6_reg.c[1]
u_logic/_al_u3741_o u_logic/_al_u3746|u_logic/Wdmax6_reg.b[1]
u_logic/_al_u3746_o u_logic/_al_u3773|u_logic/_al_u3816.a[1]
u_logic/_al_u3773_o u_logic/_al_u3866|u_logic/_al_u3823.a[1]
u_logic/_al_u3866_o u_logic/_al_u3681|u_logic/_al_u3941.b[0]
u_logic/_al_u3941_o u_logic/_al_u3942.a[1]
u_logic/_al_u3942_o u_logic/_al_u3977|u_logic/_al_u1507.a[1]
u_logic/_al_u3977_o u_logic/_al_u2303|u_logic/Ydopw6_reg.a[0]
Timing path: u_logic/M6kax6_reg.clk->u_logic/_al_u2303|u_logic/Ydopw6_reg
u_logic/M6kax6_reg.clk
u_logic/_al_u2303|u_logic/Ydopw6_reg
341 -8.671000 19.884000 28.555000 19 19
u_logic/M6kax6 u_logic/_al_u182|u_logic/_al_u192.b[1]
u_logic/Wanow6_lutinv u_logic/_al_u239|u_logic/Ljwax6_reg.a[1]
u_logic/_al_u239_o u_logic/_al_u219|u_logic/Llwax6_reg.c[0]
u_logic/S90iu6 u_logic/_al_u242|u_logic/_al_u272.d[1]
u_logic/Mifpw6[18] u_logic/mult0_1_0_.a[0]
u_logic/mult0_1_0_0 u_logic/u1/u0|u1/ucin.a[1]
u_logic/n135[0] u_logic/u2/u0|u2/ucin.b[1]
u_logic/u2/c1 u_logic/u2/u2|u2/u1.fci
u_logic/n159[1] u_logic/_al_u3820|u_logic/_al_u3738.d[0]
u_logic/_al_u3738_o u_logic/_al_u3739|u_logic/_al_u3824.b[1]
u_logic/_al_u3739_o u_logic/_al_u3740.c[1]
u_logic/Y4miu6 u_logic/_al_u3741|u_logic/W7max6_reg.c[1]
u_logic/_al_u3741_o u_logic/_al_u3746|u_logic/Wdmax6_reg.b[1]
u_logic/_al_u3746_o u_logic/_al_u3773|u_logic/_al_u3816.a[1]
u_logic/_al_u3773_o u_logic/_al_u3866|u_logic/_al_u3823.a[1]
u_logic/_al_u3866_o u_logic/_al_u3681|u_logic/_al_u3941.b[0]
u_logic/_al_u3941_o u_logic/_al_u3942.a[0]
u_logic/_al_u3942_o u_logic/_al_u3977|u_logic/_al_u1507.a[1]
u_logic/_al_u3977_o u_logic/_al_u2303|u_logic/Ydopw6_reg.a[0]
Endpoint: u_logic/Jvvpw6_reg
404 -5.988000 2982027 3
Timing path: u_logic/_al_u1478|u_logic/Htmpw6_reg.clk->u_logic/Jvvpw6_reg
u_logic/_al_u1478|u_logic/Htmpw6_reg.clk
u_logic/Jvvpw6_reg
406 -5.988000 19.884000 25.872000 18 20
u_logic/Htmpw6 u_logic/_al_u745|u_logic/_al_u1128.a[0]
u_logic/Qiqow6 u_logic/_al_u1193|u_logic/Exypw6_reg.a[1]
u_logic/_al_u1193_o u_logic/_al_u1405|u_logic/_al_u1194.a[0]
u_logic/_al_u1194_o u_logic/T80qw6_reg|u_logic/Tk0qw6_reg.a[0]
u_logic/_al_u1195_o u_logic/Odnax6_reg|u_logic/S1nax6_reg.a[0]
u_logic/_al_u1197_o u_logic/_al_u1701|u_logic/_al_u1641.a[0]
u_logic/Zu6ju6 u_logic/_al_u1643|u_logic/_al_u3843.d[1]
u_logic/S2epw6 u_logic/add3_add4/u7_al_u4816.a[0]
u_logic/add3_add4/c11 u_logic/add3_add4/u11_al_u4817.fci
u_logic/add3_add4/c15 u_logic/add3_add4/u15_al_u4818.fci
u_logic/add3_add4/c19 u_logic/add3_add4/u19_al_u4819.fci
u_logic/Nxkbx6[23] u_logic/_al_u2504|u_logic/_al_u2496.d[1]
u_logic/Me6pw6 u_logic/_al_u2484|u_logic/_al_u2505.d[0]
u_logic/_al_u2505_o u_logic/N3hbx6_reg|u_logic/Tsdbx6_reg.a[1]
u_logic/_al_u3543_o u_logic/_al_u3637|u_logic/Dk9bx6_reg.d[0]
u_logic/_al_u3544_o u_logic/Gkeax6_reg|u_logic/Hpbbx6_reg.a[1]
u_logic/_al_u3546_o u_logic/Dmeax6_reg|u_logic/Daebx6_reg.a[1]
u_logic/_al_u3550_o u_logic/_al_u3186|u_logic/Tfcax6_reg.b[0]
u_logic/_al_u3559_o u_logic/Tceax6_reg|u_logic/C1fax6_reg.a[1]
u_logic/Dx7iu6 u_logic/Jvvpw6_reg.a[1]
Timing path: u_logic/_al_u1478|u_logic/Htmpw6_reg.clk->u_logic/Jvvpw6_reg
u_logic/_al_u1478|u_logic/Htmpw6_reg.clk
u_logic/Jvvpw6_reg
471 -5.988000 19.884000 25.872000 18 20
u_logic/Htmpw6 u_logic/_al_u745|u_logic/_al_u1128.a[0]
u_logic/Qiqow6 u_logic/_al_u1193|u_logic/Exypw6_reg.a[1]
u_logic/_al_u1193_o u_logic/_al_u1405|u_logic/_al_u1194.a[0]
u_logic/_al_u1194_o u_logic/T80qw6_reg|u_logic/Tk0qw6_reg.a[0]
u_logic/_al_u1195_o u_logic/Odnax6_reg|u_logic/S1nax6_reg.a[0]
u_logic/_al_u1197_o u_logic/_al_u1701|u_logic/_al_u1641.a[0]
u_logic/Zu6ju6 u_logic/_al_u1643|u_logic/_al_u3843.d[1]
u_logic/S2epw6 u_logic/add3_add4/u7_al_u4816.a[0]
u_logic/add3_add4/c11 u_logic/add3_add4/u11_al_u4817.fci
u_logic/add3_add4/c15 u_logic/add3_add4/u15_al_u4818.fci
u_logic/add3_add4/c19 u_logic/add3_add4/u19_al_u4819.fci
u_logic/Nxkbx6[23] u_logic/_al_u2504|u_logic/_al_u2496.d[1]
u_logic/Me6pw6 u_logic/_al_u2484|u_logic/_al_u2505.d[0]
u_logic/_al_u2505_o u_logic/N3hbx6_reg|u_logic/Tsdbx6_reg.a[1]
u_logic/_al_u3543_o u_logic/_al_u3637|u_logic/Dk9bx6_reg.d[0]
u_logic/_al_u3544_o u_logic/Gkeax6_reg|u_logic/Hpbbx6_reg.a[1]
u_logic/_al_u3546_o u_logic/Dmeax6_reg|u_logic/Daebx6_reg.a[1]
u_logic/_al_u3550_o u_logic/_al_u3186|u_logic/Tfcax6_reg.b[0]
u_logic/_al_u3559_o u_logic/Tceax6_reg|u_logic/C1fax6_reg.a[1]
u_logic/Dx7iu6 u_logic/Jvvpw6_reg.a[0]
Timing path: u_logic/Hirpw6_reg.clk->u_logic/Jvvpw6_reg
u_logic/Hirpw6_reg.clk
u_logic/Jvvpw6_reg
536 -5.967000 19.884000 25.851000 17 17
u_logic/Hirpw6 u_logic/_al_u160|u_logic/_al_u664.c[0]
u_logic/Frziu6_lutinv u_logic/_al_u665.b[1]
u_logic/_al_u665_o u_logic/_al_u667|u_logic/_al_u910.a[1]
u_logic/_al_u667_o u_logic/_al_u1474|u_logic/_al_u673.a[0]
u_logic/_al_u673_o u_logic/_al_u783|u_logic/Eotax6_reg.b[1]
u_logic/_al_u783_o u_logic/_al_u784|u_logic/_al_u791.d[1]
u_logic/Idfpw6[17] u_logic/add3_add4/u15_al_u4818.d[1]
u_logic/add3_add4/c19 u_logic/add3_add4/u19_al_u4819.fci
u_logic/Nxkbx6[23] u_logic/_al_u2504|u_logic/_al_u2496.d[1]
u_logic/Me6pw6 u_logic/_al_u2484|u_logic/_al_u2505.d[0]
u_logic/_al_u2505_o u_logic/N3hbx6_reg|u_logic/Tsdbx6_reg.a[1]
u_logic/_al_u3543_o u_logic/_al_u3637|u_logic/Dk9bx6_reg.d[0]
u_logic/_al_u3544_o u_logic/Gkeax6_reg|u_logic/Hpbbx6_reg.a[1]
u_logic/_al_u3546_o u_logic/Dmeax6_reg|u_logic/Daebx6_reg.a[1]
u_logic/_al_u3550_o u_logic/_al_u3186|u_logic/Tfcax6_reg.b[0]
u_logic/_al_u3559_o u_logic/Tceax6_reg|u_logic/C1fax6_reg.a[1]
u_logic/Dx7iu6 u_logic/Jvvpw6_reg.a[1]
Hold check
595 3
Endpoint: RAM_DATA/ram_mem_unify_al_u30_4096x8_sub_000000_000
597 0.229000 12 3
Timing path: RAMDATA_Interface/reg0_b4|RAMDATA_Interface/reg0_b10.clk->RAM_DATA/ram_mem_unify_al_u30_4096x8_sub_000000_000
RAMDATA_Interface/reg0_b4|RAMDATA_Interface/reg0_b10.clk
RAM_DATA/ram_mem_unify_al_u30_4096x8_sub_000000_000
599 0.229000 0.200000 0.429000 0 1
RAMDATA_WADDR[10] RAM_DATA/ram_mem_unify_al_u30_4096x8_sub_000000_000.addra[11]
Timing path: RAMDATA_Interface/reg0_b5|RAMDATA_Interface/reg0_b2.clk->RAM_DATA/ram_mem_unify_al_u30_4096x8_sub_000000_000
RAMDATA_Interface/reg0_b5|RAMDATA_Interface/reg0_b2.clk
RAM_DATA/ram_mem_unify_al_u30_4096x8_sub_000000_000
626 0.229000 0.200000 0.429000 0 1
RAMDATA_WADDR[5] RAM_DATA/ram_mem_unify_al_u30_4096x8_sub_000000_000.addra[6]
Timing path: RAMDATA_Interface/reg0_b4|RAMDATA_Interface/reg0_b10.clk->RAM_DATA/ram_mem_unify_al_u30_4096x8_sub_000000_000
RAMDATA_Interface/reg0_b4|RAMDATA_Interface/reg0_b10.clk
RAM_DATA/ram_mem_unify_al_u30_4096x8_sub_000000_000
653 0.341000 0.200000 0.541000 0 1
RAMDATA_WADDR[4] RAM_DATA/ram_mem_unify_al_u30_4096x8_sub_000000_000.addra[5]
Endpoint: RAM_DATA/ram_mem_unify_al_u30_4096x8_sub_000000_006
680 0.271000 12 3
Timing path: RAMDATA_Interface/reg0_b11|RAMDATA_Interface/reg0_b8.clk->RAM_DATA/ram_mem_unify_al_u30_4096x8_sub_000000_006
RAMDATA_Interface/reg0_b11|RAMDATA_Interface/reg0_b8.clk
RAM_DATA/ram_mem_unify_al_u30_4096x8_sub_000000_006
682 0.271000 0.200000 0.471000 0 1
RAMDATA_WADDR[8] RAM_DATA/ram_mem_unify_al_u30_4096x8_sub_000000_006.addra[9]
Timing path: RAMDATA_Interface/reg0_b5|RAMDATA_Interface/reg0_b2.clk->RAM_DATA/ram_mem_unify_al_u30_4096x8_sub_000000_006
RAMDATA_Interface/reg0_b5|RAMDATA_Interface/reg0_b2.clk
RAM_DATA/ram_mem_unify_al_u30_4096x8_sub_000000_006
709 0.375000 0.200000 0.575000 0 1
RAMDATA_WADDR[5] RAM_DATA/ram_mem_unify_al_u30_4096x8_sub_000000_006.addra[6]
Timing path: RAMDATA_Interface/reg0_b6|RAMDATA_Interface/reg0_b7.clk->RAM_DATA/ram_mem_unify_al_u30_4096x8_sub_000000_006
RAMDATA_Interface/reg0_b6|RAMDATA_Interface/reg0_b7.clk
RAM_DATA/ram_mem_unify_al_u30_4096x8_sub_000000_006
736 0.411000 0.200000 0.611000 0 1
RAMDATA_WADDR[7] RAM_DATA/ram_mem_unify_al_u30_4096x8_sub_000000_006.addra[8]
Endpoint: RAM_CODE/ram_mem_unify_al_u20_4096x8_sub_000000_000
763 0.280000 12 3
Timing path: u_logic/_al_u1539|RAMCODE_Interface/reg0_b5.clk->RAM_CODE/ram_mem_unify_al_u20_4096x8_sub_000000_000
u_logic/_al_u1539|RAMCODE_Interface/reg0_b5.clk
RAM_CODE/ram_mem_unify_al_u20_4096x8_sub_000000_000
765 0.280000 0.200000 0.480000 0 1
RAMCODE_WADDR[5] RAM_CODE/ram_mem_unify_al_u20_4096x8_sub_000000_000.addra[6]
Timing path: RAMCODE_Interface/reg0_b7|RAMCODE_Interface/reg0_b3.clk->RAM_CODE/ram_mem_unify_al_u20_4096x8_sub_000000_000
RAMCODE_Interface/reg0_b7|RAMCODE_Interface/reg0_b3.clk
RAM_CODE/ram_mem_unify_al_u20_4096x8_sub_000000_000
792 0.439000 0.200000 0.639000 0 1
RAMCODE_WADDR[7] RAM_CODE/ram_mem_unify_al_u20_4096x8_sub_000000_000.addra[8]
Timing path: RAMCODE_Interface/reg0_b0|RAMCODE_Interface/reg0_b1.clk->RAM_CODE/ram_mem_unify_al_u20_4096x8_sub_000000_000
RAMCODE_Interface/reg0_b0|RAMCODE_Interface/reg0_b1.clk
RAM_CODE/ram_mem_unify_al_u20_4096x8_sub_000000_000
819 0.448000 0.200000 0.648000 0 1
RAMCODE_WADDR[1] RAM_CODE/ram_mem_unify_al_u20_4096x8_sub_000000_000.addra[2]
Recovery check
846 3
Endpoint: u_logic/Qf4bx6_reg|u_logic/Sh4bx6_reg
848 16.555000 1 1
Timing path: u_logic/_al_u4349|cpuresetn_reg.clk->u_logic/Qf4bx6_reg|u_logic/Sh4bx6_reg
u_logic/_al_u4349|cpuresetn_reg.clk
u_logic/Qf4bx6_reg|u_logic/Sh4bx6_reg
850 16.555000 19.700000 3.145000 0 1
cpuresetn u_logic/Qf4bx6_reg|u_logic/Sh4bx6_reg.sr
Endpoint: SPI_TX/reg0_b7|SPI_TX/reg0_b3
877 16.877000 1 1
Timing path: u_logic/_al_u4349|cpuresetn_reg.clk->SPI_TX/reg0_b7|SPI_TX/reg0_b3
u_logic/_al_u4349|cpuresetn_reg.clk
SPI_TX/reg0_b7|SPI_TX/reg0_b3
879 16.877000 19.700000 2.823000 0 1
cpuresetn SPI_TX/reg0_b7|SPI_TX/reg0_b3.sr
Endpoint: SPI_TX/reg0_b11|SPI_TX/reg0_b12
906 16.877000 1 1
Timing path: u_logic/_al_u4349|cpuresetn_reg.clk->SPI_TX/reg0_b11|SPI_TX/reg0_b12
u_logic/_al_u4349|cpuresetn_reg.clk
SPI_TX/reg0_b11|SPI_TX/reg0_b12
908 16.877000 19.700000 2.823000 0 1
cpuresetn SPI_TX/reg0_b11|SPI_TX/reg0_b12.sr
Removal check
935 3
Endpoint: u_logic/_al_u134|u_logic/Dqkbx6_reg
937 0.281000 1 1
Timing path: u_logic/Hwhpw6_reg|u_logic/Kxhpw6_reg.clk->u_logic/_al_u134|u_logic/Dqkbx6_reg
u_logic/Hwhpw6_reg|u_logic/Kxhpw6_reg.clk
u_logic/_al_u134|u_logic/Dqkbx6_reg
939 0.281000 0.300000 0.581000 0 1
u_logic/Kxhpw6 u_logic/_al_u134|u_logic/Dqkbx6_reg.sr
Endpoint: u_logic/_al_u1045|u_logic/T82qw6_reg
966 0.281000 1 1
Timing path: u_logic/Hwhpw6_reg|u_logic/Kxhpw6_reg.clk->u_logic/_al_u1045|u_logic/T82qw6_reg
u_logic/Hwhpw6_reg|u_logic/Kxhpw6_reg.clk
u_logic/_al_u1045|u_logic/T82qw6_reg
968 0.281000 0.300000 0.581000 0 1
u_logic/Kxhpw6 u_logic/_al_u1045|u_logic/T82qw6_reg.sr
Endpoint: u_logic/_al_u1021|u_logic/Hpcbx6_reg
995 0.281000 1 1
Timing path: u_logic/Hwhpw6_reg|u_logic/Kxhpw6_reg.clk->u_logic/_al_u1021|u_logic/Hpcbx6_reg
u_logic/Hwhpw6_reg|u_logic/Kxhpw6_reg.clk
u_logic/_al_u1021|u_logic/Hpcbx6_reg
997 0.281000 0.300000 0.581000 0 1
u_logic/Kxhpw6 u_logic/_al_u1021|u_logic/Hpcbx6_reg.sr
Period check
1024 4
Endpoint: ethernet_i0/mac_test0/mac_top0/mac_tx0/udp0/tx_data_fifo/fifo_inst_3_.clkw
1028 16.700000 1 0
Endpoint: ethernet_i0/mac_test0/mac_top0/mac_tx0/udp0/tx_data_fifo/fifo_inst_2_.clkw
1029 16.700000 1 0
Endpoint: ethernet_i0/mac_test0/mac_top0/mac_tx0/udp0/tx_data_fifo/fifo_inst_1_.clkw
1030 16.700000 1 0
Endpoint: ethernet_i0/mac_test0/mac_top0/mac_tx0/udp0/tx_data_fifo/fifo_inst_0_.clkw
1031 16.700000 1 0
Timing group statistics:
Clock constraints:
Clock Name Min Period Max Freq Skew Fanout TNS
DeriveClock (50.0MHz) 29.076ns 34MHz 0.000ns 6999 -697.928ns
Minimum input arrival time before clock: no constraint path
Maximum output required time after clock: no constraint path
Maximum combinational path delay: no constraint path
Warning: No clock constraint on 16 clock net(s):
CW_CLK_MSI
FM_HW/ADC_CLK
FM_HW/CW_CLK
FM_HW/EOC
FM_HW/FM_Demodulation/EOC_Count_Demodulate
FM_HW/FM_Demodulation/I2S_BCLK_pad
FM_HW/FM_RSSI_SCAN/EOC_Count_Demodulate
FM_HW/clk_PWM_160
FM_HW/clk_PWM_256
FM_HW/clk_fm_demo_sampling
MSI_REFCLK_pad
clk_fm_ethernet
clk_pad
ethernet_i0/gmii_rx_clk
scan_unit/scan_clk
u_logic/SWCLKTCK_pad

173
project/MMC_place.area
View File

@ -1,78 +1,95 @@
standard
***Report Model: CortexM0_SoC***
IO Statistics
#IO 39
#input 8
#output 30
#inout 1
Utilization Statistics
#lut 16271 out of 19600 83.02%
#reg 2074 out of 19600 10.58%
#le 16397
#lut only 14323 out of 16397 87.35%
#reg only 126 out of 16397 0.77%
#lut&reg 1948 out of 16397 11.88%
#dsp 26 out of 29 89.66%
#bram 32 out of 64 50.00%
#bram9k 32
#fifo9k 0
#bram32k 0 out of 16 0.00%
#adc 1 out of 1 100.00%
#pad 39 out of 186 20.97%
#ireg 0
#oreg 0
#treg 0
#pll 2 out of 4 50.00%
Detailed IO Report
Name Direction Location IOStandard DriveStrength PullType PackReg
RSTn INPUT A14 LVCMOS33 N/A PULLUP NONE
RXD INPUT F12 LVCMOS33 N/A PULLUP NONE
SWCLK INPUT R2 LVCMOS33 N/A PULLUP NONE
clk INPUT R7 LVCMOS33 N/A PULLUP NONE
col[3] INPUT F10 LVTTL33 N/A PULLUP NONE
col[2] INPUT C11 LVTTL33 N/A PULLUP NONE
col[1] INPUT D11 LVTTL33 N/A PULLUP NONE
col[0] INPUT E11 LVTTL33 N/A PULLUP NONE
LED[7] OUTPUT F16 LVCMOS33 8 NONE NONE
LED[6] OUTPUT E16 LVCMOS33 8 NONE NONE
LED[5] OUTPUT E13 LVCMOS33 8 NONE NONE
LED[4] OUTPUT C16 LVCMOS33 8 NONE NONE
LED[3] OUTPUT C15 LVCMOS33 8 NONE NONE
LED[2] OUTPUT B16 LVCMOS33 8 NONE NONE
LED[1] OUTPUT B15 LVCMOS33 8 NONE NONE
LED[0] OUTPUT B14 LVCMOS33 8 NONE NONE
MSI_CS OUTPUT P9 LVCMOS33 8 NONE NONE
MSI_REFCLK OUTPUT R15 LVCMOS33 8 NONE NONE
MSI_SCLK OUTPUT M9 LVCMOS33 8 NONE NONE
MSI_SDATA OUTPUT N9 LVCMOS33 8 NONE NONE
TXD OUTPUT D12 LVCMOS33 8 NONE NONE
audio_pwm OUTPUT N8 LVCMOS33 8 NONE NONE
row[3] OUTPUT D9 LVTTL33 8 NONE NONE
row[2] OUTPUT F9 LVTTL33 8 NONE NONE
row[1] OUTPUT C10 LVTTL33 8 NONE NONE
row[0] OUTPUT E10 LVTTL33 8 NONE NONE
seg[7] OUTPUT C8 LVCMOS33 8 NONE NONE
seg[6] OUTPUT A8 LVCMOS33 8 NONE NONE
seg[5] OUTPUT B5 LVCMOS33 8 NONE NONE
seg[4] OUTPUT A7 LVCMOS33 8 NONE NONE
seg[3] OUTPUT E8 LVCMOS33 8 NONE NONE
seg[2] OUTPUT B8 LVCMOS33 8 NONE NONE
seg[1] OUTPUT A6 LVCMOS33 8 NONE NONE
seg[0] OUTPUT A4 LVCMOS33 8 NONE NONE
sel[3] OUTPUT A3 LVCMOS33 8 NONE NONE
sel[2] OUTPUT A5 LVCMOS33 8 NONE NONE
sel[1] OUTPUT B6 LVCMOS33 8 NONE NONE
sel[0] OUTPUT C9 LVCMOS33 8 NONE NONE
SWDIO INOUT P2 LVCMOS33 8 PULLUP NONE
Report Hierarchy Area:
+----------------------------------------------------------------------+
|Instance |Module |le |lut |ripple |seq |bram |dsp |
+----------------------------------------------------------------------+
|top |CortexM0_SoC |16397 |15898 |373 |2074 |32 |26 |
+----------------------------------------------------------------------+
standard
***Report Model: CortexM0_SoC***
IO Statistics
#IO 56
#input 14
#output 40
#inout 2
Utilization Statistics
#lut 16033 out of 19600 81.80%
#reg 11125 out of 19600 56.76%
#le 17848
#lut only 6723 out of 17848 37.67%
#reg only 1815 out of 17848 10.17%
#lut&reg 9310 out of 17848 52.16%
#dsp 13 out of 29 44.83%
#bram 39 out of 64 60.94%
#bram9k 35
#fifo9k 4
#bram32k 0 out of 16 0.00%
#adc 1 out of 1 100.00%
#pad 56 out of 186 30.11%
#ireg 5
#oreg 6
#treg 0
#pll 3 out of 4 75.00%
Detailed IO Report
Name Direction Location IOStandard DriveStrength PullType PackReg
RSTn INPUT A14 LVCMOS33 N/A PULLUP NONE
RXD INPUT F12 LVCMOS33 N/A PULLUP NONE
SWCLK INPUT R2 LVCMOS33 N/A PULLUP NONE
clk INPUT R7 LVCMOS33 N/A PULLUP NONE
col[3] INPUT F10 LVTTL33 N/A PULLUP NONE
col[2] INPUT C11 LVTTL33 N/A PULLUP NONE
col[1] INPUT D11 LVTTL33 N/A PULLUP NONE
col[0] INPUT E11 LVTTL33 N/A PULLUP NONE
rgmii_rxc INPUT K6 LVCMOS33 N/A PULLUP NONE
rgmii_rxctl INPUT L4 LVCMOS33 N/A PULLUP IDDRX1
rgmii_rxd[3] INPUT K5 LVCMOS33 N/A PULLUP IDDRX1
rgmii_rxd[2] INPUT K3 LVCMOS33 N/A PULLUP IDDRX1
rgmii_rxd[1] INPUT J6 LVCMOS33 N/A PULLUP IDDRX1
rgmii_rxd[0] INPUT L3 LVCMOS33 N/A PULLUP IDDRX1
I2S_BCLK OUTPUT D14 LVCMOS33 8 NONE NONE
I2S_LRCLK OUTPUT E15 LVCMOS33 8 NONE NONE
I2S_SDATA OUTPUT F14 LVCMOS33 8 NONE NONE
LED[7] OUTPUT F16 LVCMOS33 8 NONE NONE
LED[6] OUTPUT E16 LVCMOS33 8 NONE NONE
LED[5] OUTPUT E13 LVCMOS33 8 NONE NONE
LED[4] OUTPUT C16 LVCMOS33 8 NONE NONE
LED[3] OUTPUT C15 LVCMOS33 8 NONE NONE
LED[2] OUTPUT B16 LVCMOS33 8 NONE NONE
LED[1] OUTPUT B15 LVCMOS33 8 NONE NONE
LED[0] OUTPUT B14 LVCMOS33 8 NONE NONE
MSI_CS OUTPUT P9 LVCMOS33 8 NONE NONE
MSI_REFCLK OUTPUT R15 LVCMOS33 8 NONE NONE
MSI_SCLK OUTPUT M9 LVCMOS33 8 NONE NONE
MSI_SDATA OUTPUT N9 LVCMOS33 8 NONE NONE
TXD OUTPUT D12 LVCMOS33 8 NONE NONE
audio_pwm OUTPUT N8 LVCMOS33 8 NONE NONE
e_mdc OUTPUT F4 LVCMOS33 8 NONE NONE
rgmii_txc OUTPUT H3 LVCMOS33 8 NONE ODDRX1
rgmii_txctl OUTPUT G3 LVCMOS33 8 NONE ODDRX1
rgmii_txd[3] OUTPUT G5 LVCMOS33 8 NONE ODDRX1
rgmii_txd[2] OUTPUT H4 LVCMOS33 8 NONE ODDRX1
rgmii_txd[1] OUTPUT G6 LVCMOS33 8 NONE ODDRX1
rgmii_txd[0] OUTPUT H5 LVCMOS33 8 NONE ODDRX1
row[3] OUTPUT D9 LVTTL33 8 NONE NONE
row[2] OUTPUT F9 LVTTL33 8 NONE NONE
row[1] OUTPUT C10 LVTTL33 8 NONE NONE
row[0] OUTPUT E10 LVTTL33 8 NONE NONE
seg[7] OUTPUT C8 LVCMOS33 8 NONE NONE
seg[6] OUTPUT A8 LVCMOS33 8 NONE NONE
seg[5] OUTPUT B5 LVCMOS33 8 NONE NONE
seg[4] OUTPUT A7 LVCMOS33 8 NONE NONE
seg[3] OUTPUT E8 LVCMOS33 8 NONE NONE
seg[2] OUTPUT B8 LVCMOS33 8 NONE NONE
seg[1] OUTPUT A6 LVCMOS33 8 NONE NONE
seg[0] OUTPUT A4 LVCMOS33 8 NONE NONE
sel[3] OUTPUT A3 LVCMOS33 8 NONE NONE
sel[2] OUTPUT A5 LVCMOS33 8 NONE NONE
sel[1] OUTPUT B6 LVCMOS33 8 NONE NONE
sel[0] OUTPUT C9 LVCMOS33 8 NONE NONE
SWDIO INOUT P2 LVCMOS33 8 PULLUP NONE
e_mdio INOUT F3 LVCMOS33 8 PULLUP NONE
Report Hierarchy Area:
+----------------------------------------------------------------------+
|Instance |Module |le |lut |ripple |seq |bram |dsp |
+----------------------------------------------------------------------+
|top |CortexM0_SoC |17848 |14968 |1065 |11136 |39 |13 |
+----------------------------------------------------------------------+

56
project/MMC_rtl.area
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@ -2,39 +2,51 @@ standard
***Report Model: CortexM0_SoC***
IO Statistics
#IO 39
#input 8
#output 30
#inout 1
#IO 56
#input 14
#output 40
#inout 2
Gate Statistics
#Basic gates 21235
#and 9763
#Basic gates 32783
#and 10581
#nand 0
#or 2092
#or 2244
#nor 0
#xor 76
#xor 537
#xnor 0
#buf 0
#not 6669
#bufif1 1
#MX21 547
#not 7499
#bufif1 2
#MX21 760
#FADD 0
#DFF 2087
#DFF 11160
#LATCH 0
#MACRO_ADD 66
#MACRO_EQ 112
#MACRO_MULT 26
#MACRO_MUX 626
#MACRO_OTHERS 13
#MACRO_ADD 190
#MACRO_EQ 312
#MACRO_MULT 16
#MACRO_MUX 3181
#MACRO_OTHERS 27
LUT Statistics
#Total_luts 5
#lut4 0
#lut5 0
#lut6 0
#lut5_mx41 0
#lut4_alu1b 5
Report Hierarchy Area:
+--------------------------------------------------------------+
|Instance |Module |gates |seq |macros |
+--------------------------------------------------------------+
|top |CortexM0_SoC |19148 |2087 |217 |
| FM_Display |FM_Display |45 |81 |38 |
| FM_HW |FM_HW |105 |403 |85 |
| FM_Demodulation |FM_Demodulation |7 |280 |49 |
| u_logic |cortexm0ds_logic |18681 |1318 |14 |
|top |CortexM0_SoC |21623 |11160 |545 |
| FM_HW |FM_HW |576 |693 |101 |
| FM_Demodulation |FM_Demodulation |498 |593 |73 |
| ethernet_i0 |ethernet_test |2016 |8791 |312 |
| mac_test0 |mac_test |2004 |8698 |285 |
| mac_top0 |mac_top |1394 |2214 |267 |
| mac_rx0 |mac_rx_top |509 |775 |103 |
| mac_tx0 |mac_tx_top |666 |973 |113 |
| u_logic |cortexm0ds_logic |18669 |1317 |14 |
+--------------------------------------------------------------+

545726
project/simulation/MMC.sdf
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386175
project/simulation/MMC_gate_sim.v
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425459
project/simulation/MMC_phy_sim.v
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425461
project/simulation/MMC_phy_sim_sta.v
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File diff suppressed because it is too large Load Diff

146212
project/simulation/MMC_rtl_sim.v
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