diff --git a/rtl/demodulation/FM_HW.v b/rtl/demodulation/FM_HW.v
index 274bb82..fc3761d 100644
--- a/rtl/demodulation/FM_HW.v
+++ b/rtl/demodulation/FM_HW.v
@@ -85,7 +85,7 @@ PLL_Demodulation U1  //use final adc clk 200Khz
         .clk1_out(ADC_CLK), //ADC工作时钟,6.4M
         .clk2_out(clk_PWM1),           //20M
         .clk4_out(clk_PWM2)          //40M
-
+    );
 `endif
 
 //ADC通道4,6轮询
diff --git a/rtl/peripherals/UART_RX.v b/rtl/peripherals/UART_RX.v
index 7cec981..2fb5dbc 100644
--- a/rtl/peripherals/UART_RX.v
+++ b/rtl/peripherals/UART_RX.v
@@ -25,7 +25,7 @@ module UART_RX (
     always@(posedge clk or negedge RSTn) begin
         if(~RSTn) counter_en <= 1'b0;
         else if(re_start&&(~counter_en)) counter_en <= 1'b1;
-        else if(counter == 4'h9) counter_en <= 1'b0;ß
+        else if(counter == 4'h9) counter_en <= 1'b0;
     end
 
     always@(posedge clk or negedge RSTn) begin