From 94f321c753c50b4058365c5acbec608446ba202d Mon Sep 17 00:00:00 2001
From: JefferyLi0903 <JefferyLi0903@outlook.com>
Date: Sat, 6 May 2023 14:20:27 +0800
Subject: [PATCH 1/2] fix: bugs

---
 rtl/demodulation/FM_HW.v  | 2 +-
 rtl/peripherals/UART_RX.v | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/rtl/demodulation/FM_HW.v b/rtl/demodulation/FM_HW.v
index 274bb82..fc3761d 100644
--- a/rtl/demodulation/FM_HW.v
+++ b/rtl/demodulation/FM_HW.v
@@ -85,7 +85,7 @@ PLL_Demodulation U1  //use final adc clk 200Khz
         .clk1_out(ADC_CLK), //ADC工作时钟,6.4M
         .clk2_out(clk_PWM1),           //20M
         .clk4_out(clk_PWM2)          //40M
-
+    );
 `endif
 
 //ADC通道4,6轮询
diff --git a/rtl/peripherals/UART_RX.v b/rtl/peripherals/UART_RX.v
index 7cec981..2fb5dbc 100644
--- a/rtl/peripherals/UART_RX.v
+++ b/rtl/peripherals/UART_RX.v
@@ -25,7 +25,7 @@ module UART_RX (
     always@(posedge clk or negedge RSTn) begin
         if(~RSTn) counter_en <= 1'b0;
         else if(re_start&&(~counter_en)) counter_en <= 1'b1;
-        else if(counter == 4'h9) counter_en <= 1'b0;ß
+        else if(counter == 4'h9) counter_en <= 1'b0;
     end
 
     always@(posedge clk or negedge RSTn) begin

From 85359906f9492dceed339896c293a90031b05680 Mon Sep 17 00:00:00 2001
From: JefferyLi0903 <JefferyLi0903@outlook.com>
Date: Sat, 6 May 2023 14:21:43 +0800
Subject: [PATCH 2/2] fix: style & bugs

---
 rtl/peripherals/Block_RAM.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/rtl/peripherals/Block_RAM.v b/rtl/peripherals/Block_RAM.v
index aa303ac..654e76c 100644
--- a/rtl/peripherals/Block_RAM.v
+++ b/rtl/peripherals/Block_RAM.v
@@ -12,7 +12,7 @@ module Block_RAM #(
 (* ram_style="block" *)reg [31:0] mem [(2**(ADDR_WIDTH))-1:0];
 
 initial begin
-    $readmemh("D:/Documents/MMC/keil/MMC.hex",mem);end
+    $readmemh("../keil/MMC.hex",mem);end
 
 always@(posedge clka) begin
     if(wea[0]) mem[addra][7:0] <= dina[7:0];