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Merge commit '85359906f9492dceed339896c293a90031b05680'

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JefferyLi0903 2023-05-06 14:25:54 +08:00
commit ace5b90d8b
2 changed files with 2 additions and 2 deletions
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2
rtl/demodulation/FM_HW.v
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@ -85,7 +85,7 @@ PLL_Demodulation U1 //use final adc clk 200Khz
.clk1_out(ADC_CLK), //ADC工作时钟,6.4M .clk1_out(ADC_CLK), //ADC工作时钟,6.4M
.clk2_out(clk_PWM1), //20M .clk2_out(clk_PWM1), //20M
.clk4_out(clk_PWM2) //40M .clk4_out(clk_PWM2) //40M
);
`endif `endif
//ADC通道4,6轮询 //ADC通道4,6轮询

2
rtl/peripherals/UART_RX.v
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@ -25,7 +25,7 @@ module UART_RX (
always@(posedge clk or negedge RSTn) begin always@(posedge clk or negedge RSTn) begin
if(~RSTn) counter_en <= 1'b0; if(~RSTn) counter_en <= 1'b0;
else if(re_start&&(~counter_en)) counter_en <= 1'b1; else if(re_start&&(~counter_en)) counter_en <= 1'b1;
else if(counter == 4'h9) counter_en <= 1'b0;ß else if(counter == 4'h9) counter_en <= 1'b0;
end end
always@(posedge clk or negedge RSTn) begin always@(posedge clk or negedge RSTn) begin