mirror of
https://github.com/JefferyLi0903/MMC.git
synced 2025-01-22 10:22:53 +08:00
402 lines
17 KiB
Plaintext
402 lines
17 KiB
Plaintext
eagle_s20
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12 22 615 14648 1000000000 9 0
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-5.407 0.191 CortexM0_SoC eagle_s20 BG256 Detail 8 1
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clock: DeriveClock
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12 1000000000 14648 5
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Setup check
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22 3
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Endpoint: u_logic/Vgjpw6_reg
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22 -5.407000 7575267 3
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Timing path: u_logic/M6kax6_reg.clk->u_logic/Vgjpw6_reg
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u_logic/M6kax6_reg.clk
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u_logic/Vgjpw6_reg
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24 -5.407000 19.884000 25.291000 19 19
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u_logic/M6kax6 u_logic/_al_u186|u_logic/_al_u188.b[0]
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u_logic/V6now6_lutinv u_logic/Ebpax6_reg|u_logic/Edpax6_reg.b[1]
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u_logic/_al_u238_o u_logic/Kmjpw6_reg.b[0]
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u_logic/S90iu6 u_logic/_al_u770|u_logic/_al_u242.d[0]
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u_logic/Mifpw6[18] u_logic/mult0_1_0_.a[0]
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u_logic/mult0_1_0_0 u_logic/u1/u0|u1/ucin.a[1]
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u_logic/n135[0] u_logic/u2/u0|u2/ucin.b[1]
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u_logic/u2/c1 u_logic/u2/u2|u2/u1.fci
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u_logic/n159[1] u_logic/_al_u3738|u_logic/Vpgbx6_reg.d[1]
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u_logic/_al_u3738_o u_logic/_al_u3739|u_logic/_al_u507.b[1]
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u_logic/_al_u3739_o u_logic/_al_u3740.c[1]
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u_logic/Y4miu6 u_logic/_al_u3741|u_logic/_al_u818.c[1]
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u_logic/_al_u3741_o u_logic/_al_u3746|u_logic/N3oax6_reg.b[1]
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u_logic/_al_u3746_o u_logic/_al_u3773|u_logic/_al_u3861.a[1]
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u_logic/_al_u3773_o u_logic/_al_u3866|u_logic/_al_u3841.a[1]
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u_logic/_al_u3866_o u_logic/_al_u3941.b[1]
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u_logic/_al_u3941_o u_logic/_al_u1731|u_logic/_al_u3942.a[0]
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u_logic/_al_u3942_o u_logic/_al_u2457|u_logic/_al_u4026.a[0]
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u_logic/_al_u4026_o u_logic/Vgjpw6_reg.a[1]
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Timing path: u_logic/M6kax6_reg.clk->u_logic/Vgjpw6_reg
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u_logic/M6kax6_reg.clk
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u_logic/Vgjpw6_reg
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87 -5.407000 19.884000 25.291000 19 19
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u_logic/M6kax6 u_logic/_al_u186|u_logic/_al_u188.b[0]
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u_logic/V6now6_lutinv u_logic/Ebpax6_reg|u_logic/Edpax6_reg.b[1]
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u_logic/_al_u238_o u_logic/Kmjpw6_reg.b[0]
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u_logic/S90iu6 u_logic/_al_u770|u_logic/_al_u242.d[0]
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u_logic/Mifpw6[18] u_logic/mult0_1_0_.a[0]
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u_logic/mult0_1_0_0 u_logic/u1/u0|u1/ucin.a[1]
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u_logic/n135[0] u_logic/u2/u0|u2/ucin.b[1]
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u_logic/u2/c1 u_logic/u2/u2|u2/u1.fci
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u_logic/n159[1] u_logic/_al_u3738|u_logic/Vpgbx6_reg.d[1]
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u_logic/_al_u3738_o u_logic/_al_u3739|u_logic/_al_u507.b[1]
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u_logic/_al_u3739_o u_logic/_al_u3740.c[1]
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u_logic/Y4miu6 u_logic/_al_u3741|u_logic/_al_u818.c[1]
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u_logic/_al_u3741_o u_logic/_al_u3746|u_logic/N3oax6_reg.b[1]
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u_logic/_al_u3746_o u_logic/_al_u3773|u_logic/_al_u3861.a[1]
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u_logic/_al_u3773_o u_logic/_al_u3866|u_logic/_al_u3841.a[1]
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u_logic/_al_u3866_o u_logic/_al_u3941.b[0]
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u_logic/_al_u3941_o u_logic/_al_u1731|u_logic/_al_u3942.a[0]
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u_logic/_al_u3942_o u_logic/_al_u2457|u_logic/_al_u4026.a[0]
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u_logic/_al_u4026_o u_logic/Vgjpw6_reg.a[1]
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Timing path: u_logic/M6kax6_reg.clk->u_logic/Vgjpw6_reg
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u_logic/M6kax6_reg.clk
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u_logic/Vgjpw6_reg
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150 -5.407000 19.884000 25.291000 19 19
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u_logic/M6kax6 u_logic/_al_u186|u_logic/_al_u188.b[0]
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u_logic/V6now6_lutinv u_logic/Ebpax6_reg|u_logic/Edpax6_reg.b[1]
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u_logic/_al_u238_o u_logic/Kmjpw6_reg.b[0]
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u_logic/S90iu6 u_logic/_al_u770|u_logic/_al_u242.d[0]
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u_logic/Mifpw6[18] u_logic/mult0_1_0_.a[0]
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u_logic/mult0_1_0_0 u_logic/u1/u0|u1/ucin.a[1]
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u_logic/n135[0] u_logic/u2/u0|u2/ucin.b[1]
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u_logic/u2/c1 u_logic/u2/u2|u2/u1.fci
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u_logic/n159[1] u_logic/_al_u3738|u_logic/Vpgbx6_reg.d[1]
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u_logic/_al_u3738_o u_logic/_al_u3739|u_logic/_al_u507.b[1]
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u_logic/_al_u3739_o u_logic/_al_u3740.c[1]
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u_logic/Y4miu6 u_logic/_al_u3741|u_logic/_al_u818.c[1]
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u_logic/_al_u3741_o u_logic/_al_u3746|u_logic/N3oax6_reg.b[1]
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u_logic/_al_u3746_o u_logic/_al_u3773|u_logic/_al_u3861.a[1]
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u_logic/_al_u3773_o u_logic/_al_u3866|u_logic/_al_u3841.a[1]
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u_logic/_al_u3866_o u_logic/_al_u3941.b[1]
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u_logic/_al_u3941_o u_logic/_al_u1731|u_logic/_al_u3942.a[0]
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u_logic/_al_u3942_o u_logic/_al_u2457|u_logic/_al_u4026.a[0]
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u_logic/_al_u4026_o u_logic/Vgjpw6_reg.a[0]
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Endpoint: u_logic/_al_u1795|u_logic/Ydopw6_reg
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213 -5.321000 3787611 3
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Timing path: u_logic/M6kax6_reg.clk->u_logic/_al_u1795|u_logic/Ydopw6_reg
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u_logic/M6kax6_reg.clk
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u_logic/_al_u1795|u_logic/Ydopw6_reg
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215 -5.321000 19.884000 25.205000 19 19
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u_logic/M6kax6 u_logic/_al_u186|u_logic/_al_u188.b[0]
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u_logic/V6now6_lutinv u_logic/Ebpax6_reg|u_logic/Edpax6_reg.b[1]
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u_logic/_al_u238_o u_logic/Kmjpw6_reg.b[0]
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u_logic/S90iu6 u_logic/_al_u770|u_logic/_al_u242.d[0]
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u_logic/Mifpw6[18] u_logic/mult0_1_0_.a[0]
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u_logic/mult0_1_0_0 u_logic/u1/u0|u1/ucin.a[1]
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u_logic/n135[0] u_logic/u2/u0|u2/ucin.b[1]
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u_logic/u2/c1 u_logic/u2/u2|u2/u1.fci
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u_logic/n159[1] u_logic/_al_u3738|u_logic/Vpgbx6_reg.d[1]
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u_logic/_al_u3738_o u_logic/_al_u3739|u_logic/_al_u507.b[1]
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u_logic/_al_u3739_o u_logic/_al_u3740.c[1]
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u_logic/Y4miu6 u_logic/_al_u3741|u_logic/_al_u818.c[1]
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u_logic/_al_u3741_o u_logic/_al_u3746|u_logic/N3oax6_reg.b[1]
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u_logic/_al_u3746_o u_logic/_al_u3773|u_logic/_al_u3861.a[1]
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u_logic/_al_u3773_o u_logic/_al_u3866|u_logic/_al_u3841.a[1]
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u_logic/_al_u3866_o u_logic/_al_u3941.b[1]
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u_logic/_al_u3941_o u_logic/_al_u1731|u_logic/_al_u3942.a[0]
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u_logic/_al_u3942_o u_logic/_al_u2336|u_logic/_al_u3977.a[0]
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u_logic/_al_u3977_o u_logic/_al_u1795|u_logic/Ydopw6_reg.a[0]
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Timing path: u_logic/M6kax6_reg.clk->u_logic/_al_u1795|u_logic/Ydopw6_reg
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u_logic/M6kax6_reg.clk
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u_logic/_al_u1795|u_logic/Ydopw6_reg
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278 -5.321000 19.884000 25.205000 19 19
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u_logic/M6kax6 u_logic/_al_u186|u_logic/_al_u188.b[0]
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u_logic/V6now6_lutinv u_logic/Ebpax6_reg|u_logic/Edpax6_reg.b[1]
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u_logic/_al_u238_o u_logic/Kmjpw6_reg.b[0]
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u_logic/S90iu6 u_logic/_al_u770|u_logic/_al_u242.d[0]
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u_logic/Mifpw6[18] u_logic/mult0_1_0_.a[0]
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u_logic/mult0_1_0_0 u_logic/u1/u0|u1/ucin.a[1]
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u_logic/n135[0] u_logic/u2/u0|u2/ucin.b[1]
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u_logic/u2/c1 u_logic/u2/u2|u2/u1.fci
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u_logic/n159[1] u_logic/_al_u3738|u_logic/Vpgbx6_reg.d[1]
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u_logic/_al_u3738_o u_logic/_al_u3739|u_logic/_al_u507.b[1]
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u_logic/_al_u3739_o u_logic/_al_u3740.c[0]
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u_logic/Y4miu6 u_logic/_al_u3741|u_logic/_al_u818.c[1]
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u_logic/_al_u3741_o u_logic/_al_u3746|u_logic/N3oax6_reg.b[1]
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u_logic/_al_u3746_o u_logic/_al_u3773|u_logic/_al_u3861.a[1]
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u_logic/_al_u3773_o u_logic/_al_u3866|u_logic/_al_u3841.a[1]
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u_logic/_al_u3866_o u_logic/_al_u3941.b[1]
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u_logic/_al_u3941_o u_logic/_al_u1731|u_logic/_al_u3942.a[0]
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u_logic/_al_u3942_o u_logic/_al_u2336|u_logic/_al_u3977.a[0]
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u_logic/_al_u3977_o u_logic/_al_u1795|u_logic/Ydopw6_reg.a[0]
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Timing path: u_logic/M6kax6_reg.clk->u_logic/_al_u1795|u_logic/Ydopw6_reg
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u_logic/M6kax6_reg.clk
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u_logic/_al_u1795|u_logic/Ydopw6_reg
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341 -5.321000 19.884000 25.205000 19 19
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u_logic/M6kax6 u_logic/_al_u186|u_logic/_al_u188.b[0]
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u_logic/V6now6_lutinv u_logic/Ebpax6_reg|u_logic/Edpax6_reg.b[1]
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u_logic/_al_u238_o u_logic/Kmjpw6_reg.b[0]
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u_logic/S90iu6 u_logic/_al_u770|u_logic/_al_u242.d[0]
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u_logic/Mifpw6[18] u_logic/mult0_1_0_.a[0]
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u_logic/mult0_1_0_0 u_logic/u1/u0|u1/ucin.a[1]
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u_logic/n135[0] u_logic/u2/u0|u2/ucin.b[1]
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u_logic/u2/c1 u_logic/u2/u2|u2/u1.fci
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u_logic/n159[1] u_logic/_al_u3738|u_logic/Vpgbx6_reg.d[1]
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u_logic/_al_u3738_o u_logic/_al_u3739|u_logic/_al_u507.b[1]
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u_logic/_al_u3739_o u_logic/_al_u3740.c[1]
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u_logic/Y4miu6 u_logic/_al_u3741|u_logic/_al_u818.c[1]
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u_logic/_al_u3741_o u_logic/_al_u3746|u_logic/N3oax6_reg.b[1]
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u_logic/_al_u3746_o u_logic/_al_u3773|u_logic/_al_u3861.a[1]
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u_logic/_al_u3773_o u_logic/_al_u3866|u_logic/_al_u3841.a[1]
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u_logic/_al_u3866_o u_logic/_al_u3941.b[0]
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u_logic/_al_u3941_o u_logic/_al_u1731|u_logic/_al_u3942.a[0]
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u_logic/_al_u3942_o u_logic/_al_u2336|u_logic/_al_u3977.a[0]
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u_logic/_al_u3977_o u_logic/_al_u1795|u_logic/Ydopw6_reg.a[0]
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Endpoint: u_logic/_al_u2966|u_logic/Isjpw6_reg
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404 -3.436000 1555207 3
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Timing path: u_logic/_al_u2285|u_logic/P5vpw6_reg.clk->u_logic/_al_u2966|u_logic/Isjpw6_reg
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u_logic/_al_u2285|u_logic/P5vpw6_reg.clk
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u_logic/_al_u2966|u_logic/Isjpw6_reg
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406 -3.436000 19.884000 23.320000 20 22
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u_logic/P5vpw6 u_logic/_al_u1099|u_logic/_al_u2552.b[0]
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u_logic/_al_u2552_o u_logic/_al_u2553|u_logic/_al_u4467.a[1]
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u_logic/_al_u2553_o u_logic/_al_u2554|u_logic/_al_u1450.a[1]
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u_logic/_al_u2554_o u_logic/_al_u2555|u_logic/_al_u195.a[1]
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u_logic/_al_u2555_o u_logic/_al_u2559|u_logic/_al_u2708.a[1]
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u_logic/_al_u2559_o u_logic/_al_u2567|u_logic/_al_u692.a[1]
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u_logic/_al_u2567_o u_logic/_al_u2571|u_logic/L6lax6_reg.a[1]
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u_logic/_al_u2571_o u_logic/_al_u2644|u_logic/_al_u2961.d[1]
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u_logic/Vtzhu6 u_logic/_al_u2646|u_logic/Sx3qw6_reg.d[1]
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u_logic/R0ghu6 u_logic/add2/ucin_al_u4831.b[0]
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u_logic/add2/c3 u_logic/add2/u3_al_u4832.fci
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u_logic/add2/c7 u_logic/add2/u7_al_u4833.fci
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u_logic/N5fpw6[9] u_logic/_al_u2524.c[0]
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u_logic/_al_u2524_o u_logic/_al_u2525.c[1]
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u_logic/_al_u2525_o u_logic/_al_u3418|u_logic/_al_u3458.a[1]
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u_logic/I9ihu6 u_logic/_al_u3362|u_logic/Nmabx6_reg.b[0]
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u_logic/_al_u3419_o u_logic/_al_u3423.a[1]
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u_logic/_al_u3423_o u_logic/_al_u3368|u_logic/Fldbx6_reg.c[0]
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u_logic/_al_u3443_o u_logic/_al_u3465|u_logic/J59ax6_reg.a[1]
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u_logic/_al_u3465_o u_logic/_al_u2966|u_logic/Isjpw6_reg.a[0]
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u_logic/Dt4iu6 u_logic/_al_u3993.a[1]
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u_logic/Kt4iu6 u_logic/_al_u2966|u_logic/Isjpw6_reg.ce
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Timing path: u_logic/_al_u2285|u_logic/P5vpw6_reg.clk->u_logic/_al_u2966|u_logic/Isjpw6_reg
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u_logic/_al_u2285|u_logic/P5vpw6_reg.clk
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u_logic/_al_u2966|u_logic/Isjpw6_reg
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475 -3.436000 19.884000 23.320000 20 22
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u_logic/P5vpw6 u_logic/_al_u1099|u_logic/_al_u2552.b[0]
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u_logic/_al_u2552_o u_logic/_al_u2553|u_logic/_al_u4467.a[1]
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u_logic/_al_u2553_o u_logic/_al_u2554|u_logic/_al_u1450.a[1]
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u_logic/_al_u2554_o u_logic/_al_u2555|u_logic/_al_u195.a[1]
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u_logic/_al_u2555_o u_logic/_al_u2559|u_logic/_al_u2708.a[1]
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u_logic/_al_u2559_o u_logic/_al_u2567|u_logic/_al_u692.a[1]
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u_logic/_al_u2567_o u_logic/_al_u2571|u_logic/L6lax6_reg.a[1]
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u_logic/_al_u2571_o u_logic/_al_u2644|u_logic/_al_u2961.d[1]
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u_logic/Vtzhu6 u_logic/_al_u2646|u_logic/Sx3qw6_reg.d[1]
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u_logic/R0ghu6 u_logic/add2/ucin_al_u4831.b[0]
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u_logic/add2/c3 u_logic/add2/u3_al_u4832.fci
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u_logic/add2/c7 u_logic/add2/u7_al_u4833.fci
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u_logic/N5fpw6[9] u_logic/_al_u2524.c[0]
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u_logic/_al_u2524_o u_logic/_al_u2525.c[1]
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u_logic/_al_u2525_o u_logic/_al_u3418|u_logic/_al_u3458.a[1]
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u_logic/I9ihu6 u_logic/_al_u3362|u_logic/Nmabx6_reg.b[0]
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u_logic/_al_u3419_o u_logic/_al_u3423.a[0]
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u_logic/_al_u3423_o u_logic/_al_u3368|u_logic/Fldbx6_reg.c[0]
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u_logic/_al_u3443_o u_logic/_al_u3465|u_logic/J59ax6_reg.a[1]
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u_logic/_al_u3465_o u_logic/_al_u2966|u_logic/Isjpw6_reg.a[0]
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u_logic/Dt4iu6 u_logic/_al_u3993.a[1]
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u_logic/Kt4iu6 u_logic/_al_u2966|u_logic/Isjpw6_reg.ce
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Timing path: u_logic/_al_u2285|u_logic/P5vpw6_reg.clk->u_logic/_al_u2966|u_logic/Isjpw6_reg
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u_logic/_al_u2285|u_logic/P5vpw6_reg.clk
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u_logic/_al_u2966|u_logic/Isjpw6_reg
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544 -3.436000 19.884000 23.320000 20 22
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u_logic/P5vpw6 u_logic/_al_u1099|u_logic/_al_u2552.b[0]
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u_logic/_al_u2552_o u_logic/_al_u2553|u_logic/_al_u4467.a[1]
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u_logic/_al_u2553_o u_logic/_al_u2554|u_logic/_al_u1450.a[1]
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u_logic/_al_u2554_o u_logic/_al_u2555|u_logic/_al_u195.a[1]
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u_logic/_al_u2555_o u_logic/_al_u2559|u_logic/_al_u2708.a[1]
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u_logic/_al_u2559_o u_logic/_al_u2567|u_logic/_al_u692.a[1]
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u_logic/_al_u2567_o u_logic/_al_u2571|u_logic/L6lax6_reg.a[1]
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u_logic/_al_u2571_o u_logic/_al_u2644|u_logic/_al_u2961.d[1]
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u_logic/Vtzhu6 u_logic/_al_u2646|u_logic/Sx3qw6_reg.d[1]
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u_logic/R0ghu6 u_logic/add2/ucin_al_u4831.b[0]
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u_logic/add2/c3 u_logic/add2/u3_al_u4832.fci
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u_logic/add2/c7 u_logic/add2/u7_al_u4833.fci
|
|
u_logic/N5fpw6[9] u_logic/_al_u2524.c[0]
|
|
u_logic/_al_u2524_o u_logic/_al_u2525.c[1]
|
|
u_logic/_al_u2525_o u_logic/_al_u3418|u_logic/_al_u3458.a[1]
|
|
u_logic/I9ihu6 u_logic/_al_u3362|u_logic/Nmabx6_reg.b[0]
|
|
u_logic/_al_u3419_o u_logic/_al_u3423.a[1]
|
|
u_logic/_al_u3423_o u_logic/_al_u3368|u_logic/Fldbx6_reg.c[0]
|
|
u_logic/_al_u3443_o u_logic/_al_u3465|u_logic/J59ax6_reg.a[1]
|
|
u_logic/_al_u3465_o u_logic/_al_u2966|u_logic/Isjpw6_reg.a[0]
|
|
u_logic/Dt4iu6 u_logic/_al_u3993.a[0]
|
|
u_logic/Kt4iu6 u_logic/_al_u2966|u_logic/Isjpw6_reg.ce
|
|
|
|
|
|
|
|
Hold check
|
|
613 3
|
|
Endpoint: ethernet_i0/mac_test0/al_ram_Buff_A_r7_c7_l
|
|
615 0.191000 2 2
|
|
Timing path: ethernet_i0/mac_test0/reg2_b0|ethernet_i0/mac_test0/reg2_b1.clk->ethernet_i0/mac_test0/al_ram_Buff_A_r7_c7_l
|
|
ethernet_i0/mac_test0/reg2_b0|ethernet_i0/mac_test0/reg2_b1.clk
|
|
ethernet_i0/mac_test0/al_ram_Buff_A_r7_c7_l
|
|
617 0.191000 0.134000 0.325000 1 1
|
|
ethernet_i0/mac_test0/count_A[1] ethernet_i0/mac_test0/al_ram_Buff_A_r7_c7_l.b[0]
|
|
|
|
Timing path: FM_HW/FM_Demodulation/reg12_b29|FM_HW/FM_Demodulation/reg12_b30.clk->ethernet_i0/mac_test0/al_ram_Buff_A_r7_c7_l
|
|
FM_HW/FM_Demodulation/reg12_b29|FM_HW/FM_Demodulation/reg12_b30.clk
|
|
ethernet_i0/mac_test0/al_ram_Buff_A_r7_c7_l
|
|
644 0.590000 0.134000 0.724000 1 1
|
|
fm_data_ethernet[29] ethernet_i0/mac_test0/al_ram_Buff_A_r7_c7_l.b[1]
|
|
|
|
|
|
Endpoint: UART_TX/FIFO_UART/al_ram_mem_c1_l
|
|
671 0.295000 94 3
|
|
Timing path: UART_TX/FIFO_UART/reg1_b2|UART_TX/FIFO_UART/reg1_b3.clk->UART_TX/FIFO_UART/al_ram_mem_c1_l
|
|
UART_TX/FIFO_UART/reg1_b2|UART_TX/FIFO_UART/reg1_b3.clk
|
|
UART_TX/FIFO_UART/al_ram_mem_c1_l
|
|
673 0.295000 0.134000 0.429000 1 1
|
|
UART_TX/FIFO_UART/wp[3] UART_TX/FIFO_UART/al_ram_mem_c1_l.d[0]
|
|
|
|
Timing path: _al_u537|UART_Interface/wr_en_reg_reg.clk->UART_TX/FIFO_UART/al_ram_mem_c1_l
|
|
_al_u537|UART_Interface/wr_en_reg_reg.clk
|
|
UART_TX/FIFO_UART/al_ram_mem_c1_l
|
|
700 1.520000 0.134000 1.654000 2 2
|
|
UART_Interface/wr_en_reg _al_u188|_al_u352.d[1]
|
|
UART_TX_data[7] UART_TX/FIFO_UART/al_ram_mem_c1_l.d[1]
|
|
|
|
Timing path: u_logic/_al_u4432|u_logic/Wvgax6_reg.clk->UART_TX/FIFO_UART/al_ram_mem_c1_l
|
|
u_logic/_al_u4432|u_logic/Wvgax6_reg.clk
|
|
UART_TX/FIFO_UART/al_ram_mem_c1_l
|
|
729 3.179000 0.134000 3.313000 3 3
|
|
u_logic/Wvgax6 u_logic/_al_u2614|u_logic/Yqzax6_reg.d[0]
|
|
HWDATA[7] _al_u188|_al_u352.c[1]
|
|
UART_TX_data[7] UART_TX/FIFO_UART/al_ram_mem_c1_l.d[1]
|
|
|
|
|
|
Endpoint: ethernet_i0/mac_test0/al_ram_Buff_B_r7_c6_l
|
|
760 0.304000 2 2
|
|
Timing path: FM_HW/FM_Demodulation/reg12_b25|FM_HW/FM_Demodulation/reg12_b26.clk->ethernet_i0/mac_test0/al_ram_Buff_B_r7_c6_l
|
|
FM_HW/FM_Demodulation/reg12_b25|FM_HW/FM_Demodulation/reg12_b26.clk
|
|
ethernet_i0/mac_test0/al_ram_Buff_B_r7_c6_l
|
|
762 0.304000 0.134000 0.438000 1 1
|
|
fm_data_ethernet[25] ethernet_i0/mac_test0/al_ram_Buff_B_r7_c6_l.b[1]
|
|
|
|
Timing path: ethernet_i0/mac_test0/reg3_b0|ethernet_i0/mac_test0/reg3_b1.clk->ethernet_i0/mac_test0/al_ram_Buff_B_r7_c6_l
|
|
ethernet_i0/mac_test0/reg3_b0|ethernet_i0/mac_test0/reg3_b1.clk
|
|
ethernet_i0/mac_test0/al_ram_Buff_B_r7_c6_l
|
|
789 0.759000 0.134000 0.893000 1 1
|
|
ethernet_i0/mac_test0/count_B[1] ethernet_i0/mac_test0/al_ram_Buff_B_r7_c6_l.b[0]
|
|
|
|
|
|
|
|
Recovery check
|
|
816 3
|
|
Endpoint: u_logic/Nlhax6_reg
|
|
818 17.230000 1 1
|
|
Timing path: u_logic/_al_u4017|cpuresetn_reg.clk->u_logic/Nlhax6_reg
|
|
u_logic/_al_u4017|cpuresetn_reg.clk
|
|
u_logic/Nlhax6_reg
|
|
820 17.230000 19.700000 2.470000 0 1
|
|
cpuresetn u_logic/Nlhax6_reg.sr
|
|
|
|
|
|
Endpoint: RAMDATA_Interface/reg0_b6|RAMDATA_Interface/reg0_b5
|
|
847 17.236000 1 1
|
|
Timing path: u_logic/_al_u4017|cpuresetn_reg.clk->RAMDATA_Interface/reg0_b6|RAMDATA_Interface/reg0_b5
|
|
u_logic/_al_u4017|cpuresetn_reg.clk
|
|
RAMDATA_Interface/reg0_b6|RAMDATA_Interface/reg0_b5
|
|
849 17.236000 19.700000 2.464000 0 1
|
|
cpuresetn RAMDATA_Interface/reg0_b6|RAMDATA_Interface/reg0_b5.sr
|
|
|
|
|
|
Endpoint: u_logic/_al_u2754|u_logic/Vzupw6_reg
|
|
876 17.334000 1 1
|
|
Timing path: u_logic/_al_u4017|cpuresetn_reg.clk->u_logic/_al_u2754|u_logic/Vzupw6_reg
|
|
u_logic/_al_u4017|cpuresetn_reg.clk
|
|
u_logic/_al_u2754|u_logic/Vzupw6_reg
|
|
878 17.334000 19.700000 2.366000 0 1
|
|
cpuresetn u_logic/_al_u2754|u_logic/Vzupw6_reg.sr
|
|
|
|
|
|
|
|
Removal check
|
|
905 3
|
|
Endpoint: u_logic/_al_u661|u_logic/Kwlpw6_reg
|
|
907 0.414000 1 1
|
|
Timing path: u_logic/_al_u63|u_logic/Kxhpw6_reg.clk->u_logic/_al_u661|u_logic/Kwlpw6_reg
|
|
u_logic/_al_u63|u_logic/Kxhpw6_reg.clk
|
|
u_logic/_al_u661|u_logic/Kwlpw6_reg
|
|
909 0.414000 0.300000 0.714000 0 1
|
|
u_logic/Kxhpw6 u_logic/_al_u661|u_logic/Kwlpw6_reg.sr
|
|
|
|
|
|
Endpoint: u_logic/Qwfax6_reg|u_logic/T0ipw6_reg
|
|
936 0.414000 1 1
|
|
Timing path: u_logic/_al_u63|u_logic/Kxhpw6_reg.clk->u_logic/Qwfax6_reg|u_logic/T0ipw6_reg
|
|
u_logic/_al_u63|u_logic/Kxhpw6_reg.clk
|
|
u_logic/Qwfax6_reg|u_logic/T0ipw6_reg
|
|
938 0.414000 0.300000 0.714000 0 1
|
|
u_logic/Kxhpw6 u_logic/Qwfax6_reg|u_logic/T0ipw6_reg.sr
|
|
|
|
|
|
Endpoint: ethernet_i0/mac_test0/mac_top0/mac_rx0/c0/reg0_b25
|
|
965 0.522000 1 1
|
|
Timing path: ethernet_i0/mac_test0/mac_top0/mac_rx0/_al_u739|ethernet_i0/mac_test0/mac_top0/mac_rx0/mac0/crcre_reg.clk->ethernet_i0/mac_test0/mac_top0/mac_rx0/c0/reg0_b25
|
|
ethernet_i0/mac_test0/mac_top0/mac_rx0/_al_u739|ethernet_i0/mac_test0/mac_top0/mac_rx0/mac0/crcre_reg.clk
|
|
ethernet_i0/mac_test0/mac_top0/mac_rx0/c0/reg0_b25
|
|
967 0.522000 0.300000 0.822000 0 1
|
|
ethernet_i0/mac_test0/mac_top0/mac_rx0/crcre ethernet_i0/mac_test0/mac_top0/mac_rx0/c0/reg0_b25.sr
|
|
|
|
|
|
|
|
Period check
|
|
994 4
|
|
Endpoint: ethernet_i0/mac_test0/mac_top0/mac_tx0/udp0/tx_data_fifo/fifo_inst_3_.clkw
|
|
998 16.700000 1 0
|
|
|
|
Endpoint: ethernet_i0/mac_test0/mac_top0/mac_tx0/udp0/tx_data_fifo/fifo_inst_2_.clkw
|
|
999 16.700000 1 0
|
|
|
|
Endpoint: ethernet_i0/mac_test0/mac_top0/mac_tx0/udp0/tx_data_fifo/fifo_inst_1_.clkw
|
|
1000 16.700000 1 0
|
|
|
|
Endpoint: ethernet_i0/mac_test0/mac_top0/mac_tx0/udp0/tx_data_fifo/fifo_inst_0_.clkw
|
|
1001 16.700000 1 0
|
|
|
|
|
|
|
|
|
|
Timing group statistics:
|
|
Clock constraints:
|
|
Clock Name Min Period Max Freq Skew Fanout TNS
|
|
DeriveClock (50.0MHz) 25.407ns 39MHz 0.000ns 3152 -144.170ns
|
|
Minimum input arrival time before clock: no constraint path
|
|
Maximum output required time after clock: no constraint path
|
|
Maximum combinational path delay: no constraint path
|
|
Warning: No clock constraint on 16 clock net(s):
|
|
CW_CLK_MSI
|
|
FM_HW/ADC_CLK
|
|
FM_HW/CW_CLK
|
|
FM_HW/EOC
|
|
FM_HW/FM_Demodulation/EOC_Count_Demodulate
|
|
FM_HW/FM_Demodulation/I2S_BCLK_pad
|
|
FM_HW/FM_RSSI_SCAN/EOC_Count_Demodulate
|
|
FM_HW/clk_PWM_160
|
|
FM_HW/clk_PWM_256
|
|
FM_HW/clk_fm_demo_sampling
|
|
MSI_REFCLK_pad
|
|
clk_fm_ethernet
|
|
clk_pad
|
|
ethernet_i0/gmii_rx_clk
|
|
scan_unit/scan_clk
|
|
u_logic/SWCLKTCK_pad
|
|
|