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43 lines
1.3 KiB
Verilog
43 lines
1.3 KiB
Verilog
module CW_TOP_WRAPPER(jtdi, jtck, jrstn, jscan, jshift, jupdate, jtdo, non_bus_din, bus_din, trig_clk, wt_ce, wt_en, wt_addr);
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localparam DEFAULT_CTRL_REG_LEN = 156;
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localparam DEFAULT_STAT_REG_LEN = 18;
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localparam DEFAULT_STOP_LEN = 5461;
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localparam DEFAULT_NON_BUS_NODE_NUM = 0;
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localparam DEFAULT_BUS_NODE_NUM = 17;
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localparam DEFAULT_BUS_NUM = 2;
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localparam DEFAULT_BUS1_WIDTH = 14;
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localparam DEFAULT_BUS2_WIDTH = 3;
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input jtdi;
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input jtck;
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input jrstn;
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input [1:0] jscan;
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input jshift;
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input jupdate;
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output [1:0] jtdo;
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input trig_clk;
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input [DEFAULT_NON_BUS_NODE_NUM-1:0] non_bus_din;
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input [DEFAULT_BUS_NODE_NUM-1:0] bus_din;
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output wt_ce;
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output wt_en;
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output [15:0] wt_addr;
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cwc_top #(.BUS1_WIDTH(DEFAULT_BUS1_WIDTH), .BUS2_WIDTH(DEFAULT_BUS2_WIDTH), .CTRL_REG_LEN(DEFAULT_CTRL_REG_LEN), .STAT_REG_LEN(DEFAULT_STAT_REG_LEN), .STOP_LEN(DEFAULT_STOP_LEN), .NON_BUS_NODE_NUM(DEFAULT_NON_BUS_NODE_NUM), .BUS_NODE_NUM(DEFAULT_BUS_NODE_NUM), .BUS_NUM(DEFAULT_BUS_NUM))
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wrapper_cwc_top(
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.jtdi(jtdi),
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.jtck(jtck),
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.jrstn(jrstn),
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.jscan(jscan),
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.jshift(jshift),
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.jupdate(jupdate),
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.jtdo(jtdo),
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.non_bus_din(non_bus_din),
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.bus_din(bus_din),
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.trig_clk(trig_clk),
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.wt_ce(wt_ce),
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.wt_en(wt_en),
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.wt_addr(wt_addr)
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);
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endmodule
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