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46 lines
1.1 KiB
Verilog
46 lines
1.1 KiB
Verilog
/************************************************************\
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** Copyright (c) 2011-2021 Anlogic, Inc.
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** All Right Reserved.
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\************************************************************/
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/************************************************************\
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** Log : This file is generated by Anlogic IP Generator.
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** File : G:/Compete/Ass/ArmCortex-M0/CortexM0_SoC_Task/Task3/td/al_ip/FM_ADC.v
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** Date : 2022 04 29
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** TD version : 5.0.30786
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\************************************************************/
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module ADC_Sample_debug(
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output wire eoc,
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output reg [11:0] dout,
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input RSTn,
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input clk,
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input [2:0] channel
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);
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clkADC_debug_pwm simEOC
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(
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.bps_en(1),
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.clk(clk),
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.RSTn(RSTn),
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.clk_ADC_debug(eoc)
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);
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reg [7:0] I_data;
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reg [7:0] Q_data;
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reg [7:0] rand;
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always@(posedge eoc or negedge RSTn ) begin
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I_data <= $random %255;
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Q_data <= $random %255;
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end
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always@(posedge eoc or negedge RSTn ) begin
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//dout <= {channel[2:0], channel[2:0],channel[2:0],channel[2:0]};
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dout[11:4] <= (channel==3'b110)?I_data:Q_data;
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dout[3:0] <=4'b0;
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end
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endmodule |