mirror of
https://github.com/JefferyLi0903/MMC.git
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1068 lines
101 KiB
Plaintext
1068 lines
101 KiB
Plaintext
=========================================================================================================
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Auto created by the td v5.0.43066
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@Copy Right: Shanghai Anlogic Infotech, 2011 - 2021.
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Tue May 23 20:43:11 2023
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=========================================================================================================
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Top Model: CortexM0_SoC
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Device: eagle_s20
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Timing Constraint File:
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STA Level: Detail
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=========================================================================================================
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Timing constraint: clock: DeriveClock
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Clock = DeriveClock, period 20ns, rising at 0ns, falling at 10ns
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34090 endpoints analyzed totally, and more than 1000000000 paths analyzed
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9 errors detected : 9 setup errors (TNS = -697.928), 0 hold errors (TNS = 0.000)
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Minimum period is 29.076ns
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---------------------------------------------------------------------------------------------------------
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Paths for end point u_logic/Vgjpw6_reg (13863737 paths)
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---------------------------------------------------------------------------------------------------------
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Slack (setup check): -9.076 ns
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Start Point: u_logic/M6kax6_reg.clk (rising edge triggered by clock DeriveClock)
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End Point: u_logic/Vgjpw6_reg.a[1] (rising edge triggered by clock DeriveClock)
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Clock group: DeriveClock
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Data Path Delay: 28.960ns (logic 11.140ns, net 17.820ns, 38% logic)
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Logic Levels: 19
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Point Type Incr Path Info
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---------------------------------------------------------------------------------------------------------
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u_logic/M6kax6_reg.clk clock 0.000 0.000
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launch clock edge 0.000 0.000
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u_logic/M6kax6_reg.q[0] clk2q 0.146 r 0.146
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u_logic/_al_u182|u_logic/_al_u192.b[1] (u_logic/M6kax6) net (fanout = 14) 1.014 r 1.160 ../rtl/topmodule/cortexm0ds_logic.v(1651)
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u_logic/_al_u182|u_logic/_al_u192.f[1] cell 0.333 r 1.493
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u_logic/_al_u239|u_logic/Ljwax6_reg.a[1] (u_logic/Wanow6_lutinv) net (fanout = 32) 4.192 r 5.685 ../rtl/topmodule/cortexm0ds_logic.v(1158)
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u_logic/_al_u239|u_logic/Ljwax6_reg.f[1] cell 0.424 r 6.109
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u_logic/_al_u219|u_logic/Llwax6_reg.c[0] (u_logic/_al_u239_o) net (fanout = 1) 0.456 r 6.565
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u_logic/_al_u219|u_logic/Llwax6_reg.f[0] cell 0.251 r 6.816
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u_logic/_al_u242|u_logic/_al_u272.d[1] (u_logic/S90iu6) net (fanout = 7) 1.520 r 8.336 ../rtl/topmodule/cortexm0ds_logic.v(307)
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u_logic/_al_u242|u_logic/_al_u272.f[1] cell 0.262 r 8.598
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u_logic/mult0_1_0_.a[0] (u_logic/Mifpw6[18]) net (fanout = 1) 0.672 r 9.270 ../rtl/topmodule/cortexm0ds_logic.v(1531)
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u_logic/mult0_1_0_.p[0] cell (MULT18) 3.563 r 12.833
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u_logic/u1/u0|u1/ucin.a[1] (u_logic/mult0_1_0_0) net (fanout = 1) 0.671 r 13.504
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u_logic/u1/u0|u1/ucin.f[1] cell 0.507 r 14.011
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u_logic/u2/u0|u2/ucin.b[1] (u_logic/n135[0]) net (fanout = 1) 0.738 r 14.749
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u_logic/u2/u0|u2/ucin.fco cell (ADDER) 0.539 r 15.288
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u_logic/u2/u2|u2/u1.fci (u_logic/u2/c1) net (fanout = 1) 0.000 f 15.288
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u_logic/u2/u2|u2/u1.f[0] cell 0.144 r 15.432
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u_logic/_al_u3820|u_logic/_al_u3738.d[0] (u_logic/n159[1]) net (fanout = 1) 0.992 r 16.424
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u_logic/_al_u3820|u_logic/_al_u3738.f[0] cell 0.262 r 16.686
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u_logic/_al_u3739|u_logic/_al_u3824.b[1] (u_logic/_al_u3738_o) net (fanout = 1) 0.941 r 17.627
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u_logic/_al_u3739|u_logic/_al_u3824.f[1] cell 0.333 r 17.960
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u_logic/_al_u3740.c[1] (u_logic/_al_u3739_o) net (fanout = 2) 0.525 r 18.485
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u_logic/_al_u3740.fx[0] cell 0.448 r 18.933
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u_logic/_al_u3741|u_logic/W7max6_reg.c[1] (u_logic/Y4miu6) net (fanout = 2) 1.510 r 20.443 ../rtl/topmodule/cortexm0ds_logic.v(599)
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u_logic/_al_u3741|u_logic/W7max6_reg.f[1] cell 0.348 r 20.791
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u_logic/_al_u3746|u_logic/Wdmax6_reg.b[1] (u_logic/_al_u3741_o) net (fanout = 1) 0.456 r 21.247
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u_logic/_al_u3746|u_logic/Wdmax6_reg.f[1] cell 0.333 r 21.580
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u_logic/_al_u3773|u_logic/_al_u3816.a[1] (u_logic/_al_u3746_o) net (fanout = 1) 0.526 r 22.106
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u_logic/_al_u3773|u_logic/_al_u3816.f[1] cell 0.424 r 22.530
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u_logic/_al_u3866|u_logic/_al_u3823.a[1] (u_logic/_al_u3773_o) net (fanout = 1) 0.618 r 23.148
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u_logic/_al_u3866|u_logic/_al_u3823.f[1] cell 0.424 r 23.572
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u_logic/_al_u3681|u_logic/_al_u3941.b[0] (u_logic/_al_u3866_o) net (fanout = 1) 0.676 r 24.248
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u_logic/_al_u3681|u_logic/_al_u3941.f[0] cell 0.431 r 24.679
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u_logic/_al_u3942.a[1] (u_logic/_al_u3941_o) net (fanout = 3) 0.468 r 25.147
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u_logic/_al_u3942.fx[0] cell 0.618 r 25.765
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u_logic/_al_u4026.a[1] (u_logic/_al_u3942_o) net (fanout = 3) 1.220 r 26.985
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u_logic/_al_u4026.fx[0] cell 0.618 r 27.603
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u_logic/Vgjpw6_reg.a[1] (u_logic/_al_u4026_o) net (fanout = 2) 0.625 r 28.228 ../rtl/topmodule/cortexm0ds_logic.v(1587)
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u_logic/Vgjpw6_reg path2reg0 0.732 28.960
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Arrival time 28.960 (19 lvl)
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u_logic/Vgjpw6_reg.clk 0.000 0.000
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capture clock edge 20.000 20.000
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cell setup -0.116 19.884
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clock uncertainty -0.000 19.884
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clock recovergence pessimism 0.000 19.884
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Required time 19.884
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---------------------------------------------------------------------------------------------------------
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Slack -9.076ns
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---------------------------------------------------------------------------------------------------------
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Slack (setup check): -9.076 ns
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Start Point: u_logic/M6kax6_reg.clk (rising edge triggered by clock DeriveClock)
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End Point: u_logic/Vgjpw6_reg.a[1] (rising edge triggered by clock DeriveClock)
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Clock group: DeriveClock
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Data Path Delay: 28.960ns (logic 11.140ns, net 17.820ns, 38% logic)
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Logic Levels: 19
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Point Type Incr Path Info
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---------------------------------------------------------------------------------------------------------
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u_logic/M6kax6_reg.clk clock 0.000 0.000
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launch clock edge 0.000 0.000
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u_logic/M6kax6_reg.q[0] clk2q 0.146 r 0.146
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u_logic/_al_u182|u_logic/_al_u192.b[1] (u_logic/M6kax6) net (fanout = 14) 1.014 r 1.160 ../rtl/topmodule/cortexm0ds_logic.v(1651)
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u_logic/_al_u182|u_logic/_al_u192.f[1] cell 0.333 r 1.493
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u_logic/_al_u239|u_logic/Ljwax6_reg.a[1] (u_logic/Wanow6_lutinv) net (fanout = 32) 4.192 r 5.685 ../rtl/topmodule/cortexm0ds_logic.v(1158)
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u_logic/_al_u239|u_logic/Ljwax6_reg.f[1] cell 0.424 r 6.109
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u_logic/_al_u219|u_logic/Llwax6_reg.c[0] (u_logic/_al_u239_o) net (fanout = 1) 0.456 r 6.565
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u_logic/_al_u219|u_logic/Llwax6_reg.f[0] cell 0.251 r 6.816
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u_logic/_al_u242|u_logic/_al_u272.d[1] (u_logic/S90iu6) net (fanout = 7) 1.520 r 8.336 ../rtl/topmodule/cortexm0ds_logic.v(307)
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u_logic/_al_u242|u_logic/_al_u272.f[1] cell 0.262 r 8.598
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u_logic/mult0_1_0_.a[0] (u_logic/Mifpw6[18]) net (fanout = 1) 0.672 r 9.270 ../rtl/topmodule/cortexm0ds_logic.v(1531)
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u_logic/mult0_1_0_.p[0] cell (MULT18) 3.563 r 12.833
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u_logic/u1/u0|u1/ucin.a[1] (u_logic/mult0_1_0_0) net (fanout = 1) 0.671 r 13.504
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u_logic/u1/u0|u1/ucin.f[1] cell 0.507 r 14.011
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u_logic/u2/u0|u2/ucin.b[1] (u_logic/n135[0]) net (fanout = 1) 0.738 r 14.749
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u_logic/u2/u0|u2/ucin.fco cell (ADDER) 0.539 r 15.288
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u_logic/u2/u2|u2/u1.fci (u_logic/u2/c1) net (fanout = 1) 0.000 f 15.288
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u_logic/u2/u2|u2/u1.f[0] cell 0.144 r 15.432
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u_logic/_al_u3820|u_logic/_al_u3738.d[0] (u_logic/n159[1]) net (fanout = 1) 0.992 r 16.424
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u_logic/_al_u3820|u_logic/_al_u3738.f[0] cell 0.262 r 16.686
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u_logic/_al_u3739|u_logic/_al_u3824.b[1] (u_logic/_al_u3738_o) net (fanout = 1) 0.941 r 17.627
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u_logic/_al_u3739|u_logic/_al_u3824.f[1] cell 0.333 r 17.960
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u_logic/_al_u3740.c[1] (u_logic/_al_u3739_o) net (fanout = 2) 0.525 r 18.485
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u_logic/_al_u3740.fx[0] cell 0.448 r 18.933
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u_logic/_al_u3741|u_logic/W7max6_reg.c[1] (u_logic/Y4miu6) net (fanout = 2) 1.510 r 20.443 ../rtl/topmodule/cortexm0ds_logic.v(599)
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u_logic/_al_u3741|u_logic/W7max6_reg.f[1] cell 0.348 r 20.791
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u_logic/_al_u3746|u_logic/Wdmax6_reg.b[1] (u_logic/_al_u3741_o) net (fanout = 1) 0.456 r 21.247
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u_logic/_al_u3746|u_logic/Wdmax6_reg.f[1] cell 0.333 r 21.580
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u_logic/_al_u3773|u_logic/_al_u3816.a[1] (u_logic/_al_u3746_o) net (fanout = 1) 0.526 r 22.106
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u_logic/_al_u3773|u_logic/_al_u3816.f[1] cell 0.424 r 22.530
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u_logic/_al_u3866|u_logic/_al_u3823.a[1] (u_logic/_al_u3773_o) net (fanout = 1) 0.618 r 23.148
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u_logic/_al_u3866|u_logic/_al_u3823.f[1] cell 0.424 r 23.572
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u_logic/_al_u3681|u_logic/_al_u3941.b[0] (u_logic/_al_u3866_o) net (fanout = 1) 0.676 r 24.248
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u_logic/_al_u3681|u_logic/_al_u3941.f[0] cell 0.431 r 24.679
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u_logic/_al_u3942.a[1] (u_logic/_al_u3941_o) net (fanout = 3) 0.468 r 25.147
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u_logic/_al_u3942.fx[0] cell 0.618 r 25.765
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u_logic/_al_u4026.a[0] (u_logic/_al_u3942_o) net (fanout = 3) 1.220 r 26.985
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u_logic/_al_u4026.fx[0] cell 0.618 r 27.603
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u_logic/Vgjpw6_reg.a[1] (u_logic/_al_u4026_o) net (fanout = 2) 0.625 r 28.228 ../rtl/topmodule/cortexm0ds_logic.v(1587)
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u_logic/Vgjpw6_reg path2reg0 0.732 28.960
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Arrival time 28.960 (19 lvl)
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u_logic/Vgjpw6_reg.clk 0.000 0.000
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capture clock edge 20.000 20.000
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cell setup -0.116 19.884
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clock uncertainty -0.000 19.884
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clock recovergence pessimism 0.000 19.884
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Required time 19.884
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---------------------------------------------------------------------------------------------------------
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Slack -9.076ns
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---------------------------------------------------------------------------------------------------------
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Slack (setup check): -9.076 ns
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Start Point: u_logic/M6kax6_reg.clk (rising edge triggered by clock DeriveClock)
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End Point: u_logic/Vgjpw6_reg.a[0] (rising edge triggered by clock DeriveClock)
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Clock group: DeriveClock
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Data Path Delay: 28.960ns (logic 11.140ns, net 17.820ns, 38% logic)
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Logic Levels: 19
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Point Type Incr Path Info
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---------------------------------------------------------------------------------------------------------
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u_logic/M6kax6_reg.clk clock 0.000 0.000
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launch clock edge 0.000 0.000
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u_logic/M6kax6_reg.q[0] clk2q 0.146 r 0.146
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u_logic/_al_u182|u_logic/_al_u192.b[1] (u_logic/M6kax6) net (fanout = 14) 1.014 r 1.160 ../rtl/topmodule/cortexm0ds_logic.v(1651)
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u_logic/_al_u182|u_logic/_al_u192.f[1] cell 0.333 r 1.493
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u_logic/_al_u239|u_logic/Ljwax6_reg.a[1] (u_logic/Wanow6_lutinv) net (fanout = 32) 4.192 r 5.685 ../rtl/topmodule/cortexm0ds_logic.v(1158)
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u_logic/_al_u239|u_logic/Ljwax6_reg.f[1] cell 0.424 r 6.109
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u_logic/_al_u219|u_logic/Llwax6_reg.c[0] (u_logic/_al_u239_o) net (fanout = 1) 0.456 r 6.565
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u_logic/_al_u219|u_logic/Llwax6_reg.f[0] cell 0.251 r 6.816
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u_logic/_al_u242|u_logic/_al_u272.d[1] (u_logic/S90iu6) net (fanout = 7) 1.520 r 8.336 ../rtl/topmodule/cortexm0ds_logic.v(307)
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u_logic/_al_u242|u_logic/_al_u272.f[1] cell 0.262 r 8.598
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u_logic/mult0_1_0_.a[0] (u_logic/Mifpw6[18]) net (fanout = 1) 0.672 r 9.270 ../rtl/topmodule/cortexm0ds_logic.v(1531)
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u_logic/mult0_1_0_.p[0] cell (MULT18) 3.563 r 12.833
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u_logic/u1/u0|u1/ucin.a[1] (u_logic/mult0_1_0_0) net (fanout = 1) 0.671 r 13.504
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u_logic/u1/u0|u1/ucin.f[1] cell 0.507 r 14.011
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u_logic/u2/u0|u2/ucin.b[1] (u_logic/n135[0]) net (fanout = 1) 0.738 r 14.749
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u_logic/u2/u0|u2/ucin.fco cell (ADDER) 0.539 r 15.288
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u_logic/u2/u2|u2/u1.fci (u_logic/u2/c1) net (fanout = 1) 0.000 f 15.288
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u_logic/u2/u2|u2/u1.f[0] cell 0.144 r 15.432
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u_logic/_al_u3820|u_logic/_al_u3738.d[0] (u_logic/n159[1]) net (fanout = 1) 0.992 r 16.424
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u_logic/_al_u3820|u_logic/_al_u3738.f[0] cell 0.262 r 16.686
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u_logic/_al_u3739|u_logic/_al_u3824.b[1] (u_logic/_al_u3738_o) net (fanout = 1) 0.941 r 17.627
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u_logic/_al_u3739|u_logic/_al_u3824.f[1] cell 0.333 r 17.960
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u_logic/_al_u3740.c[1] (u_logic/_al_u3739_o) net (fanout = 2) 0.525 r 18.485
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u_logic/_al_u3740.fx[0] cell 0.448 r 18.933
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u_logic/_al_u3741|u_logic/W7max6_reg.c[1] (u_logic/Y4miu6) net (fanout = 2) 1.510 r 20.443 ../rtl/topmodule/cortexm0ds_logic.v(599)
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u_logic/_al_u3741|u_logic/W7max6_reg.f[1] cell 0.348 r 20.791
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u_logic/_al_u3746|u_logic/Wdmax6_reg.b[1] (u_logic/_al_u3741_o) net (fanout = 1) 0.456 r 21.247
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u_logic/_al_u3746|u_logic/Wdmax6_reg.f[1] cell 0.333 r 21.580
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u_logic/_al_u3773|u_logic/_al_u3816.a[1] (u_logic/_al_u3746_o) net (fanout = 1) 0.526 r 22.106
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u_logic/_al_u3773|u_logic/_al_u3816.f[1] cell 0.424 r 22.530
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u_logic/_al_u3866|u_logic/_al_u3823.a[1] (u_logic/_al_u3773_o) net (fanout = 1) 0.618 r 23.148
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u_logic/_al_u3866|u_logic/_al_u3823.f[1] cell 0.424 r 23.572
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u_logic/_al_u3681|u_logic/_al_u3941.b[0] (u_logic/_al_u3866_o) net (fanout = 1) 0.676 r 24.248
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u_logic/_al_u3681|u_logic/_al_u3941.f[0] cell 0.431 r 24.679
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u_logic/_al_u3942.a[1] (u_logic/_al_u3941_o) net (fanout = 3) 0.468 r 25.147
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u_logic/_al_u3942.fx[0] cell 0.618 r 25.765
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u_logic/_al_u4026.a[1] (u_logic/_al_u3942_o) net (fanout = 3) 1.220 r 26.985
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u_logic/_al_u4026.fx[0] cell 0.618 r 27.603
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u_logic/Vgjpw6_reg.a[0] (u_logic/_al_u4026_o) net (fanout = 2) 0.625 r 28.228 ../rtl/topmodule/cortexm0ds_logic.v(1587)
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u_logic/Vgjpw6_reg path2reg0 0.732 28.960
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Arrival time 28.960 (19 lvl)
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u_logic/Vgjpw6_reg.clk 0.000 0.000
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capture clock edge 20.000 20.000
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cell setup -0.116 19.884
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clock uncertainty -0.000 19.884
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clock recovergence pessimism 0.000 19.884
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Required time 19.884
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---------------------------------------------------------------------------------------------------------
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Slack -9.076ns
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---------------------------------------------------------------------------------------------------------
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Paths for end point u_logic/_al_u2303|u_logic/Ydopw6_reg (3466379 paths)
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---------------------------------------------------------------------------------------------------------
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Slack (setup check): -8.671 ns
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Start Point: u_logic/M6kax6_reg.clk (rising edge triggered by clock DeriveClock)
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End Point: u_logic/_al_u2303|u_logic/Ydopw6_reg.a[0] (rising edge triggered by clock DeriveClock)
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Clock group: DeriveClock
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Data Path Delay: 28.555ns (logic 10.756ns, net 17.799ns, 37% logic)
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Logic Levels: 19
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Point Type Incr Path Info
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---------------------------------------------------------------------------------------------------------
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u_logic/M6kax6_reg.clk clock 0.000 0.000
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launch clock edge 0.000 0.000
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u_logic/M6kax6_reg.q[0] clk2q 0.146 r 0.146
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u_logic/_al_u182|u_logic/_al_u192.b[1] (u_logic/M6kax6) net (fanout = 14) 1.014 r 1.160 ../rtl/topmodule/cortexm0ds_logic.v(1651)
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u_logic/_al_u182|u_logic/_al_u192.f[1] cell 0.333 r 1.493
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u_logic/_al_u239|u_logic/Ljwax6_reg.a[1] (u_logic/Wanow6_lutinv) net (fanout = 32) 4.192 r 5.685 ../rtl/topmodule/cortexm0ds_logic.v(1158)
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u_logic/_al_u239|u_logic/Ljwax6_reg.f[1] cell 0.424 r 6.109
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u_logic/_al_u219|u_logic/Llwax6_reg.c[0] (u_logic/_al_u239_o) net (fanout = 1) 0.456 r 6.565
|
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u_logic/_al_u219|u_logic/Llwax6_reg.f[0] cell 0.251 r 6.816
|
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u_logic/_al_u242|u_logic/_al_u272.d[1] (u_logic/S90iu6) net (fanout = 7) 1.520 r 8.336 ../rtl/topmodule/cortexm0ds_logic.v(307)
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u_logic/_al_u242|u_logic/_al_u272.f[1] cell 0.262 r 8.598
|
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u_logic/mult0_1_0_.a[0] (u_logic/Mifpw6[18]) net (fanout = 1) 0.672 r 9.270 ../rtl/topmodule/cortexm0ds_logic.v(1531)
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u_logic/mult0_1_0_.p[0] cell (MULT18) 3.563 r 12.833
|
|
u_logic/u1/u0|u1/ucin.a[1] (u_logic/mult0_1_0_0) net (fanout = 1) 0.671 r 13.504
|
|
u_logic/u1/u0|u1/ucin.f[1] cell 0.507 r 14.011
|
|
u_logic/u2/u0|u2/ucin.b[1] (u_logic/n135[0]) net (fanout = 1) 0.738 r 14.749
|
|
u_logic/u2/u0|u2/ucin.fco cell (ADDER) 0.539 r 15.288
|
|
u_logic/u2/u2|u2/u1.fci (u_logic/u2/c1) net (fanout = 1) 0.000 f 15.288
|
|
u_logic/u2/u2|u2/u1.f[0] cell 0.144 r 15.432
|
|
u_logic/_al_u3820|u_logic/_al_u3738.d[0] (u_logic/n159[1]) net (fanout = 1) 0.992 r 16.424
|
|
u_logic/_al_u3820|u_logic/_al_u3738.f[0] cell 0.262 r 16.686
|
|
u_logic/_al_u3739|u_logic/_al_u3824.b[1] (u_logic/_al_u3738_o) net (fanout = 1) 0.941 r 17.627
|
|
u_logic/_al_u3739|u_logic/_al_u3824.f[1] cell 0.333 r 17.960
|
|
u_logic/_al_u3740.c[1] (u_logic/_al_u3739_o) net (fanout = 2) 0.525 r 18.485
|
|
u_logic/_al_u3740.fx[0] cell 0.448 r 18.933
|
|
u_logic/_al_u3741|u_logic/W7max6_reg.c[1] (u_logic/Y4miu6) net (fanout = 2) 1.510 r 20.443 ../rtl/topmodule/cortexm0ds_logic.v(599)
|
|
u_logic/_al_u3741|u_logic/W7max6_reg.f[1] cell 0.348 r 20.791
|
|
u_logic/_al_u3746|u_logic/Wdmax6_reg.b[1] (u_logic/_al_u3741_o) net (fanout = 1) 0.456 r 21.247
|
|
u_logic/_al_u3746|u_logic/Wdmax6_reg.f[1] cell 0.333 r 21.580
|
|
u_logic/_al_u3773|u_logic/_al_u3816.a[1] (u_logic/_al_u3746_o) net (fanout = 1) 0.526 r 22.106
|
|
u_logic/_al_u3773|u_logic/_al_u3816.f[1] cell 0.424 r 22.530
|
|
u_logic/_al_u3866|u_logic/_al_u3823.a[1] (u_logic/_al_u3773_o) net (fanout = 1) 0.618 r 23.148
|
|
u_logic/_al_u3866|u_logic/_al_u3823.f[1] cell 0.424 r 23.572
|
|
u_logic/_al_u3681|u_logic/_al_u3941.b[0] (u_logic/_al_u3866_o) net (fanout = 1) 0.676 r 24.248
|
|
u_logic/_al_u3681|u_logic/_al_u3941.f[0] cell 0.431 r 24.679
|
|
u_logic/_al_u3942.a[1] (u_logic/_al_u3941_o) net (fanout = 3) 0.468 r 25.147
|
|
u_logic/_al_u3942.fx[0] cell 0.618 r 25.765
|
|
u_logic/_al_u3977|u_logic/_al_u1507.a[1] (u_logic/_al_u3942_o) net (fanout = 3) 1.368 r 27.133
|
|
u_logic/_al_u3977|u_logic/_al_u1507.f[1] cell 0.424 r 27.557
|
|
u_logic/_al_u2303|u_logic/Ydopw6_reg.a[0] (u_logic/_al_u3977_o) net (fanout = 1) 0.456 r 28.013 ../rtl/topmodule/cortexm0ds_logic.v(1596)
|
|
u_logic/_al_u2303|u_logic/Ydopw6_reg path2reg0 0.542 28.555
|
|
Arrival time 28.555 (19 lvl)
|
|
|
|
u_logic/_al_u2303|u_logic/Ydopw6_reg.clk 0.000 0.000
|
|
capture clock edge 20.000 20.000
|
|
cell setup -0.116 19.884
|
|
clock uncertainty -0.000 19.884
|
|
clock recovergence pessimism 0.000 19.884
|
|
Required time 19.884
|
|
---------------------------------------------------------------------------------------------------------
|
|
Slack -8.671ns
|
|
|
|
---------------------------------------------------------------------------------------------------------
|
|
|
|
Slack (setup check): -8.671 ns
|
|
Start Point: u_logic/M6kax6_reg.clk (rising edge triggered by clock DeriveClock)
|
|
End Point: u_logic/_al_u2303|u_logic/Ydopw6_reg.a[0] (rising edge triggered by clock DeriveClock)
|
|
Clock group: DeriveClock
|
|
Data Path Delay: 28.555ns (logic 10.756ns, net 17.799ns, 37% logic)
|
|
Logic Levels: 19
|
|
|
|
Point Type Incr Path Info
|
|
---------------------------------------------------------------------------------------------------------
|
|
u_logic/M6kax6_reg.clk clock 0.000 0.000
|
|
launch clock edge 0.000 0.000
|
|
u_logic/M6kax6_reg.q[0] clk2q 0.146 r 0.146
|
|
u_logic/_al_u182|u_logic/_al_u192.b[1] (u_logic/M6kax6) net (fanout = 14) 1.014 r 1.160 ../rtl/topmodule/cortexm0ds_logic.v(1651)
|
|
u_logic/_al_u182|u_logic/_al_u192.f[1] cell 0.333 r 1.493
|
|
u_logic/_al_u239|u_logic/Ljwax6_reg.a[1] (u_logic/Wanow6_lutinv) net (fanout = 32) 4.192 r 5.685 ../rtl/topmodule/cortexm0ds_logic.v(1158)
|
|
u_logic/_al_u239|u_logic/Ljwax6_reg.f[1] cell 0.424 r 6.109
|
|
u_logic/_al_u219|u_logic/Llwax6_reg.c[0] (u_logic/_al_u239_o) net (fanout = 1) 0.456 r 6.565
|
|
u_logic/_al_u219|u_logic/Llwax6_reg.f[0] cell 0.251 r 6.816
|
|
u_logic/_al_u242|u_logic/_al_u272.d[1] (u_logic/S90iu6) net (fanout = 7) 1.520 r 8.336 ../rtl/topmodule/cortexm0ds_logic.v(307)
|
|
u_logic/_al_u242|u_logic/_al_u272.f[1] cell 0.262 r 8.598
|
|
u_logic/mult0_1_0_.a[0] (u_logic/Mifpw6[18]) net (fanout = 1) 0.672 r 9.270 ../rtl/topmodule/cortexm0ds_logic.v(1531)
|
|
u_logic/mult0_1_0_.p[0] cell (MULT18) 3.563 r 12.833
|
|
u_logic/u1/u0|u1/ucin.a[1] (u_logic/mult0_1_0_0) net (fanout = 1) 0.671 r 13.504
|
|
u_logic/u1/u0|u1/ucin.f[1] cell 0.507 r 14.011
|
|
u_logic/u2/u0|u2/ucin.b[1] (u_logic/n135[0]) net (fanout = 1) 0.738 r 14.749
|
|
u_logic/u2/u0|u2/ucin.fco cell (ADDER) 0.539 r 15.288
|
|
u_logic/u2/u2|u2/u1.fci (u_logic/u2/c1) net (fanout = 1) 0.000 f 15.288
|
|
u_logic/u2/u2|u2/u1.f[0] cell 0.144 r 15.432
|
|
u_logic/_al_u3820|u_logic/_al_u3738.d[0] (u_logic/n159[1]) net (fanout = 1) 0.992 r 16.424
|
|
u_logic/_al_u3820|u_logic/_al_u3738.f[0] cell 0.262 r 16.686
|
|
u_logic/_al_u3739|u_logic/_al_u3824.b[1] (u_logic/_al_u3738_o) net (fanout = 1) 0.941 r 17.627
|
|
u_logic/_al_u3739|u_logic/_al_u3824.f[1] cell 0.333 r 17.960
|
|
u_logic/_al_u3740.c[0] (u_logic/_al_u3739_o) net (fanout = 2) 0.525 r 18.485
|
|
u_logic/_al_u3740.fx[0] cell 0.448 r 18.933
|
|
u_logic/_al_u3741|u_logic/W7max6_reg.c[1] (u_logic/Y4miu6) net (fanout = 2) 1.510 r 20.443 ../rtl/topmodule/cortexm0ds_logic.v(599)
|
|
u_logic/_al_u3741|u_logic/W7max6_reg.f[1] cell 0.348 r 20.791
|
|
u_logic/_al_u3746|u_logic/Wdmax6_reg.b[1] (u_logic/_al_u3741_o) net (fanout = 1) 0.456 r 21.247
|
|
u_logic/_al_u3746|u_logic/Wdmax6_reg.f[1] cell 0.333 r 21.580
|
|
u_logic/_al_u3773|u_logic/_al_u3816.a[1] (u_logic/_al_u3746_o) net (fanout = 1) 0.526 r 22.106
|
|
u_logic/_al_u3773|u_logic/_al_u3816.f[1] cell 0.424 r 22.530
|
|
u_logic/_al_u3866|u_logic/_al_u3823.a[1] (u_logic/_al_u3773_o) net (fanout = 1) 0.618 r 23.148
|
|
u_logic/_al_u3866|u_logic/_al_u3823.f[1] cell 0.424 r 23.572
|
|
u_logic/_al_u3681|u_logic/_al_u3941.b[0] (u_logic/_al_u3866_o) net (fanout = 1) 0.676 r 24.248
|
|
u_logic/_al_u3681|u_logic/_al_u3941.f[0] cell 0.431 r 24.679
|
|
u_logic/_al_u3942.a[1] (u_logic/_al_u3941_o) net (fanout = 3) 0.468 r 25.147
|
|
u_logic/_al_u3942.fx[0] cell 0.618 r 25.765
|
|
u_logic/_al_u3977|u_logic/_al_u1507.a[1] (u_logic/_al_u3942_o) net (fanout = 3) 1.368 r 27.133
|
|
u_logic/_al_u3977|u_logic/_al_u1507.f[1] cell 0.424 r 27.557
|
|
u_logic/_al_u2303|u_logic/Ydopw6_reg.a[0] (u_logic/_al_u3977_o) net (fanout = 1) 0.456 r 28.013 ../rtl/topmodule/cortexm0ds_logic.v(1596)
|
|
u_logic/_al_u2303|u_logic/Ydopw6_reg path2reg0 0.542 28.555
|
|
Arrival time 28.555 (19 lvl)
|
|
|
|
u_logic/_al_u2303|u_logic/Ydopw6_reg.clk 0.000 0.000
|
|
capture clock edge 20.000 20.000
|
|
cell setup -0.116 19.884
|
|
clock uncertainty -0.000 19.884
|
|
clock recovergence pessimism 0.000 19.884
|
|
Required time 19.884
|
|
---------------------------------------------------------------------------------------------------------
|
|
Slack -8.671ns
|
|
|
|
---------------------------------------------------------------------------------------------------------
|
|
|
|
Slack (setup check): -8.671 ns
|
|
Start Point: u_logic/M6kax6_reg.clk (rising edge triggered by clock DeriveClock)
|
|
End Point: u_logic/_al_u2303|u_logic/Ydopw6_reg.a[0] (rising edge triggered by clock DeriveClock)
|
|
Clock group: DeriveClock
|
|
Data Path Delay: 28.555ns (logic 10.756ns, net 17.799ns, 37% logic)
|
|
Logic Levels: 19
|
|
|
|
Point Type Incr Path Info
|
|
---------------------------------------------------------------------------------------------------------
|
|
u_logic/M6kax6_reg.clk clock 0.000 0.000
|
|
launch clock edge 0.000 0.000
|
|
u_logic/M6kax6_reg.q[0] clk2q 0.146 r 0.146
|
|
u_logic/_al_u182|u_logic/_al_u192.b[1] (u_logic/M6kax6) net (fanout = 14) 1.014 r 1.160 ../rtl/topmodule/cortexm0ds_logic.v(1651)
|
|
u_logic/_al_u182|u_logic/_al_u192.f[1] cell 0.333 r 1.493
|
|
u_logic/_al_u239|u_logic/Ljwax6_reg.a[1] (u_logic/Wanow6_lutinv) net (fanout = 32) 4.192 r 5.685 ../rtl/topmodule/cortexm0ds_logic.v(1158)
|
|
u_logic/_al_u239|u_logic/Ljwax6_reg.f[1] cell 0.424 r 6.109
|
|
u_logic/_al_u219|u_logic/Llwax6_reg.c[0] (u_logic/_al_u239_o) net (fanout = 1) 0.456 r 6.565
|
|
u_logic/_al_u219|u_logic/Llwax6_reg.f[0] cell 0.251 r 6.816
|
|
u_logic/_al_u242|u_logic/_al_u272.d[1] (u_logic/S90iu6) net (fanout = 7) 1.520 r 8.336 ../rtl/topmodule/cortexm0ds_logic.v(307)
|
|
u_logic/_al_u242|u_logic/_al_u272.f[1] cell 0.262 r 8.598
|
|
u_logic/mult0_1_0_.a[0] (u_logic/Mifpw6[18]) net (fanout = 1) 0.672 r 9.270 ../rtl/topmodule/cortexm0ds_logic.v(1531)
|
|
u_logic/mult0_1_0_.p[0] cell (MULT18) 3.563 r 12.833
|
|
u_logic/u1/u0|u1/ucin.a[1] (u_logic/mult0_1_0_0) net (fanout = 1) 0.671 r 13.504
|
|
u_logic/u1/u0|u1/ucin.f[1] cell 0.507 r 14.011
|
|
u_logic/u2/u0|u2/ucin.b[1] (u_logic/n135[0]) net (fanout = 1) 0.738 r 14.749
|
|
u_logic/u2/u0|u2/ucin.fco cell (ADDER) 0.539 r 15.288
|
|
u_logic/u2/u2|u2/u1.fci (u_logic/u2/c1) net (fanout = 1) 0.000 f 15.288
|
|
u_logic/u2/u2|u2/u1.f[0] cell 0.144 r 15.432
|
|
u_logic/_al_u3820|u_logic/_al_u3738.d[0] (u_logic/n159[1]) net (fanout = 1) 0.992 r 16.424
|
|
u_logic/_al_u3820|u_logic/_al_u3738.f[0] cell 0.262 r 16.686
|
|
u_logic/_al_u3739|u_logic/_al_u3824.b[1] (u_logic/_al_u3738_o) net (fanout = 1) 0.941 r 17.627
|
|
u_logic/_al_u3739|u_logic/_al_u3824.f[1] cell 0.333 r 17.960
|
|
u_logic/_al_u3740.c[1] (u_logic/_al_u3739_o) net (fanout = 2) 0.525 r 18.485
|
|
u_logic/_al_u3740.fx[0] cell 0.448 r 18.933
|
|
u_logic/_al_u3741|u_logic/W7max6_reg.c[1] (u_logic/Y4miu6) net (fanout = 2) 1.510 r 20.443 ../rtl/topmodule/cortexm0ds_logic.v(599)
|
|
u_logic/_al_u3741|u_logic/W7max6_reg.f[1] cell 0.348 r 20.791
|
|
u_logic/_al_u3746|u_logic/Wdmax6_reg.b[1] (u_logic/_al_u3741_o) net (fanout = 1) 0.456 r 21.247
|
|
u_logic/_al_u3746|u_logic/Wdmax6_reg.f[1] cell 0.333 r 21.580
|
|
u_logic/_al_u3773|u_logic/_al_u3816.a[1] (u_logic/_al_u3746_o) net (fanout = 1) 0.526 r 22.106
|
|
u_logic/_al_u3773|u_logic/_al_u3816.f[1] cell 0.424 r 22.530
|
|
u_logic/_al_u3866|u_logic/_al_u3823.a[1] (u_logic/_al_u3773_o) net (fanout = 1) 0.618 r 23.148
|
|
u_logic/_al_u3866|u_logic/_al_u3823.f[1] cell 0.424 r 23.572
|
|
u_logic/_al_u3681|u_logic/_al_u3941.b[0] (u_logic/_al_u3866_o) net (fanout = 1) 0.676 r 24.248
|
|
u_logic/_al_u3681|u_logic/_al_u3941.f[0] cell 0.431 r 24.679
|
|
u_logic/_al_u3942.a[0] (u_logic/_al_u3941_o) net (fanout = 3) 0.468 r 25.147
|
|
u_logic/_al_u3942.fx[0] cell 0.618 r 25.765
|
|
u_logic/_al_u3977|u_logic/_al_u1507.a[1] (u_logic/_al_u3942_o) net (fanout = 3) 1.368 r 27.133
|
|
u_logic/_al_u3977|u_logic/_al_u1507.f[1] cell 0.424 r 27.557
|
|
u_logic/_al_u2303|u_logic/Ydopw6_reg.a[0] (u_logic/_al_u3977_o) net (fanout = 1) 0.456 r 28.013 ../rtl/topmodule/cortexm0ds_logic.v(1596)
|
|
u_logic/_al_u2303|u_logic/Ydopw6_reg path2reg0 0.542 28.555
|
|
Arrival time 28.555 (19 lvl)
|
|
|
|
u_logic/_al_u2303|u_logic/Ydopw6_reg.clk 0.000 0.000
|
|
capture clock edge 20.000 20.000
|
|
cell setup -0.116 19.884
|
|
clock uncertainty -0.000 19.884
|
|
clock recovergence pessimism 0.000 19.884
|
|
Required time 19.884
|
|
---------------------------------------------------------------------------------------------------------
|
|
Slack -8.671ns
|
|
|
|
---------------------------------------------------------------------------------------------------------
|
|
|
|
Paths for end point u_logic/Jvvpw6_reg (2982027 paths)
|
|
---------------------------------------------------------------------------------------------------------
|
|
Slack (setup check): -5.988 ns
|
|
Start Point: u_logic/_al_u1478|u_logic/Htmpw6_reg.clk (rising edge triggered by clock DeriveClock)
|
|
End Point: u_logic/Jvvpw6_reg.a[1] (rising edge triggered by clock DeriveClock)
|
|
Clock group: DeriveClock
|
|
Data Path Delay: 25.872ns (logic 8.140ns, net 17.732ns, 31% logic)
|
|
Logic Levels: 18
|
|
|
|
Point Type Incr Path Info
|
|
---------------------------------------------------------------------------------------------------------
|
|
u_logic/_al_u1478|u_logic/Htmpw6_reg.clk clock 0.000 0.000
|
|
launch clock edge 0.000 0.000
|
|
u_logic/_al_u1478|u_logic/Htmpw6_reg.q[0] clk2q 0.146 r 0.146
|
|
u_logic/_al_u745|u_logic/_al_u1128.a[0] (u_logic/Htmpw6) net (fanout = 18) 1.084 r 1.230 ../rtl/topmodule/cortexm0ds_logic.v(1593)
|
|
u_logic/_al_u745|u_logic/_al_u1128.f[0] cell 0.408 r 1.638
|
|
u_logic/_al_u1193|u_logic/Exypw6_reg.a[1] (u_logic/Qiqow6) net (fanout = 33) 2.529 r 4.167 ../rtl/topmodule/cortexm0ds_logic.v(1201)
|
|
u_logic/_al_u1193|u_logic/Exypw6_reg.f[1] cell 0.408 r 4.575
|
|
u_logic/_al_u1405|u_logic/_al_u1194.a[0] (u_logic/_al_u1193_o) net (fanout = 1) 0.459 r 5.034
|
|
u_logic/_al_u1405|u_logic/_al_u1194.f[0] cell 0.424 r 5.458
|
|
u_logic/T80qw6_reg|u_logic/Tk0qw6_reg.a[0] (u_logic/_al_u1194_o) net (fanout = 1) 0.594 r 6.052
|
|
u_logic/T80qw6_reg|u_logic/Tk0qw6_reg.f[0] cell 0.424 r 6.476
|
|
u_logic/Odnax6_reg|u_logic/S1nax6_reg.a[0] (u_logic/_al_u1195_o) net (fanout = 1) 0.526 r 7.002
|
|
u_logic/Odnax6_reg|u_logic/S1nax6_reg.f[0] cell 0.424 r 7.426
|
|
u_logic/_al_u1701|u_logic/_al_u1641.a[0] (u_logic/_al_u1197_o) net (fanout = 6) 1.453 r 8.879
|
|
u_logic/_al_u1701|u_logic/_al_u1641.f[0] cell 0.408 r 9.287
|
|
u_logic/_al_u1643|u_logic/_al_u3843.d[1] (u_logic/Zu6ju6) net (fanout = 1) 0.456 r 9.743 ../rtl/topmodule/cortexm0ds_logic.v(876)
|
|
u_logic/_al_u1643|u_logic/_al_u3843.f[1] cell 0.262 r 10.005
|
|
u_logic/add3_add4/u7_al_u4816.a[0] (u_logic/S2epw6) net (fanout = 3) 1.038 r 11.043 ../rtl/topmodule/cortexm0ds_logic.v(1516)
|
|
u_logic/add3_add4/u7_al_u4816.fco cell (ADDER) 0.947 r 11.990
|
|
u_logic/add3_add4/u11_al_u4817.fci (u_logic/add3_add4/c11) net (fanout = 1) 0.000 f 11.990 ../rtl/topmodule/cortexm0ds_logic.v(3159)
|
|
u_logic/add3_add4/u11_al_u4817.fco cell (ADDER) 0.132 r 12.122
|
|
u_logic/add3_add4/u15_al_u4818.fci (u_logic/add3_add4/c15) net (fanout = 1) 0.000 f 12.122 ../rtl/topmodule/cortexm0ds_logic.v(3159)
|
|
u_logic/add3_add4/u15_al_u4818.fco cell (ADDER) 0.132 r 12.254
|
|
u_logic/add3_add4/u19_al_u4819.fci (u_logic/add3_add4/c19) net (fanout = 1) 0.000 f 12.254 ../rtl/topmodule/cortexm0ds_logic.v(3159)
|
|
u_logic/add3_add4/u19_al_u4819.fx[1] cell 0.453 r 12.707
|
|
u_logic/_al_u2504|u_logic/_al_u2496.d[1] (u_logic/Nxkbx6[23]) net (fanout = 3) 0.890 r 13.597 ../rtl/topmodule/cortexm0ds_logic.v(1721)
|
|
u_logic/_al_u2504|u_logic/_al_u2496.f[1] cell 0.262 r 13.859
|
|
u_logic/_al_u2484|u_logic/_al_u2505.d[0] (u_logic/Me6pw6) net (fanout = 1) 0.468 r 14.327 ../rtl/topmodule/cortexm0ds_logic.v(1413)
|
|
u_logic/_al_u2484|u_logic/_al_u2505.f[0] cell 0.262 r 14.589
|
|
u_logic/N3hbx6_reg|u_logic/Tsdbx6_reg.a[1] (u_logic/_al_u2505_o) net (fanout = 15) 1.611 r 16.200
|
|
u_logic/N3hbx6_reg|u_logic/Tsdbx6_reg.f[1] cell 0.424 r 16.624
|
|
u_logic/_al_u3637|u_logic/Dk9bx6_reg.d[0] (u_logic/_al_u3543_o) net (fanout = 1) 0.738 r 17.362
|
|
u_logic/_al_u3637|u_logic/Dk9bx6_reg.f[0] cell 0.205 r 17.567
|
|
u_logic/Gkeax6_reg|u_logic/Hpbbx6_reg.a[1] (u_logic/_al_u3544_o) net (fanout = 1) 1.565 r 19.132
|
|
u_logic/Gkeax6_reg|u_logic/Hpbbx6_reg.f[1] cell 0.424 r 19.556
|
|
u_logic/Dmeax6_reg|u_logic/Daebx6_reg.a[1] (u_logic/_al_u3546_o) net (fanout = 1) 0.307 r 19.863
|
|
u_logic/Dmeax6_reg|u_logic/Daebx6_reg.f[1] cell 0.424 r 20.287
|
|
u_logic/_al_u3186|u_logic/Tfcax6_reg.b[0] (u_logic/_al_u3550_o) net (fanout = 1) 0.806 r 21.093
|
|
u_logic/_al_u3186|u_logic/Tfcax6_reg.f[0] cell 0.431 r 21.524
|
|
u_logic/Tceax6_reg|u_logic/C1fax6_reg.a[1] (u_logic/_al_u3559_o) net (fanout = 2) 1.136 r 22.660
|
|
u_logic/Tceax6_reg|u_logic/C1fax6_reg.f[1] cell 0.408 r 23.068
|
|
u_logic/Jvvpw6_reg.a[1] (u_logic/Dx7iu6) net (fanout = 2) 2.072 r 25.140 ../rtl/topmodule/cortexm0ds_logic.v(409)
|
|
u_logic/Jvvpw6_reg path2reg0 0.732 25.872
|
|
Arrival time 25.872 (18 lvl)
|
|
|
|
u_logic/Jvvpw6_reg.clk 0.000 0.000
|
|
capture clock edge 20.000 20.000
|
|
cell setup -0.116 19.884
|
|
clock uncertainty -0.000 19.884
|
|
clock recovergence pessimism 0.000 19.884
|
|
Required time 19.884
|
|
---------------------------------------------------------------------------------------------------------
|
|
Slack -5.988ns
|
|
|
|
---------------------------------------------------------------------------------------------------------
|
|
|
|
Slack (setup check): -5.988 ns
|
|
Start Point: u_logic/_al_u1478|u_logic/Htmpw6_reg.clk (rising edge triggered by clock DeriveClock)
|
|
End Point: u_logic/Jvvpw6_reg.a[0] (rising edge triggered by clock DeriveClock)
|
|
Clock group: DeriveClock
|
|
Data Path Delay: 25.872ns (logic 8.140ns, net 17.732ns, 31% logic)
|
|
Logic Levels: 18
|
|
|
|
Point Type Incr Path Info
|
|
---------------------------------------------------------------------------------------------------------
|
|
u_logic/_al_u1478|u_logic/Htmpw6_reg.clk clock 0.000 0.000
|
|
launch clock edge 0.000 0.000
|
|
u_logic/_al_u1478|u_logic/Htmpw6_reg.q[0] clk2q 0.146 r 0.146
|
|
u_logic/_al_u745|u_logic/_al_u1128.a[0] (u_logic/Htmpw6) net (fanout = 18) 1.084 r 1.230 ../rtl/topmodule/cortexm0ds_logic.v(1593)
|
|
u_logic/_al_u745|u_logic/_al_u1128.f[0] cell 0.408 r 1.638
|
|
u_logic/_al_u1193|u_logic/Exypw6_reg.a[1] (u_logic/Qiqow6) net (fanout = 33) 2.529 r 4.167 ../rtl/topmodule/cortexm0ds_logic.v(1201)
|
|
u_logic/_al_u1193|u_logic/Exypw6_reg.f[1] cell 0.408 r 4.575
|
|
u_logic/_al_u1405|u_logic/_al_u1194.a[0] (u_logic/_al_u1193_o) net (fanout = 1) 0.459 r 5.034
|
|
u_logic/_al_u1405|u_logic/_al_u1194.f[0] cell 0.424 r 5.458
|
|
u_logic/T80qw6_reg|u_logic/Tk0qw6_reg.a[0] (u_logic/_al_u1194_o) net (fanout = 1) 0.594 r 6.052
|
|
u_logic/T80qw6_reg|u_logic/Tk0qw6_reg.f[0] cell 0.424 r 6.476
|
|
u_logic/Odnax6_reg|u_logic/S1nax6_reg.a[0] (u_logic/_al_u1195_o) net (fanout = 1) 0.526 r 7.002
|
|
u_logic/Odnax6_reg|u_logic/S1nax6_reg.f[0] cell 0.424 r 7.426
|
|
u_logic/_al_u1701|u_logic/_al_u1641.a[0] (u_logic/_al_u1197_o) net (fanout = 6) 1.453 r 8.879
|
|
u_logic/_al_u1701|u_logic/_al_u1641.f[0] cell 0.408 r 9.287
|
|
u_logic/_al_u1643|u_logic/_al_u3843.d[1] (u_logic/Zu6ju6) net (fanout = 1) 0.456 r 9.743 ../rtl/topmodule/cortexm0ds_logic.v(876)
|
|
u_logic/_al_u1643|u_logic/_al_u3843.f[1] cell 0.262 r 10.005
|
|
u_logic/add3_add4/u7_al_u4816.a[0] (u_logic/S2epw6) net (fanout = 3) 1.038 r 11.043 ../rtl/topmodule/cortexm0ds_logic.v(1516)
|
|
u_logic/add3_add4/u7_al_u4816.fco cell (ADDER) 0.947 r 11.990
|
|
u_logic/add3_add4/u11_al_u4817.fci (u_logic/add3_add4/c11) net (fanout = 1) 0.000 f 11.990 ../rtl/topmodule/cortexm0ds_logic.v(3159)
|
|
u_logic/add3_add4/u11_al_u4817.fco cell (ADDER) 0.132 r 12.122
|
|
u_logic/add3_add4/u15_al_u4818.fci (u_logic/add3_add4/c15) net (fanout = 1) 0.000 f 12.122 ../rtl/topmodule/cortexm0ds_logic.v(3159)
|
|
u_logic/add3_add4/u15_al_u4818.fco cell (ADDER) 0.132 r 12.254
|
|
u_logic/add3_add4/u19_al_u4819.fci (u_logic/add3_add4/c19) net (fanout = 1) 0.000 f 12.254 ../rtl/topmodule/cortexm0ds_logic.v(3159)
|
|
u_logic/add3_add4/u19_al_u4819.fx[1] cell 0.453 r 12.707
|
|
u_logic/_al_u2504|u_logic/_al_u2496.d[1] (u_logic/Nxkbx6[23]) net (fanout = 3) 0.890 r 13.597 ../rtl/topmodule/cortexm0ds_logic.v(1721)
|
|
u_logic/_al_u2504|u_logic/_al_u2496.f[1] cell 0.262 r 13.859
|
|
u_logic/_al_u2484|u_logic/_al_u2505.d[0] (u_logic/Me6pw6) net (fanout = 1) 0.468 r 14.327 ../rtl/topmodule/cortexm0ds_logic.v(1413)
|
|
u_logic/_al_u2484|u_logic/_al_u2505.f[0] cell 0.262 r 14.589
|
|
u_logic/N3hbx6_reg|u_logic/Tsdbx6_reg.a[1] (u_logic/_al_u2505_o) net (fanout = 15) 1.611 r 16.200
|
|
u_logic/N3hbx6_reg|u_logic/Tsdbx6_reg.f[1] cell 0.424 r 16.624
|
|
u_logic/_al_u3637|u_logic/Dk9bx6_reg.d[0] (u_logic/_al_u3543_o) net (fanout = 1) 0.738 r 17.362
|
|
u_logic/_al_u3637|u_logic/Dk9bx6_reg.f[0] cell 0.205 r 17.567
|
|
u_logic/Gkeax6_reg|u_logic/Hpbbx6_reg.a[1] (u_logic/_al_u3544_o) net (fanout = 1) 1.565 r 19.132
|
|
u_logic/Gkeax6_reg|u_logic/Hpbbx6_reg.f[1] cell 0.424 r 19.556
|
|
u_logic/Dmeax6_reg|u_logic/Daebx6_reg.a[1] (u_logic/_al_u3546_o) net (fanout = 1) 0.307 r 19.863
|
|
u_logic/Dmeax6_reg|u_logic/Daebx6_reg.f[1] cell 0.424 r 20.287
|
|
u_logic/_al_u3186|u_logic/Tfcax6_reg.b[0] (u_logic/_al_u3550_o) net (fanout = 1) 0.806 r 21.093
|
|
u_logic/_al_u3186|u_logic/Tfcax6_reg.f[0] cell 0.431 r 21.524
|
|
u_logic/Tceax6_reg|u_logic/C1fax6_reg.a[1] (u_logic/_al_u3559_o) net (fanout = 2) 1.136 r 22.660
|
|
u_logic/Tceax6_reg|u_logic/C1fax6_reg.f[1] cell 0.408 r 23.068
|
|
u_logic/Jvvpw6_reg.a[0] (u_logic/Dx7iu6) net (fanout = 2) 2.072 r 25.140 ../rtl/topmodule/cortexm0ds_logic.v(409)
|
|
u_logic/Jvvpw6_reg path2reg0 0.732 25.872
|
|
Arrival time 25.872 (18 lvl)
|
|
|
|
u_logic/Jvvpw6_reg.clk 0.000 0.000
|
|
capture clock edge 20.000 20.000
|
|
cell setup -0.116 19.884
|
|
clock uncertainty -0.000 19.884
|
|
clock recovergence pessimism 0.000 19.884
|
|
Required time 19.884
|
|
---------------------------------------------------------------------------------------------------------
|
|
Slack -5.988ns
|
|
|
|
---------------------------------------------------------------------------------------------------------
|
|
|
|
Slack (setup check): -5.967 ns
|
|
Start Point: u_logic/Hirpw6_reg.clk (rising edge triggered by clock DeriveClock)
|
|
End Point: u_logic/Jvvpw6_reg.a[1] (rising edge triggered by clock DeriveClock)
|
|
Clock group: DeriveClock
|
|
Data Path Delay: 25.851ns (logic 7.205ns, net 18.646ns, 27% logic)
|
|
Logic Levels: 17
|
|
|
|
Point Type Incr Path Info
|
|
---------------------------------------------------------------------------------------------------------
|
|
u_logic/Hirpw6_reg.clk clock 0.000 0.000
|
|
launch clock edge 0.000 0.000
|
|
u_logic/Hirpw6_reg.q[0] clk2q 0.146 r 0.146
|
|
u_logic/_al_u160|u_logic/_al_u664.c[0] (u_logic/Hirpw6) net (fanout = 89) 1.768 r 1.914 ../rtl/topmodule/cortexm0ds_logic.v(1601)
|
|
u_logic/_al_u160|u_logic/_al_u664.f[0] cell 0.251 r 2.165
|
|
u_logic/_al_u665.b[1] (u_logic/Frziu6_lutinv) net (fanout = 19) 1.361 r 3.526 ../rtl/topmodule/cortexm0ds_logic.v(781)
|
|
u_logic/_al_u665.fx[0] cell 0.543 r 4.069
|
|
u_logic/_al_u667|u_logic/_al_u910.a[1] (u_logic/_al_u665_o) net (fanout = 1) 0.625 r 4.694
|
|
u_logic/_al_u667|u_logic/_al_u910.f[1] cell 0.408 r 5.102
|
|
u_logic/_al_u1474|u_logic/_al_u673.a[0] (u_logic/_al_u667_o) net (fanout = 1) 0.519 r 5.621
|
|
u_logic/_al_u1474|u_logic/_al_u673.f[0] cell 0.424 r 6.045
|
|
u_logic/_al_u783|u_logic/Eotax6_reg.b[1] (u_logic/_al_u673_o) net (fanout = 32) 2.789 r 8.834
|
|
u_logic/_al_u783|u_logic/Eotax6_reg.f[1] cell 0.431 r 9.265
|
|
u_logic/_al_u784|u_logic/_al_u791.d[1] (u_logic/_al_u783_o) net (fanout = 4) 0.712 r 9.977
|
|
u_logic/_al_u784|u_logic/_al_u791.f[1] cell 0.262 r 10.239
|
|
u_logic/add3_add4/u15_al_u4818.d[1] (u_logic/Idfpw6[17]) net (fanout = 1) 1.279 r 11.518 ../rtl/topmodule/cortexm0ds_logic.v(1528)
|
|
u_logic/add3_add4/u15_al_u4818.fco cell (ADDER) 0.715 r 12.233
|
|
u_logic/add3_add4/u19_al_u4819.fci (u_logic/add3_add4/c19) net (fanout = 1) 0.000 f 12.233 ../rtl/topmodule/cortexm0ds_logic.v(3159)
|
|
u_logic/add3_add4/u19_al_u4819.fx[1] cell 0.453 r 12.686
|
|
u_logic/_al_u2504|u_logic/_al_u2496.d[1] (u_logic/Nxkbx6[23]) net (fanout = 3) 0.890 r 13.576 ../rtl/topmodule/cortexm0ds_logic.v(1721)
|
|
u_logic/_al_u2504|u_logic/_al_u2496.f[1] cell 0.262 r 13.838
|
|
u_logic/_al_u2484|u_logic/_al_u2505.d[0] (u_logic/Me6pw6) net (fanout = 1) 0.468 r 14.306 ../rtl/topmodule/cortexm0ds_logic.v(1413)
|
|
u_logic/_al_u2484|u_logic/_al_u2505.f[0] cell 0.262 r 14.568
|
|
u_logic/N3hbx6_reg|u_logic/Tsdbx6_reg.a[1] (u_logic/_al_u2505_o) net (fanout = 15) 1.611 r 16.179
|
|
u_logic/N3hbx6_reg|u_logic/Tsdbx6_reg.f[1] cell 0.424 r 16.603
|
|
u_logic/_al_u3637|u_logic/Dk9bx6_reg.d[0] (u_logic/_al_u3543_o) net (fanout = 1) 0.738 r 17.341
|
|
u_logic/_al_u3637|u_logic/Dk9bx6_reg.f[0] cell 0.205 r 17.546
|
|
u_logic/Gkeax6_reg|u_logic/Hpbbx6_reg.a[1] (u_logic/_al_u3544_o) net (fanout = 1) 1.565 r 19.111
|
|
u_logic/Gkeax6_reg|u_logic/Hpbbx6_reg.f[1] cell 0.424 r 19.535
|
|
u_logic/Dmeax6_reg|u_logic/Daebx6_reg.a[1] (u_logic/_al_u3546_o) net (fanout = 1) 0.307 r 19.842
|
|
u_logic/Dmeax6_reg|u_logic/Daebx6_reg.f[1] cell 0.424 r 20.266
|
|
u_logic/_al_u3186|u_logic/Tfcax6_reg.b[0] (u_logic/_al_u3550_o) net (fanout = 1) 0.806 r 21.072
|
|
u_logic/_al_u3186|u_logic/Tfcax6_reg.f[0] cell 0.431 r 21.503
|
|
u_logic/Tceax6_reg|u_logic/C1fax6_reg.a[1] (u_logic/_al_u3559_o) net (fanout = 2) 1.136 r 22.639
|
|
u_logic/Tceax6_reg|u_logic/C1fax6_reg.f[1] cell 0.408 r 23.047
|
|
u_logic/Jvvpw6_reg.a[1] (u_logic/Dx7iu6) net (fanout = 2) 2.072 r 25.119 ../rtl/topmodule/cortexm0ds_logic.v(409)
|
|
u_logic/Jvvpw6_reg path2reg0 0.732 25.851
|
|
Arrival time 25.851 (17 lvl)
|
|
|
|
u_logic/Jvvpw6_reg.clk 0.000 0.000
|
|
capture clock edge 20.000 20.000
|
|
cell setup -0.116 19.884
|
|
clock uncertainty -0.000 19.884
|
|
clock recovergence pessimism 0.000 19.884
|
|
Required time 19.884
|
|
---------------------------------------------------------------------------------------------------------
|
|
Slack -5.967ns
|
|
|
|
---------------------------------------------------------------------------------------------------------
|
|
|
|
Hold checks:
|
|
---------------------------------------------------------------------------------------------------------
|
|
Paths for end point RAM_DATA/ram_mem_unify_al_u30_4096x8_sub_000000_000 (12 paths)
|
|
---------------------------------------------------------------------------------------------------------
|
|
Slack (hold check): 0.229 ns
|
|
Start Point: RAMDATA_Interface/reg0_b4|RAMDATA_Interface/reg0_b10.clk (rising edge triggered by clock DeriveClock)
|
|
End Point: RAM_DATA/ram_mem_unify_al_u30_4096x8_sub_000000_000.addra[11] (rising edge triggered by clock DeriveClock)
|
|
Clock group: DeriveClock
|
|
Data Path Delay: 0.429ns (logic 0.137ns, net 0.292ns, 31% logic)
|
|
Logic Levels: 0
|
|
|
|
Point Type Incr Path Info
|
|
---------------------------------------------------------------------------------------------------------
|
|
RAMDATA_Interface/reg0_b4|RAMDATA_Interface/reg0_b10.clk clock 0.000 0.000
|
|
launch clock edge 0.000 0.000
|
|
RAMDATA_Interface/reg0_b4|RAMDATA_Interface/reg0_b10.q[0] clk2q 0.137 r 0.137
|
|
RAM_DATA/ram_mem_unify_al_u30_4096x8_sub_000000_000.addra[11] (RAMDATA_WADDR[10]) net (fanout = 16) 0.292 r 0.429 ../rtl/topmodule/CortexM0_SoC.v(443)
|
|
RAM_DATA/ram_mem_unify_al_u30_4096x8_sub_000000_000 (EMB) 0.000 0.429
|
|
Arrival time 0.429 (0 lvl)
|
|
|
|
RAM_DATA/ram_mem_unify_al_u30_4096x8_sub_000000_000.clka 0.000 0.000
|
|
capture clock edge 0.000 0.000
|
|
cell hold 0.200 0.200
|
|
clock uncertainty 0.000 0.200
|
|
clock recovergence pessimism 0.000 0.200
|
|
Required time 0.200
|
|
---------------------------------------------------------------------------------------------------------
|
|
Slack 0.229ns
|
|
|
|
---------------------------------------------------------------------------------------------------------
|
|
|
|
Slack (hold check): 0.229 ns
|
|
Start Point: RAMDATA_Interface/reg0_b5|RAMDATA_Interface/reg0_b2.clk (rising edge triggered by clock DeriveClock)
|
|
End Point: RAM_DATA/ram_mem_unify_al_u30_4096x8_sub_000000_000.addra[6] (rising edge triggered by clock DeriveClock)
|
|
Clock group: DeriveClock
|
|
Data Path Delay: 0.429ns (logic 0.137ns, net 0.292ns, 31% logic)
|
|
Logic Levels: 0
|
|
|
|
Point Type Incr Path Info
|
|
---------------------------------------------------------------------------------------------------------
|
|
RAMDATA_Interface/reg0_b5|RAMDATA_Interface/reg0_b2.clk clock 0.000 0.000
|
|
launch clock edge 0.000 0.000
|
|
RAMDATA_Interface/reg0_b5|RAMDATA_Interface/reg0_b2.q[1] clk2q 0.137 r 0.137
|
|
RAM_DATA/ram_mem_unify_al_u30_4096x8_sub_000000_000.addra[6] (RAMDATA_WADDR[5]) net (fanout = 16) 0.292 r 0.429 ../rtl/topmodule/CortexM0_SoC.v(443)
|
|
RAM_DATA/ram_mem_unify_al_u30_4096x8_sub_000000_000 (EMB) 0.000 0.429
|
|
Arrival time 0.429 (0 lvl)
|
|
|
|
RAM_DATA/ram_mem_unify_al_u30_4096x8_sub_000000_000.clka 0.000 0.000
|
|
capture clock edge 0.000 0.000
|
|
cell hold 0.200 0.200
|
|
clock uncertainty 0.000 0.200
|
|
clock recovergence pessimism 0.000 0.200
|
|
Required time 0.200
|
|
---------------------------------------------------------------------------------------------------------
|
|
Slack 0.229ns
|
|
|
|
---------------------------------------------------------------------------------------------------------
|
|
|
|
Slack (hold check): 0.341 ns
|
|
Start Point: RAMDATA_Interface/reg0_b4|RAMDATA_Interface/reg0_b10.clk (rising edge triggered by clock DeriveClock)
|
|
End Point: RAM_DATA/ram_mem_unify_al_u30_4096x8_sub_000000_000.addra[5] (rising edge triggered by clock DeriveClock)
|
|
Clock group: DeriveClock
|
|
Data Path Delay: 0.541ns (logic 0.137ns, net 0.404ns, 25% logic)
|
|
Logic Levels: 0
|
|
|
|
Point Type Incr Path Info
|
|
---------------------------------------------------------------------------------------------------------
|
|
RAMDATA_Interface/reg0_b4|RAMDATA_Interface/reg0_b10.clk clock 0.000 0.000
|
|
launch clock edge 0.000 0.000
|
|
RAMDATA_Interface/reg0_b4|RAMDATA_Interface/reg0_b10.q[1] clk2q 0.137 r 0.137
|
|
RAM_DATA/ram_mem_unify_al_u30_4096x8_sub_000000_000.addra[5] (RAMDATA_WADDR[4]) net (fanout = 16) 0.404 r 0.541 ../rtl/topmodule/CortexM0_SoC.v(443)
|
|
RAM_DATA/ram_mem_unify_al_u30_4096x8_sub_000000_000 (EMB) 0.000 0.541
|
|
Arrival time 0.541 (0 lvl)
|
|
|
|
RAM_DATA/ram_mem_unify_al_u30_4096x8_sub_000000_000.clka 0.000 0.000
|
|
capture clock edge 0.000 0.000
|
|
cell hold 0.200 0.200
|
|
clock uncertainty 0.000 0.200
|
|
clock recovergence pessimism 0.000 0.200
|
|
Required time 0.200
|
|
---------------------------------------------------------------------------------------------------------
|
|
Slack 0.341ns
|
|
|
|
---------------------------------------------------------------------------------------------------------
|
|
|
|
Paths for end point RAM_DATA/ram_mem_unify_al_u30_4096x8_sub_000000_006 (12 paths)
|
|
---------------------------------------------------------------------------------------------------------
|
|
Slack (hold check): 0.271 ns
|
|
Start Point: RAMDATA_Interface/reg0_b11|RAMDATA_Interface/reg0_b8.clk (rising edge triggered by clock DeriveClock)
|
|
End Point: RAM_DATA/ram_mem_unify_al_u30_4096x8_sub_000000_006.addra[9] (rising edge triggered by clock DeriveClock)
|
|
Clock group: DeriveClock
|
|
Data Path Delay: 0.471ns (logic 0.137ns, net 0.334ns, 29% logic)
|
|
Logic Levels: 0
|
|
|
|
Point Type Incr Path Info
|
|
---------------------------------------------------------------------------------------------------------
|
|
RAMDATA_Interface/reg0_b11|RAMDATA_Interface/reg0_b8.clk clock 0.000 0.000
|
|
launch clock edge 0.000 0.000
|
|
RAMDATA_Interface/reg0_b11|RAMDATA_Interface/reg0_b8.q[0] clk2q 0.137 r 0.137
|
|
RAM_DATA/ram_mem_unify_al_u30_4096x8_sub_000000_006.addra[9] (RAMDATA_WADDR[8]) net (fanout = 16) 0.334 r 0.471 ../rtl/topmodule/CortexM0_SoC.v(443)
|
|
RAM_DATA/ram_mem_unify_al_u30_4096x8_sub_000000_006 (EMB) 0.000 0.471
|
|
Arrival time 0.471 (0 lvl)
|
|
|
|
RAM_DATA/ram_mem_unify_al_u30_4096x8_sub_000000_006.clka 0.000 0.000
|
|
capture clock edge 0.000 0.000
|
|
cell hold 0.200 0.200
|
|
clock uncertainty 0.000 0.200
|
|
clock recovergence pessimism 0.000 0.200
|
|
Required time 0.200
|
|
---------------------------------------------------------------------------------------------------------
|
|
Slack 0.271ns
|
|
|
|
---------------------------------------------------------------------------------------------------------
|
|
|
|
Slack (hold check): 0.375 ns
|
|
Start Point: RAMDATA_Interface/reg0_b5|RAMDATA_Interface/reg0_b2.clk (rising edge triggered by clock DeriveClock)
|
|
End Point: RAM_DATA/ram_mem_unify_al_u30_4096x8_sub_000000_006.addra[6] (rising edge triggered by clock DeriveClock)
|
|
Clock group: DeriveClock
|
|
Data Path Delay: 0.575ns (logic 0.137ns, net 0.438ns, 23% logic)
|
|
Logic Levels: 0
|
|
|
|
Point Type Incr Path Info
|
|
---------------------------------------------------------------------------------------------------------
|
|
RAMDATA_Interface/reg0_b5|RAMDATA_Interface/reg0_b2.clk clock 0.000 0.000
|
|
launch clock edge 0.000 0.000
|
|
RAMDATA_Interface/reg0_b5|RAMDATA_Interface/reg0_b2.q[1] clk2q 0.137 r 0.137
|
|
RAM_DATA/ram_mem_unify_al_u30_4096x8_sub_000000_006.addra[6] (RAMDATA_WADDR[5]) net (fanout = 16) 0.438 r 0.575 ../rtl/topmodule/CortexM0_SoC.v(443)
|
|
RAM_DATA/ram_mem_unify_al_u30_4096x8_sub_000000_006 (EMB) 0.000 0.575
|
|
Arrival time 0.575 (0 lvl)
|
|
|
|
RAM_DATA/ram_mem_unify_al_u30_4096x8_sub_000000_006.clka 0.000 0.000
|
|
capture clock edge 0.000 0.000
|
|
cell hold 0.200 0.200
|
|
clock uncertainty 0.000 0.200
|
|
clock recovergence pessimism 0.000 0.200
|
|
Required time 0.200
|
|
---------------------------------------------------------------------------------------------------------
|
|
Slack 0.375ns
|
|
|
|
---------------------------------------------------------------------------------------------------------
|
|
|
|
Slack (hold check): 0.411 ns
|
|
Start Point: RAMDATA_Interface/reg0_b6|RAMDATA_Interface/reg0_b7.clk (rising edge triggered by clock DeriveClock)
|
|
End Point: RAM_DATA/ram_mem_unify_al_u30_4096x8_sub_000000_006.addra[8] (rising edge triggered by clock DeriveClock)
|
|
Clock group: DeriveClock
|
|
Data Path Delay: 0.611ns (logic 0.137ns, net 0.474ns, 22% logic)
|
|
Logic Levels: 0
|
|
|
|
Point Type Incr Path Info
|
|
---------------------------------------------------------------------------------------------------------
|
|
RAMDATA_Interface/reg0_b6|RAMDATA_Interface/reg0_b7.clk clock 0.000 0.000
|
|
launch clock edge 0.000 0.000
|
|
RAMDATA_Interface/reg0_b6|RAMDATA_Interface/reg0_b7.q[0] clk2q 0.137 r 0.137
|
|
RAM_DATA/ram_mem_unify_al_u30_4096x8_sub_000000_006.addra[8] (RAMDATA_WADDR[7]) net (fanout = 16) 0.474 r 0.611 ../rtl/topmodule/CortexM0_SoC.v(443)
|
|
RAM_DATA/ram_mem_unify_al_u30_4096x8_sub_000000_006 (EMB) 0.000 0.611
|
|
Arrival time 0.611 (0 lvl)
|
|
|
|
RAM_DATA/ram_mem_unify_al_u30_4096x8_sub_000000_006.clka 0.000 0.000
|
|
capture clock edge 0.000 0.000
|
|
cell hold 0.200 0.200
|
|
clock uncertainty 0.000 0.200
|
|
clock recovergence pessimism 0.000 0.200
|
|
Required time 0.200
|
|
---------------------------------------------------------------------------------------------------------
|
|
Slack 0.411ns
|
|
|
|
---------------------------------------------------------------------------------------------------------
|
|
|
|
Paths for end point RAM_CODE/ram_mem_unify_al_u20_4096x8_sub_000000_000 (12 paths)
|
|
---------------------------------------------------------------------------------------------------------
|
|
Slack (hold check): 0.280 ns
|
|
Start Point: u_logic/_al_u1539|RAMCODE_Interface/reg0_b5.clk (rising edge triggered by clock DeriveClock)
|
|
End Point: RAM_CODE/ram_mem_unify_al_u20_4096x8_sub_000000_000.addra[6] (rising edge triggered by clock DeriveClock)
|
|
Clock group: DeriveClock
|
|
Data Path Delay: 0.480ns (logic 0.137ns, net 0.343ns, 28% logic)
|
|
Logic Levels: 0
|
|
|
|
Point Type Incr Path Info
|
|
---------------------------------------------------------------------------------------------------------
|
|
u_logic/_al_u1539|RAMCODE_Interface/reg0_b5.clk clock 0.000 0.000
|
|
launch clock edge 0.000 0.000
|
|
u_logic/_al_u1539|RAMCODE_Interface/reg0_b5.q[0] clk2q 0.137 r 0.137
|
|
RAM_CODE/ram_mem_unify_al_u20_4096x8_sub_000000_000.addra[6] (RAMCODE_WADDR[5]) net (fanout = 16) 0.343 r 0.480 ../rtl/topmodule/CortexM0_SoC.v(383)
|
|
RAM_CODE/ram_mem_unify_al_u20_4096x8_sub_000000_000 (EMB) 0.000 0.480
|
|
Arrival time 0.480 (0 lvl)
|
|
|
|
RAM_CODE/ram_mem_unify_al_u20_4096x8_sub_000000_000.clka 0.000 0.000
|
|
capture clock edge 0.000 0.000
|
|
cell hold 0.200 0.200
|
|
clock uncertainty 0.000 0.200
|
|
clock recovergence pessimism 0.000 0.200
|
|
Required time 0.200
|
|
---------------------------------------------------------------------------------------------------------
|
|
Slack 0.280ns
|
|
|
|
---------------------------------------------------------------------------------------------------------
|
|
|
|
Slack (hold check): 0.439 ns
|
|
Start Point: RAMCODE_Interface/reg0_b7|RAMCODE_Interface/reg0_b3.clk (rising edge triggered by clock DeriveClock)
|
|
End Point: RAM_CODE/ram_mem_unify_al_u20_4096x8_sub_000000_000.addra[8] (rising edge triggered by clock DeriveClock)
|
|
Clock group: DeriveClock
|
|
Data Path Delay: 0.639ns (logic 0.137ns, net 0.502ns, 21% logic)
|
|
Logic Levels: 0
|
|
|
|
Point Type Incr Path Info
|
|
---------------------------------------------------------------------------------------------------------
|
|
RAMCODE_Interface/reg0_b7|RAMCODE_Interface/reg0_b3.clk clock 0.000 0.000
|
|
launch clock edge 0.000 0.000
|
|
RAMCODE_Interface/reg0_b7|RAMCODE_Interface/reg0_b3.q[1] clk2q 0.137 r 0.137
|
|
RAM_CODE/ram_mem_unify_al_u20_4096x8_sub_000000_000.addra[8] (RAMCODE_WADDR[7]) net (fanout = 16) 0.502 r 0.639 ../rtl/topmodule/CortexM0_SoC.v(383)
|
|
RAM_CODE/ram_mem_unify_al_u20_4096x8_sub_000000_000 (EMB) 0.000 0.639
|
|
Arrival time 0.639 (0 lvl)
|
|
|
|
RAM_CODE/ram_mem_unify_al_u20_4096x8_sub_000000_000.clka 0.000 0.000
|
|
capture clock edge 0.000 0.000
|
|
cell hold 0.200 0.200
|
|
clock uncertainty 0.000 0.200
|
|
clock recovergence pessimism 0.000 0.200
|
|
Required time 0.200
|
|
---------------------------------------------------------------------------------------------------------
|
|
Slack 0.439ns
|
|
|
|
---------------------------------------------------------------------------------------------------------
|
|
|
|
Slack (hold check): 0.448 ns
|
|
Start Point: RAMCODE_Interface/reg0_b0|RAMCODE_Interface/reg0_b1.clk (rising edge triggered by clock DeriveClock)
|
|
End Point: RAM_CODE/ram_mem_unify_al_u20_4096x8_sub_000000_000.addra[2] (rising edge triggered by clock DeriveClock)
|
|
Clock group: DeriveClock
|
|
Data Path Delay: 0.648ns (logic 0.137ns, net 0.511ns, 21% logic)
|
|
Logic Levels: 0
|
|
|
|
Point Type Incr Path Info
|
|
---------------------------------------------------------------------------------------------------------
|
|
RAMCODE_Interface/reg0_b0|RAMCODE_Interface/reg0_b1.clk clock 0.000 0.000
|
|
launch clock edge 0.000 0.000
|
|
RAMCODE_Interface/reg0_b0|RAMCODE_Interface/reg0_b1.q[0] clk2q 0.137 r 0.137
|
|
RAM_CODE/ram_mem_unify_al_u20_4096x8_sub_000000_000.addra[2] (RAMCODE_WADDR[1]) net (fanout = 16) 0.511 r 0.648 ../rtl/topmodule/CortexM0_SoC.v(383)
|
|
RAM_CODE/ram_mem_unify_al_u20_4096x8_sub_000000_000 (EMB) 0.000 0.648
|
|
Arrival time 0.648 (0 lvl)
|
|
|
|
RAM_CODE/ram_mem_unify_al_u20_4096x8_sub_000000_000.clka 0.000 0.000
|
|
capture clock edge 0.000 0.000
|
|
cell hold 0.200 0.200
|
|
clock uncertainty 0.000 0.200
|
|
clock recovergence pessimism 0.000 0.200
|
|
Required time 0.200
|
|
---------------------------------------------------------------------------------------------------------
|
|
Slack 0.448ns
|
|
|
|
---------------------------------------------------------------------------------------------------------
|
|
|
|
Recovery checks:
|
|
---------------------------------------------------------------------------------------------------------
|
|
Paths for end point u_logic/Qf4bx6_reg|u_logic/Sh4bx6_reg (1 paths)
|
|
---------------------------------------------------------------------------------------------------------
|
|
Slack (recovery check): 16.555 ns
|
|
Start Point: u_logic/_al_u4349|cpuresetn_reg.clk (rising edge triggered by clock DeriveClock)
|
|
End Point: u_logic/Qf4bx6_reg|u_logic/Sh4bx6_reg.sr (rising edge triggered by clock DeriveClock)
|
|
Clock group: DeriveClock
|
|
Data Path Delay: 3.145ns (logic 0.289ns, net 2.856ns, 9% logic)
|
|
Logic Levels: 0
|
|
|
|
Point Type Incr Path Info
|
|
---------------------------------------------------------------------------------------------------------
|
|
u_logic/_al_u4349|cpuresetn_reg.clk clock 0.000 0.000
|
|
launch clock edge 0.000 0.000
|
|
u_logic/_al_u4349|cpuresetn_reg.q[0] clk2q 0.146 r 0.146
|
|
u_logic/Qf4bx6_reg|u_logic/Sh4bx6_reg.sr (cpuresetn) net (fanout = 301) 2.856 r 3.002 ../rtl/topmodule/CortexM0_SoC.v(95)
|
|
u_logic/Qf4bx6_reg|u_logic/Sh4bx6_reg path2reg 0.143 3.145
|
|
Arrival time 3.145 (0 lvl)
|
|
|
|
u_logic/Qf4bx6_reg|u_logic/Sh4bx6_reg.clk 0.000 0.000
|
|
capture clock edge 20.000 20.000
|
|
cell recovery -0.300 19.700
|
|
clock uncertainty -0.000 19.700
|
|
clock recovergence pessimism 0.000 19.700
|
|
Required time 19.700
|
|
---------------------------------------------------------------------------------------------------------
|
|
Slack 16.555ns
|
|
|
|
---------------------------------------------------------------------------------------------------------
|
|
|
|
Paths for end point SPI_TX/reg0_b7|SPI_TX/reg0_b3 (1 paths)
|
|
---------------------------------------------------------------------------------------------------------
|
|
Slack (recovery check): 16.877 ns
|
|
Start Point: u_logic/_al_u4349|cpuresetn_reg.clk (rising edge triggered by clock DeriveClock)
|
|
End Point: SPI_TX/reg0_b7|SPI_TX/reg0_b3.sr (rising edge triggered by clock DeriveClock)
|
|
Clock group: DeriveClock
|
|
Data Path Delay: 2.823ns (logic 0.289ns, net 2.534ns, 10% logic)
|
|
Logic Levels: 0
|
|
|
|
Point Type Incr Path Info
|
|
---------------------------------------------------------------------------------------------------------
|
|
u_logic/_al_u4349|cpuresetn_reg.clk clock 0.000 0.000
|
|
launch clock edge 0.000 0.000
|
|
u_logic/_al_u4349|cpuresetn_reg.q[0] clk2q 0.146 r 0.146
|
|
SPI_TX/reg0_b7|SPI_TX/reg0_b3.sr (cpuresetn) net (fanout = 301) 2.534 r 2.680 ../rtl/topmodule/CortexM0_SoC.v(95)
|
|
SPI_TX/reg0_b7|SPI_TX/reg0_b3 path2reg 0.143 2.823
|
|
Arrival time 2.823 (0 lvl)
|
|
|
|
SPI_TX/reg0_b7|SPI_TX/reg0_b3.clk 0.000 0.000
|
|
capture clock edge 20.000 20.000
|
|
cell recovery -0.300 19.700
|
|
clock uncertainty -0.000 19.700
|
|
clock recovergence pessimism 0.000 19.700
|
|
Required time 19.700
|
|
---------------------------------------------------------------------------------------------------------
|
|
Slack 16.877ns
|
|
|
|
---------------------------------------------------------------------------------------------------------
|
|
|
|
Paths for end point SPI_TX/reg0_b11|SPI_TX/reg0_b12 (1 paths)
|
|
---------------------------------------------------------------------------------------------------------
|
|
Slack (recovery check): 16.877 ns
|
|
Start Point: u_logic/_al_u4349|cpuresetn_reg.clk (rising edge triggered by clock DeriveClock)
|
|
End Point: SPI_TX/reg0_b11|SPI_TX/reg0_b12.sr (rising edge triggered by clock DeriveClock)
|
|
Clock group: DeriveClock
|
|
Data Path Delay: 2.823ns (logic 0.289ns, net 2.534ns, 10% logic)
|
|
Logic Levels: 0
|
|
|
|
Point Type Incr Path Info
|
|
---------------------------------------------------------------------------------------------------------
|
|
u_logic/_al_u4349|cpuresetn_reg.clk clock 0.000 0.000
|
|
launch clock edge 0.000 0.000
|
|
u_logic/_al_u4349|cpuresetn_reg.q[0] clk2q 0.146 r 0.146
|
|
SPI_TX/reg0_b11|SPI_TX/reg0_b12.sr (cpuresetn) net (fanout = 301) 2.534 r 2.680 ../rtl/topmodule/CortexM0_SoC.v(95)
|
|
SPI_TX/reg0_b11|SPI_TX/reg0_b12 path2reg 0.143 2.823
|
|
Arrival time 2.823 (0 lvl)
|
|
|
|
SPI_TX/reg0_b11|SPI_TX/reg0_b12.clk 0.000 0.000
|
|
capture clock edge 20.000 20.000
|
|
cell recovery -0.300 19.700
|
|
clock uncertainty -0.000 19.700
|
|
clock recovergence pessimism 0.000 19.700
|
|
Required time 19.700
|
|
---------------------------------------------------------------------------------------------------------
|
|
Slack 16.877ns
|
|
|
|
---------------------------------------------------------------------------------------------------------
|
|
|
|
Removal checks:
|
|
---------------------------------------------------------------------------------------------------------
|
|
Paths for end point u_logic/_al_u134|u_logic/Dqkbx6_reg (1 paths)
|
|
---------------------------------------------------------------------------------------------------------
|
|
Slack (removal check): 0.281 ns
|
|
Start Point: u_logic/Hwhpw6_reg|u_logic/Kxhpw6_reg.clk (rising edge triggered by clock DeriveClock)
|
|
End Point: u_logic/_al_u134|u_logic/Dqkbx6_reg.sr (rising edge triggered by clock DeriveClock)
|
|
Clock group: DeriveClock
|
|
Data Path Delay: 0.581ns (logic 0.246ns, net 0.335ns, 42% logic)
|
|
Logic Levels: 0
|
|
|
|
Point Type Incr Path Info
|
|
---------------------------------------------------------------------------------------------------------
|
|
u_logic/Hwhpw6_reg|u_logic/Kxhpw6_reg.clk clock 0.000 0.000
|
|
launch clock edge 0.000 0.000
|
|
u_logic/Hwhpw6_reg|u_logic/Kxhpw6_reg.q[0] clk2q 0.137 r 0.137
|
|
u_logic/_al_u134|u_logic/Dqkbx6_reg.sr (u_logic/Kxhpw6) net (fanout = 25) 0.335 r 0.472 ../rtl/topmodule/cortexm0ds_logic.v(1584)
|
|
u_logic/_al_u134|u_logic/Dqkbx6_reg path2reg 0.109 0.581
|
|
Arrival time 0.581 (0 lvl)
|
|
|
|
u_logic/_al_u134|u_logic/Dqkbx6_reg.clk 0.000 0.000
|
|
capture clock edge 0.000 0.000
|
|
cell removal 0.300 0.300
|
|
clock uncertainty 0.000 0.300
|
|
clock recovergence pessimism 0.000 0.300
|
|
Required time 0.300
|
|
---------------------------------------------------------------------------------------------------------
|
|
Slack 0.281ns
|
|
|
|
---------------------------------------------------------------------------------------------------------
|
|
|
|
Paths for end point u_logic/_al_u1045|u_logic/T82qw6_reg (1 paths)
|
|
---------------------------------------------------------------------------------------------------------
|
|
Slack (removal check): 0.281 ns
|
|
Start Point: u_logic/Hwhpw6_reg|u_logic/Kxhpw6_reg.clk (rising edge triggered by clock DeriveClock)
|
|
End Point: u_logic/_al_u1045|u_logic/T82qw6_reg.sr (rising edge triggered by clock DeriveClock)
|
|
Clock group: DeriveClock
|
|
Data Path Delay: 0.581ns (logic 0.246ns, net 0.335ns, 42% logic)
|
|
Logic Levels: 0
|
|
|
|
Point Type Incr Path Info
|
|
---------------------------------------------------------------------------------------------------------
|
|
u_logic/Hwhpw6_reg|u_logic/Kxhpw6_reg.clk clock 0.000 0.000
|
|
launch clock edge 0.000 0.000
|
|
u_logic/Hwhpw6_reg|u_logic/Kxhpw6_reg.q[0] clk2q 0.137 r 0.137
|
|
u_logic/_al_u1045|u_logic/T82qw6_reg.sr (u_logic/Kxhpw6) net (fanout = 25) 0.335 r 0.472 ../rtl/topmodule/cortexm0ds_logic.v(1584)
|
|
u_logic/_al_u1045|u_logic/T82qw6_reg path2reg 0.109 0.581
|
|
Arrival time 0.581 (0 lvl)
|
|
|
|
u_logic/_al_u1045|u_logic/T82qw6_reg.clk 0.000 0.000
|
|
capture clock edge 0.000 0.000
|
|
cell removal 0.300 0.300
|
|
clock uncertainty 0.000 0.300
|
|
clock recovergence pessimism 0.000 0.300
|
|
Required time 0.300
|
|
---------------------------------------------------------------------------------------------------------
|
|
Slack 0.281ns
|
|
|
|
---------------------------------------------------------------------------------------------------------
|
|
|
|
Paths for end point u_logic/_al_u1021|u_logic/Hpcbx6_reg (1 paths)
|
|
---------------------------------------------------------------------------------------------------------
|
|
Slack (removal check): 0.281 ns
|
|
Start Point: u_logic/Hwhpw6_reg|u_logic/Kxhpw6_reg.clk (rising edge triggered by clock DeriveClock)
|
|
End Point: u_logic/_al_u1021|u_logic/Hpcbx6_reg.sr (rising edge triggered by clock DeriveClock)
|
|
Clock group: DeriveClock
|
|
Data Path Delay: 0.581ns (logic 0.246ns, net 0.335ns, 42% logic)
|
|
Logic Levels: 0
|
|
|
|
Point Type Incr Path Info
|
|
---------------------------------------------------------------------------------------------------------
|
|
u_logic/Hwhpw6_reg|u_logic/Kxhpw6_reg.clk clock 0.000 0.000
|
|
launch clock edge 0.000 0.000
|
|
u_logic/Hwhpw6_reg|u_logic/Kxhpw6_reg.q[0] clk2q 0.137 r 0.137
|
|
u_logic/_al_u1021|u_logic/Hpcbx6_reg.sr (u_logic/Kxhpw6) net (fanout = 25) 0.335 r 0.472 ../rtl/topmodule/cortexm0ds_logic.v(1584)
|
|
u_logic/_al_u1021|u_logic/Hpcbx6_reg path2reg 0.109 0.581
|
|
Arrival time 0.581 (0 lvl)
|
|
|
|
u_logic/_al_u1021|u_logic/Hpcbx6_reg.clk 0.000 0.000
|
|
capture clock edge 0.000 0.000
|
|
cell removal 0.300 0.300
|
|
clock uncertainty 0.000 0.300
|
|
clock recovergence pessimism 0.000 0.300
|
|
Required time 0.300
|
|
---------------------------------------------------------------------------------------------------------
|
|
Slack 0.281ns
|
|
|
|
---------------------------------------------------------------------------------------------------------
|
|
|
|
Period checks:
|
|
---------------------------------------------------------------------------------------------------------
|
|
Point Type Setting(ns) Requied(ns) Slack(ns)
|
|
---------------------------------------------------------------------------------------------------------
|
|
ethernet_i0/mac_test0/mac_top0/mac_tx0/udp0/tx_data_fifo/fifo_inst_3_.clkw min period 20.000 3.300 16.700
|
|
ethernet_i0/mac_test0/mac_top0/mac_tx0/udp0/tx_data_fifo/fifo_inst_2_.clkw min period 20.000 3.300 16.700
|
|
ethernet_i0/mac_test0/mac_top0/mac_tx0/udp0/tx_data_fifo/fifo_inst_1_.clkw min period 20.000 3.300 16.700
|
|
ethernet_i0/mac_test0/mac_top0/mac_tx0/udp0/tx_data_fifo/fifo_inst_0_.clkw min period 20.000 3.300 16.700
|
|
|
|
=========================================================================================================
|
|
Timing summary:
|
|
---------------------------------------------------------------------------------------------------------
|
|
Constraint path number: more than 1,000,000,000 (STA coverage = 92.34%)
|
|
Timing violations: 9 setup errors, and 0 hold errors.
|
|
Minimal setup slack: -9.076, minimal hold slack: 0.229
|
|
|
|
Timing group statistics:
|
|
Clock constraints:
|
|
Clock Name Min Period Max Freq Skew Fanout TNS
|
|
DeriveClock (50.0MHz) 29.076ns 34MHz 0.000ns 6999 -697.928ns
|
|
Minimum input arrival time before clock: no constraint path
|
|
Maximum output required time after clock: no constraint path
|
|
Maximum combinational path delay: no constraint path
|
|
|
|
|
|
Warning: No clock constraint on 16 clock net(s):
|
|
CW_CLK_MSI
|
|
FM_HW/ADC_CLK
|
|
FM_HW/CW_CLK
|
|
FM_HW/EOC
|
|
FM_HW/FM_Demodulation/EOC_Count_Demodulate
|
|
FM_HW/FM_Demodulation/I2S_BCLK_pad
|
|
FM_HW/FM_RSSI_SCAN/EOC_Count_Demodulate
|
|
FM_HW/clk_PWM_160
|
|
FM_HW/clk_PWM_256
|
|
FM_HW/clk_fm_demo_sampling
|
|
MSI_REFCLK_pad
|
|
clk_fm_ethernet
|
|
clk_pad
|
|
ethernet_i0/gmii_rx_clk
|
|
scan_unit/scan_clk
|
|
u_logic/SWCLKTCK_pad
|
|
|
|
---------------------------------------------------------------------------------------------------------
|