mirror of
https://github.com/JefferyLi0903/MMC.git
synced 2025-02-06 10:28:22 +08:00
402 lines
17 KiB
Plaintext
402 lines
17 KiB
Plaintext
eagle_s20
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12 22 597 34090 1000000000 9 0
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-9.076 0.229 CortexM0_SoC eagle_s20 BG256 Detail 8 1
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clock: DeriveClock
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12 1000000000 34090 5
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Setup check
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22 3
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Endpoint: u_logic/Vgjpw6_reg
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22 -9.076000 13863737 3
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Timing path: u_logic/M6kax6_reg.clk->u_logic/Vgjpw6_reg
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u_logic/M6kax6_reg.clk
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u_logic/Vgjpw6_reg
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24 -9.076000 19.884000 28.960000 19 19
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u_logic/M6kax6 u_logic/_al_u182|u_logic/_al_u192.b[1]
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u_logic/Wanow6_lutinv u_logic/_al_u239|u_logic/Ljwax6_reg.a[1]
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u_logic/_al_u239_o u_logic/_al_u219|u_logic/Llwax6_reg.c[0]
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u_logic/S90iu6 u_logic/_al_u242|u_logic/_al_u272.d[1]
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u_logic/Mifpw6[18] u_logic/mult0_1_0_.a[0]
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u_logic/mult0_1_0_0 u_logic/u1/u0|u1/ucin.a[1]
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u_logic/n135[0] u_logic/u2/u0|u2/ucin.b[1]
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u_logic/u2/c1 u_logic/u2/u2|u2/u1.fci
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u_logic/n159[1] u_logic/_al_u3820|u_logic/_al_u3738.d[0]
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u_logic/_al_u3738_o u_logic/_al_u3739|u_logic/_al_u3824.b[1]
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u_logic/_al_u3739_o u_logic/_al_u3740.c[1]
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u_logic/Y4miu6 u_logic/_al_u3741|u_logic/W7max6_reg.c[1]
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u_logic/_al_u3741_o u_logic/_al_u3746|u_logic/Wdmax6_reg.b[1]
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u_logic/_al_u3746_o u_logic/_al_u3773|u_logic/_al_u3816.a[1]
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u_logic/_al_u3773_o u_logic/_al_u3866|u_logic/_al_u3823.a[1]
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u_logic/_al_u3866_o u_logic/_al_u3681|u_logic/_al_u3941.b[0]
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u_logic/_al_u3941_o u_logic/_al_u3942.a[1]
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u_logic/_al_u3942_o u_logic/_al_u4026.a[1]
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u_logic/_al_u4026_o u_logic/Vgjpw6_reg.a[1]
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Timing path: u_logic/M6kax6_reg.clk->u_logic/Vgjpw6_reg
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u_logic/M6kax6_reg.clk
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u_logic/Vgjpw6_reg
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87 -9.076000 19.884000 28.960000 19 19
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u_logic/M6kax6 u_logic/_al_u182|u_logic/_al_u192.b[1]
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u_logic/Wanow6_lutinv u_logic/_al_u239|u_logic/Ljwax6_reg.a[1]
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u_logic/_al_u239_o u_logic/_al_u219|u_logic/Llwax6_reg.c[0]
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u_logic/S90iu6 u_logic/_al_u242|u_logic/_al_u272.d[1]
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u_logic/Mifpw6[18] u_logic/mult0_1_0_.a[0]
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u_logic/mult0_1_0_0 u_logic/u1/u0|u1/ucin.a[1]
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u_logic/n135[0] u_logic/u2/u0|u2/ucin.b[1]
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u_logic/u2/c1 u_logic/u2/u2|u2/u1.fci
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u_logic/n159[1] u_logic/_al_u3820|u_logic/_al_u3738.d[0]
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u_logic/_al_u3738_o u_logic/_al_u3739|u_logic/_al_u3824.b[1]
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u_logic/_al_u3739_o u_logic/_al_u3740.c[1]
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u_logic/Y4miu6 u_logic/_al_u3741|u_logic/W7max6_reg.c[1]
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u_logic/_al_u3741_o u_logic/_al_u3746|u_logic/Wdmax6_reg.b[1]
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u_logic/_al_u3746_o u_logic/_al_u3773|u_logic/_al_u3816.a[1]
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u_logic/_al_u3773_o u_logic/_al_u3866|u_logic/_al_u3823.a[1]
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u_logic/_al_u3866_o u_logic/_al_u3681|u_logic/_al_u3941.b[0]
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u_logic/_al_u3941_o u_logic/_al_u3942.a[1]
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u_logic/_al_u3942_o u_logic/_al_u4026.a[0]
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u_logic/_al_u4026_o u_logic/Vgjpw6_reg.a[1]
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Timing path: u_logic/M6kax6_reg.clk->u_logic/Vgjpw6_reg
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u_logic/M6kax6_reg.clk
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u_logic/Vgjpw6_reg
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150 -9.076000 19.884000 28.960000 19 19
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u_logic/M6kax6 u_logic/_al_u182|u_logic/_al_u192.b[1]
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u_logic/Wanow6_lutinv u_logic/_al_u239|u_logic/Ljwax6_reg.a[1]
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u_logic/_al_u239_o u_logic/_al_u219|u_logic/Llwax6_reg.c[0]
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u_logic/S90iu6 u_logic/_al_u242|u_logic/_al_u272.d[1]
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u_logic/Mifpw6[18] u_logic/mult0_1_0_.a[0]
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u_logic/mult0_1_0_0 u_logic/u1/u0|u1/ucin.a[1]
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u_logic/n135[0] u_logic/u2/u0|u2/ucin.b[1]
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u_logic/u2/c1 u_logic/u2/u2|u2/u1.fci
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u_logic/n159[1] u_logic/_al_u3820|u_logic/_al_u3738.d[0]
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u_logic/_al_u3738_o u_logic/_al_u3739|u_logic/_al_u3824.b[1]
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u_logic/_al_u3739_o u_logic/_al_u3740.c[1]
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u_logic/Y4miu6 u_logic/_al_u3741|u_logic/W7max6_reg.c[1]
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u_logic/_al_u3741_o u_logic/_al_u3746|u_logic/Wdmax6_reg.b[1]
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u_logic/_al_u3746_o u_logic/_al_u3773|u_logic/_al_u3816.a[1]
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u_logic/_al_u3773_o u_logic/_al_u3866|u_logic/_al_u3823.a[1]
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u_logic/_al_u3866_o u_logic/_al_u3681|u_logic/_al_u3941.b[0]
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u_logic/_al_u3941_o u_logic/_al_u3942.a[1]
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u_logic/_al_u3942_o u_logic/_al_u4026.a[1]
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u_logic/_al_u4026_o u_logic/Vgjpw6_reg.a[0]
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Endpoint: u_logic/_al_u2303|u_logic/Ydopw6_reg
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213 -8.671000 3466379 3
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Timing path: u_logic/M6kax6_reg.clk->u_logic/_al_u2303|u_logic/Ydopw6_reg
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u_logic/M6kax6_reg.clk
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u_logic/_al_u2303|u_logic/Ydopw6_reg
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215 -8.671000 19.884000 28.555000 19 19
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u_logic/M6kax6 u_logic/_al_u182|u_logic/_al_u192.b[1]
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u_logic/Wanow6_lutinv u_logic/_al_u239|u_logic/Ljwax6_reg.a[1]
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u_logic/_al_u239_o u_logic/_al_u219|u_logic/Llwax6_reg.c[0]
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u_logic/S90iu6 u_logic/_al_u242|u_logic/_al_u272.d[1]
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u_logic/Mifpw6[18] u_logic/mult0_1_0_.a[0]
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u_logic/mult0_1_0_0 u_logic/u1/u0|u1/ucin.a[1]
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u_logic/n135[0] u_logic/u2/u0|u2/ucin.b[1]
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u_logic/u2/c1 u_logic/u2/u2|u2/u1.fci
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u_logic/n159[1] u_logic/_al_u3820|u_logic/_al_u3738.d[0]
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u_logic/_al_u3738_o u_logic/_al_u3739|u_logic/_al_u3824.b[1]
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u_logic/_al_u3739_o u_logic/_al_u3740.c[1]
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u_logic/Y4miu6 u_logic/_al_u3741|u_logic/W7max6_reg.c[1]
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u_logic/_al_u3741_o u_logic/_al_u3746|u_logic/Wdmax6_reg.b[1]
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u_logic/_al_u3746_o u_logic/_al_u3773|u_logic/_al_u3816.a[1]
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u_logic/_al_u3773_o u_logic/_al_u3866|u_logic/_al_u3823.a[1]
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u_logic/_al_u3866_o u_logic/_al_u3681|u_logic/_al_u3941.b[0]
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u_logic/_al_u3941_o u_logic/_al_u3942.a[1]
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u_logic/_al_u3942_o u_logic/_al_u3977|u_logic/_al_u1507.a[1]
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u_logic/_al_u3977_o u_logic/_al_u2303|u_logic/Ydopw6_reg.a[0]
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Timing path: u_logic/M6kax6_reg.clk->u_logic/_al_u2303|u_logic/Ydopw6_reg
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u_logic/M6kax6_reg.clk
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u_logic/_al_u2303|u_logic/Ydopw6_reg
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278 -8.671000 19.884000 28.555000 19 19
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u_logic/M6kax6 u_logic/_al_u182|u_logic/_al_u192.b[1]
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u_logic/Wanow6_lutinv u_logic/_al_u239|u_logic/Ljwax6_reg.a[1]
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u_logic/_al_u239_o u_logic/_al_u219|u_logic/Llwax6_reg.c[0]
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u_logic/S90iu6 u_logic/_al_u242|u_logic/_al_u272.d[1]
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u_logic/Mifpw6[18] u_logic/mult0_1_0_.a[0]
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u_logic/mult0_1_0_0 u_logic/u1/u0|u1/ucin.a[1]
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u_logic/n135[0] u_logic/u2/u0|u2/ucin.b[1]
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u_logic/u2/c1 u_logic/u2/u2|u2/u1.fci
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u_logic/n159[1] u_logic/_al_u3820|u_logic/_al_u3738.d[0]
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u_logic/_al_u3738_o u_logic/_al_u3739|u_logic/_al_u3824.b[1]
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u_logic/_al_u3739_o u_logic/_al_u3740.c[0]
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u_logic/Y4miu6 u_logic/_al_u3741|u_logic/W7max6_reg.c[1]
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u_logic/_al_u3741_o u_logic/_al_u3746|u_logic/Wdmax6_reg.b[1]
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u_logic/_al_u3746_o u_logic/_al_u3773|u_logic/_al_u3816.a[1]
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u_logic/_al_u3773_o u_logic/_al_u3866|u_logic/_al_u3823.a[1]
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u_logic/_al_u3866_o u_logic/_al_u3681|u_logic/_al_u3941.b[0]
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u_logic/_al_u3941_o u_logic/_al_u3942.a[1]
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u_logic/_al_u3942_o u_logic/_al_u3977|u_logic/_al_u1507.a[1]
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u_logic/_al_u3977_o u_logic/_al_u2303|u_logic/Ydopw6_reg.a[0]
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Timing path: u_logic/M6kax6_reg.clk->u_logic/_al_u2303|u_logic/Ydopw6_reg
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u_logic/M6kax6_reg.clk
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u_logic/_al_u2303|u_logic/Ydopw6_reg
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341 -8.671000 19.884000 28.555000 19 19
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u_logic/M6kax6 u_logic/_al_u182|u_logic/_al_u192.b[1]
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u_logic/Wanow6_lutinv u_logic/_al_u239|u_logic/Ljwax6_reg.a[1]
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u_logic/_al_u239_o u_logic/_al_u219|u_logic/Llwax6_reg.c[0]
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u_logic/S90iu6 u_logic/_al_u242|u_logic/_al_u272.d[1]
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u_logic/Mifpw6[18] u_logic/mult0_1_0_.a[0]
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u_logic/mult0_1_0_0 u_logic/u1/u0|u1/ucin.a[1]
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u_logic/n135[0] u_logic/u2/u0|u2/ucin.b[1]
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u_logic/u2/c1 u_logic/u2/u2|u2/u1.fci
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u_logic/n159[1] u_logic/_al_u3820|u_logic/_al_u3738.d[0]
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u_logic/_al_u3738_o u_logic/_al_u3739|u_logic/_al_u3824.b[1]
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u_logic/_al_u3739_o u_logic/_al_u3740.c[1]
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u_logic/Y4miu6 u_logic/_al_u3741|u_logic/W7max6_reg.c[1]
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u_logic/_al_u3741_o u_logic/_al_u3746|u_logic/Wdmax6_reg.b[1]
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u_logic/_al_u3746_o u_logic/_al_u3773|u_logic/_al_u3816.a[1]
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u_logic/_al_u3773_o u_logic/_al_u3866|u_logic/_al_u3823.a[1]
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u_logic/_al_u3866_o u_logic/_al_u3681|u_logic/_al_u3941.b[0]
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u_logic/_al_u3941_o u_logic/_al_u3942.a[0]
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u_logic/_al_u3942_o u_logic/_al_u3977|u_logic/_al_u1507.a[1]
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u_logic/_al_u3977_o u_logic/_al_u2303|u_logic/Ydopw6_reg.a[0]
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Endpoint: u_logic/Jvvpw6_reg
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404 -5.988000 2982027 3
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Timing path: u_logic/_al_u1478|u_logic/Htmpw6_reg.clk->u_logic/Jvvpw6_reg
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u_logic/_al_u1478|u_logic/Htmpw6_reg.clk
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u_logic/Jvvpw6_reg
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406 -5.988000 19.884000 25.872000 18 20
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u_logic/Htmpw6 u_logic/_al_u745|u_logic/_al_u1128.a[0]
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u_logic/Qiqow6 u_logic/_al_u1193|u_logic/Exypw6_reg.a[1]
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u_logic/_al_u1193_o u_logic/_al_u1405|u_logic/_al_u1194.a[0]
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u_logic/_al_u1194_o u_logic/T80qw6_reg|u_logic/Tk0qw6_reg.a[0]
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u_logic/_al_u1195_o u_logic/Odnax6_reg|u_logic/S1nax6_reg.a[0]
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u_logic/_al_u1197_o u_logic/_al_u1701|u_logic/_al_u1641.a[0]
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u_logic/Zu6ju6 u_logic/_al_u1643|u_logic/_al_u3843.d[1]
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u_logic/S2epw6 u_logic/add3_add4/u7_al_u4816.a[0]
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u_logic/add3_add4/c11 u_logic/add3_add4/u11_al_u4817.fci
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u_logic/add3_add4/c15 u_logic/add3_add4/u15_al_u4818.fci
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u_logic/add3_add4/c19 u_logic/add3_add4/u19_al_u4819.fci
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u_logic/Nxkbx6[23] u_logic/_al_u2504|u_logic/_al_u2496.d[1]
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u_logic/Me6pw6 u_logic/_al_u2484|u_logic/_al_u2505.d[0]
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u_logic/_al_u2505_o u_logic/N3hbx6_reg|u_logic/Tsdbx6_reg.a[1]
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u_logic/_al_u3543_o u_logic/_al_u3637|u_logic/Dk9bx6_reg.d[0]
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u_logic/_al_u3544_o u_logic/Gkeax6_reg|u_logic/Hpbbx6_reg.a[1]
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u_logic/_al_u3546_o u_logic/Dmeax6_reg|u_logic/Daebx6_reg.a[1]
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u_logic/_al_u3550_o u_logic/_al_u3186|u_logic/Tfcax6_reg.b[0]
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u_logic/_al_u3559_o u_logic/Tceax6_reg|u_logic/C1fax6_reg.a[1]
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u_logic/Dx7iu6 u_logic/Jvvpw6_reg.a[1]
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Timing path: u_logic/_al_u1478|u_logic/Htmpw6_reg.clk->u_logic/Jvvpw6_reg
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u_logic/_al_u1478|u_logic/Htmpw6_reg.clk
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u_logic/Jvvpw6_reg
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471 -5.988000 19.884000 25.872000 18 20
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u_logic/Htmpw6 u_logic/_al_u745|u_logic/_al_u1128.a[0]
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u_logic/Qiqow6 u_logic/_al_u1193|u_logic/Exypw6_reg.a[1]
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u_logic/_al_u1193_o u_logic/_al_u1405|u_logic/_al_u1194.a[0]
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u_logic/_al_u1194_o u_logic/T80qw6_reg|u_logic/Tk0qw6_reg.a[0]
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u_logic/_al_u1195_o u_logic/Odnax6_reg|u_logic/S1nax6_reg.a[0]
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u_logic/_al_u1197_o u_logic/_al_u1701|u_logic/_al_u1641.a[0]
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u_logic/Zu6ju6 u_logic/_al_u1643|u_logic/_al_u3843.d[1]
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u_logic/S2epw6 u_logic/add3_add4/u7_al_u4816.a[0]
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u_logic/add3_add4/c11 u_logic/add3_add4/u11_al_u4817.fci
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u_logic/add3_add4/c15 u_logic/add3_add4/u15_al_u4818.fci
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u_logic/add3_add4/c19 u_logic/add3_add4/u19_al_u4819.fci
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u_logic/Nxkbx6[23] u_logic/_al_u2504|u_logic/_al_u2496.d[1]
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u_logic/Me6pw6 u_logic/_al_u2484|u_logic/_al_u2505.d[0]
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u_logic/_al_u2505_o u_logic/N3hbx6_reg|u_logic/Tsdbx6_reg.a[1]
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u_logic/_al_u3543_o u_logic/_al_u3637|u_logic/Dk9bx6_reg.d[0]
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u_logic/_al_u3544_o u_logic/Gkeax6_reg|u_logic/Hpbbx6_reg.a[1]
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u_logic/_al_u3546_o u_logic/Dmeax6_reg|u_logic/Daebx6_reg.a[1]
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u_logic/_al_u3550_o u_logic/_al_u3186|u_logic/Tfcax6_reg.b[0]
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u_logic/_al_u3559_o u_logic/Tceax6_reg|u_logic/C1fax6_reg.a[1]
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u_logic/Dx7iu6 u_logic/Jvvpw6_reg.a[0]
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Timing path: u_logic/Hirpw6_reg.clk->u_logic/Jvvpw6_reg
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u_logic/Hirpw6_reg.clk
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u_logic/Jvvpw6_reg
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536 -5.967000 19.884000 25.851000 17 17
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u_logic/Hirpw6 u_logic/_al_u160|u_logic/_al_u664.c[0]
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u_logic/Frziu6_lutinv u_logic/_al_u665.b[1]
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u_logic/_al_u665_o u_logic/_al_u667|u_logic/_al_u910.a[1]
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u_logic/_al_u667_o u_logic/_al_u1474|u_logic/_al_u673.a[0]
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u_logic/_al_u673_o u_logic/_al_u783|u_logic/Eotax6_reg.b[1]
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u_logic/_al_u783_o u_logic/_al_u784|u_logic/_al_u791.d[1]
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u_logic/Idfpw6[17] u_logic/add3_add4/u15_al_u4818.d[1]
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u_logic/add3_add4/c19 u_logic/add3_add4/u19_al_u4819.fci
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u_logic/Nxkbx6[23] u_logic/_al_u2504|u_logic/_al_u2496.d[1]
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u_logic/Me6pw6 u_logic/_al_u2484|u_logic/_al_u2505.d[0]
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u_logic/_al_u2505_o u_logic/N3hbx6_reg|u_logic/Tsdbx6_reg.a[1]
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u_logic/_al_u3543_o u_logic/_al_u3637|u_logic/Dk9bx6_reg.d[0]
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u_logic/_al_u3544_o u_logic/Gkeax6_reg|u_logic/Hpbbx6_reg.a[1]
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u_logic/_al_u3546_o u_logic/Dmeax6_reg|u_logic/Daebx6_reg.a[1]
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u_logic/_al_u3550_o u_logic/_al_u3186|u_logic/Tfcax6_reg.b[0]
|
|
u_logic/_al_u3559_o u_logic/Tceax6_reg|u_logic/C1fax6_reg.a[1]
|
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u_logic/Dx7iu6 u_logic/Jvvpw6_reg.a[1]
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|
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|
|
Hold check
|
|
595 3
|
|
Endpoint: RAM_DATA/ram_mem_unify_al_u30_4096x8_sub_000000_000
|
|
597 0.229000 12 3
|
|
Timing path: RAMDATA_Interface/reg0_b4|RAMDATA_Interface/reg0_b10.clk->RAM_DATA/ram_mem_unify_al_u30_4096x8_sub_000000_000
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|
RAMDATA_Interface/reg0_b4|RAMDATA_Interface/reg0_b10.clk
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|
RAM_DATA/ram_mem_unify_al_u30_4096x8_sub_000000_000
|
|
599 0.229000 0.200000 0.429000 0 1
|
|
RAMDATA_WADDR[10] RAM_DATA/ram_mem_unify_al_u30_4096x8_sub_000000_000.addra[11]
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|
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Timing path: RAMDATA_Interface/reg0_b5|RAMDATA_Interface/reg0_b2.clk->RAM_DATA/ram_mem_unify_al_u30_4096x8_sub_000000_000
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RAMDATA_Interface/reg0_b5|RAMDATA_Interface/reg0_b2.clk
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RAM_DATA/ram_mem_unify_al_u30_4096x8_sub_000000_000
|
|
626 0.229000 0.200000 0.429000 0 1
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RAMDATA_WADDR[5] RAM_DATA/ram_mem_unify_al_u30_4096x8_sub_000000_000.addra[6]
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Timing path: RAMDATA_Interface/reg0_b4|RAMDATA_Interface/reg0_b10.clk->RAM_DATA/ram_mem_unify_al_u30_4096x8_sub_000000_000
|
|
RAMDATA_Interface/reg0_b4|RAMDATA_Interface/reg0_b10.clk
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|
RAM_DATA/ram_mem_unify_al_u30_4096x8_sub_000000_000
|
|
653 0.341000 0.200000 0.541000 0 1
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RAMDATA_WADDR[4] RAM_DATA/ram_mem_unify_al_u30_4096x8_sub_000000_000.addra[5]
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Endpoint: RAM_DATA/ram_mem_unify_al_u30_4096x8_sub_000000_006
|
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680 0.271000 12 3
|
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Timing path: RAMDATA_Interface/reg0_b11|RAMDATA_Interface/reg0_b8.clk->RAM_DATA/ram_mem_unify_al_u30_4096x8_sub_000000_006
|
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RAMDATA_Interface/reg0_b11|RAMDATA_Interface/reg0_b8.clk
|
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RAM_DATA/ram_mem_unify_al_u30_4096x8_sub_000000_006
|
|
682 0.271000 0.200000 0.471000 0 1
|
|
RAMDATA_WADDR[8] RAM_DATA/ram_mem_unify_al_u30_4096x8_sub_000000_006.addra[9]
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Timing path: RAMDATA_Interface/reg0_b5|RAMDATA_Interface/reg0_b2.clk->RAM_DATA/ram_mem_unify_al_u30_4096x8_sub_000000_006
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RAMDATA_Interface/reg0_b5|RAMDATA_Interface/reg0_b2.clk
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RAM_DATA/ram_mem_unify_al_u30_4096x8_sub_000000_006
|
|
709 0.375000 0.200000 0.575000 0 1
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|
RAMDATA_WADDR[5] RAM_DATA/ram_mem_unify_al_u30_4096x8_sub_000000_006.addra[6]
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Timing path: RAMDATA_Interface/reg0_b6|RAMDATA_Interface/reg0_b7.clk->RAM_DATA/ram_mem_unify_al_u30_4096x8_sub_000000_006
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RAMDATA_Interface/reg0_b6|RAMDATA_Interface/reg0_b7.clk
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RAM_DATA/ram_mem_unify_al_u30_4096x8_sub_000000_006
|
|
736 0.411000 0.200000 0.611000 0 1
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RAMDATA_WADDR[7] RAM_DATA/ram_mem_unify_al_u30_4096x8_sub_000000_006.addra[8]
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Endpoint: RAM_CODE/ram_mem_unify_al_u20_4096x8_sub_000000_000
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763 0.280000 12 3
|
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Timing path: u_logic/_al_u1539|RAMCODE_Interface/reg0_b5.clk->RAM_CODE/ram_mem_unify_al_u20_4096x8_sub_000000_000
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u_logic/_al_u1539|RAMCODE_Interface/reg0_b5.clk
|
|
RAM_CODE/ram_mem_unify_al_u20_4096x8_sub_000000_000
|
|
765 0.280000 0.200000 0.480000 0 1
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RAMCODE_WADDR[5] RAM_CODE/ram_mem_unify_al_u20_4096x8_sub_000000_000.addra[6]
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|
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Timing path: RAMCODE_Interface/reg0_b7|RAMCODE_Interface/reg0_b3.clk->RAM_CODE/ram_mem_unify_al_u20_4096x8_sub_000000_000
|
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RAMCODE_Interface/reg0_b7|RAMCODE_Interface/reg0_b3.clk
|
|
RAM_CODE/ram_mem_unify_al_u20_4096x8_sub_000000_000
|
|
792 0.439000 0.200000 0.639000 0 1
|
|
RAMCODE_WADDR[7] RAM_CODE/ram_mem_unify_al_u20_4096x8_sub_000000_000.addra[8]
|
|
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|
Timing path: RAMCODE_Interface/reg0_b0|RAMCODE_Interface/reg0_b1.clk->RAM_CODE/ram_mem_unify_al_u20_4096x8_sub_000000_000
|
|
RAMCODE_Interface/reg0_b0|RAMCODE_Interface/reg0_b1.clk
|
|
RAM_CODE/ram_mem_unify_al_u20_4096x8_sub_000000_000
|
|
819 0.448000 0.200000 0.648000 0 1
|
|
RAMCODE_WADDR[1] RAM_CODE/ram_mem_unify_al_u20_4096x8_sub_000000_000.addra[2]
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|
|
|
|
|
|
|
Recovery check
|
|
846 3
|
|
Endpoint: u_logic/Qf4bx6_reg|u_logic/Sh4bx6_reg
|
|
848 16.555000 1 1
|
|
Timing path: u_logic/_al_u4349|cpuresetn_reg.clk->u_logic/Qf4bx6_reg|u_logic/Sh4bx6_reg
|
|
u_logic/_al_u4349|cpuresetn_reg.clk
|
|
u_logic/Qf4bx6_reg|u_logic/Sh4bx6_reg
|
|
850 16.555000 19.700000 3.145000 0 1
|
|
cpuresetn u_logic/Qf4bx6_reg|u_logic/Sh4bx6_reg.sr
|
|
|
|
|
|
Endpoint: SPI_TX/reg0_b7|SPI_TX/reg0_b3
|
|
877 16.877000 1 1
|
|
Timing path: u_logic/_al_u4349|cpuresetn_reg.clk->SPI_TX/reg0_b7|SPI_TX/reg0_b3
|
|
u_logic/_al_u4349|cpuresetn_reg.clk
|
|
SPI_TX/reg0_b7|SPI_TX/reg0_b3
|
|
879 16.877000 19.700000 2.823000 0 1
|
|
cpuresetn SPI_TX/reg0_b7|SPI_TX/reg0_b3.sr
|
|
|
|
|
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Endpoint: SPI_TX/reg0_b11|SPI_TX/reg0_b12
|
|
906 16.877000 1 1
|
|
Timing path: u_logic/_al_u4349|cpuresetn_reg.clk->SPI_TX/reg0_b11|SPI_TX/reg0_b12
|
|
u_logic/_al_u4349|cpuresetn_reg.clk
|
|
SPI_TX/reg0_b11|SPI_TX/reg0_b12
|
|
908 16.877000 19.700000 2.823000 0 1
|
|
cpuresetn SPI_TX/reg0_b11|SPI_TX/reg0_b12.sr
|
|
|
|
|
|
|
|
Removal check
|
|
935 3
|
|
Endpoint: u_logic/_al_u134|u_logic/Dqkbx6_reg
|
|
937 0.281000 1 1
|
|
Timing path: u_logic/Hwhpw6_reg|u_logic/Kxhpw6_reg.clk->u_logic/_al_u134|u_logic/Dqkbx6_reg
|
|
u_logic/Hwhpw6_reg|u_logic/Kxhpw6_reg.clk
|
|
u_logic/_al_u134|u_logic/Dqkbx6_reg
|
|
939 0.281000 0.300000 0.581000 0 1
|
|
u_logic/Kxhpw6 u_logic/_al_u134|u_logic/Dqkbx6_reg.sr
|
|
|
|
|
|
Endpoint: u_logic/_al_u1045|u_logic/T82qw6_reg
|
|
966 0.281000 1 1
|
|
Timing path: u_logic/Hwhpw6_reg|u_logic/Kxhpw6_reg.clk->u_logic/_al_u1045|u_logic/T82qw6_reg
|
|
u_logic/Hwhpw6_reg|u_logic/Kxhpw6_reg.clk
|
|
u_logic/_al_u1045|u_logic/T82qw6_reg
|
|
968 0.281000 0.300000 0.581000 0 1
|
|
u_logic/Kxhpw6 u_logic/_al_u1045|u_logic/T82qw6_reg.sr
|
|
|
|
|
|
Endpoint: u_logic/_al_u1021|u_logic/Hpcbx6_reg
|
|
995 0.281000 1 1
|
|
Timing path: u_logic/Hwhpw6_reg|u_logic/Kxhpw6_reg.clk->u_logic/_al_u1021|u_logic/Hpcbx6_reg
|
|
u_logic/Hwhpw6_reg|u_logic/Kxhpw6_reg.clk
|
|
u_logic/_al_u1021|u_logic/Hpcbx6_reg
|
|
997 0.281000 0.300000 0.581000 0 1
|
|
u_logic/Kxhpw6 u_logic/_al_u1021|u_logic/Hpcbx6_reg.sr
|
|
|
|
|
|
|
|
Period check
|
|
1024 4
|
|
Endpoint: ethernet_i0/mac_test0/mac_top0/mac_tx0/udp0/tx_data_fifo/fifo_inst_3_.clkw
|
|
1028 16.700000 1 0
|
|
|
|
Endpoint: ethernet_i0/mac_test0/mac_top0/mac_tx0/udp0/tx_data_fifo/fifo_inst_2_.clkw
|
|
1029 16.700000 1 0
|
|
|
|
Endpoint: ethernet_i0/mac_test0/mac_top0/mac_tx0/udp0/tx_data_fifo/fifo_inst_1_.clkw
|
|
1030 16.700000 1 0
|
|
|
|
Endpoint: ethernet_i0/mac_test0/mac_top0/mac_tx0/udp0/tx_data_fifo/fifo_inst_0_.clkw
|
|
1031 16.700000 1 0
|
|
|
|
|
|
|
|
|
|
Timing group statistics:
|
|
Clock constraints:
|
|
Clock Name Min Period Max Freq Skew Fanout TNS
|
|
DeriveClock (50.0MHz) 29.076ns 34MHz 0.000ns 6999 -697.928ns
|
|
Minimum input arrival time before clock: no constraint path
|
|
Maximum output required time after clock: no constraint path
|
|
Maximum combinational path delay: no constraint path
|
|
Warning: No clock constraint on 16 clock net(s):
|
|
CW_CLK_MSI
|
|
FM_HW/ADC_CLK
|
|
FM_HW/CW_CLK
|
|
FM_HW/EOC
|
|
FM_HW/FM_Demodulation/EOC_Count_Demodulate
|
|
FM_HW/FM_Demodulation/I2S_BCLK_pad
|
|
FM_HW/FM_RSSI_SCAN/EOC_Count_Demodulate
|
|
FM_HW/clk_PWM_160
|
|
FM_HW/clk_PWM_256
|
|
FM_HW/clk_fm_demo_sampling
|
|
MSI_REFCLK_pad
|
|
clk_fm_ethernet
|
|
clk_pad
|
|
ethernet_i0/gmii_rx_clk
|
|
scan_unit/scan_clk
|
|
u_logic/SWCLKTCK_pad
|
|
|