mirror of
https://github.com/JefferyLi0903/MMC.git
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100 lines
2.5 KiB
Verilog
100 lines
2.5 KiB
Verilog
/************************************************************\
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** Copyright (c) 2011-2021 Anlogic, Inc.
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** All Right Reserved.
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\************************************************************/
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/************************************************************\
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** Log : This file is generated by Anlogic IP Generator.
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** File : /home/jefferyli/Downloads/MMC/project/al_ip/PLL_PWM.v
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** Date : 2023 05 23
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** TD version : 5.0.43066
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\************************************************************/
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///////////////////////////////////////////////////////////////////////////////
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// Input frequency: 50.000Mhz
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// Clock multiplication factor: 16
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// Clock division factor: 5
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// Clock information:
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// Clock name | Frequency | Phase shift
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// C0 | 160.000000MHZ | 0 DEG
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// C1 | 240.000000MHZ | 0 DEG
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// C2 | 320.000000MHZ | 0 DEG
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// C3 | 80.000000 MHZ | 0 DEG
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///////////////////////////////////////////////////////////////////////////////
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`timescale 1 ns / 100 fs
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module PLL_PWM(refclk,
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reset,
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stdby,
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extlock,
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clk0_out,
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clk1_out,
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clk2_out,
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clk3_out);
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input refclk;
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input reset;
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input stdby;
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output extlock;
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output clk0_out;
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output clk1_out;
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output clk2_out;
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output clk3_out;
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wire clk0_buf;
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EG_LOGIC_BUFG bufg_feedback( .i(clk0_buf), .o(clk0_out) );
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EG_PHY_PLL #(.DPHASE_SOURCE("DISABLE"),
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.DYNCFG("DISABLE"),
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.FIN("50.000"),
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.FEEDBK_MODE("NORMAL"),
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.FEEDBK_PATH("CLKC0_EXT"),
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.STDBY_ENABLE("ENABLE"),
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.PLLRST_ENA("ENABLE"),
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.SYNC_ENABLE("DISABLE"),
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.DERIVE_PLL_CLOCKS("DISABLE"),
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.GEN_BASIC_CLOCK("DISABLE"),
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.GMC_GAIN(0),
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.ICP_CURRENT(9),
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.KVCO(2),
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.LPF_CAPACITOR(2),
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.LPF_RESISTOR(8),
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.REFCLK_DIV(5),
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.FBCLK_DIV(16),
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.CLKC0_ENABLE("ENABLE"),
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.CLKC0_DIV(6),
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.CLKC0_CPHASE(5),
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.CLKC0_FPHASE(0),
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.CLKC1_ENABLE("ENABLE"),
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.CLKC1_DIV(4),
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.CLKC1_CPHASE(3),
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.CLKC1_FPHASE(0),
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.CLKC2_ENABLE("ENABLE"),
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.CLKC2_DIV(3),
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.CLKC2_CPHASE(2),
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.CLKC2_FPHASE(0),
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.CLKC3_ENABLE("ENABLE"),
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.CLKC3_DIV(12),
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.CLKC3_CPHASE(11),
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.CLKC3_FPHASE(0) )
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pll_inst (.refclk(refclk),
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.reset(reset),
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.stdby(stdby),
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.extlock(extlock),
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.load_reg(1'b0),
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.psclk(1'b0),
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.psdown(1'b0),
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.psstep(1'b0),
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.psclksel(3'b000),
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.psdone(open),
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.dclk(1'b0),
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.dcs(1'b0),
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.dwe(1'b0),
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.di(8'b00000000),
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.daddr(6'b000000),
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.do({open, open, open, open, open, open, open, open}),
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.fbclk(clk0_out),
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.clkc({open, clk3_out, clk2_out, clk1_out, clk0_buf}));
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endmodule
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