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https://github.com/JefferyLi0903/MMC.git
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55 lines
771 B
Verilog
55 lines
771 B
Verilog
// Verilog testbench created by TD v5.0.43066
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// 2022-06-25 11:13:09
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`timescale 1ns / 1ps
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module CortexM0_SoC_tb();
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reg RSTn;
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reg RXD;
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reg SWCLK;
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reg clk;
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wire [7:0] LED;
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wire MSI_CS;
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wire MSI_REFCLK;
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reg MSI_SCLK;
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wire MSI_SDATA;
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wire TXD;
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wire audio_pwm;
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wire [7:0] seg;
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wire [3:0] sel;
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wire SWDIO;
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//Clock process
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parameter PERIOD = 10;
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always #(PERIOD/2) MSI_SCLK = ~MSI_SCLK;
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//glbl Instantiate
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glbl glbl();
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//Unit Instantiate
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CortexM0_SoC uut(
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.RSTn(RSTn),
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.RXD(RXD),
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.SWCLK(SWCLK),
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.clk(clk),
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.LED(LED),
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.MSI_CS(MSI_CS),
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.MSI_REFCLK(MSI_REFCLK),
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.MSI_SCLK(MSI_SCLK),
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.MSI_SDATA(MSI_SDATA),
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.TXD(TXD),
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.audio_pwm(audio_pwm),
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.seg(seg),
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.sel(sel),
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.SWDIO(SWDIO));
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//Stimulus process
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initial begin
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clk = 0;
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RSTn=0;
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#100
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RSTn=1;
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end
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endmodule |