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https://github.com/JefferyLi0903/MMC.git
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74 lines
1.8 KiB
Verilog
74 lines
1.8 KiB
Verilog
module UART_TX (
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input clk ,
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input clk_uart,
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input RSTn ,
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input [7:0] data ,
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input tx_en ,
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output reg TXD ,
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output wire state ,
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output wire bps_en
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);
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//FIFO 8bit-16depth
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wire FIFOrd_en;
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wire FIFOwr_en;
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wire [7:0] FIFOdata ;
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wire FIFOempty;
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wire FIFOfull ;
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FIFO FIFO (
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.clock(clk ),
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.sclr (RSTn ),
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.rdreq(FIFOrd_en),
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.wrreq(FIFOwr_en),
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.full (FIFOfull ),
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.empty(FIFOempty),
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.data (data ),
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.q (FIFOdata )
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);
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//FIFO write control
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assign FIFOwr_en = (~FIFOfull) & tx_en;
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assign state = FIFOfull;
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//UART TX
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reg counter_en;
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reg [3:0] counter ;
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wire trans_finish;
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assign trans_finish = (counter == 4'hb);
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wire trans_start;
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assign trans_start = (~FIFOempty) & (~counter_en);
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always@(posedge clk or negedge RSTn) begin
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if(~RSTn) counter_en <= 1'b0;
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else if(trans_start) counter_en <= 1'b1;
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else if(trans_finish) counter_en <= 1'b0;
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end
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always@(posedge clk or negedge RSTn) begin
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if(~RSTn) counter <= 4'h0;
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else if(counter_en) begin
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if(clk_uart) counter <= counter + 1'b1;
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else if(trans_finish) counter <= 4'h0;
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end
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end
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assign bps_en = counter_en;
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wire [9:0] data_formed;
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assign data_formed = {1'b1,FIFOdata,1'b0};
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always@(posedge clk or negedge RSTn) begin
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if(~RSTn) TXD <= 1'b1;
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else if(counter_en) begin
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if(clk_uart && (counter <= 4'h9)) TXD <= data_formed[counter];
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end else TXD <= 1'b1;
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end
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//FIFO read control
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assign FIFOrd_en = (~FIFOempty) & trans_finish;
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endmodule |