mirror of
https://github.com/JefferyLi0903/MMC.git
synced 2025-02-06 10:28:22 +08:00
679 lines
20 KiB
Verilog
679 lines
20 KiB
Verilog
`include "header.vh"
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module CortexM0_SoC #(
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parameter FM_ADDR_WIDTH = 13,
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parameter ADDR_WIDTH = 12
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) (
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input wire clk,
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input wire RSTn,
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inout wire SWDIO,
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input wire SWCLK,
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output wire [7:0] LED,
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output wire TXD,
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input wire RXD,
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output wire MSI_REFCLK,
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output wire MSI_SDATA,
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output wire MSI_CS,
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output wire MSI_SCLK,
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output wire audio_pwm,
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output wire [3:0] sel,
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output wire [7:0] seg,
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input wire [3:0] col,
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output wire [3:0] row
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);
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//------------------------------------------------------------------------------
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// DEBUG IOBUF
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//------------------------------------------------------------------------------
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wire SWDO;
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wire SWDOEN;
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wire SWDI;
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assign SWDI = SWDIO;
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assign SWDIO = (SWDOEN) ? SWDO : 1'bz;
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//------------------------------------------------------------------------------
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// Interrupt
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//------------------------------------------------------------------------------
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wire [31:0] IRQ;
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wire interrupt_UART;
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wire interrupt_IQ_done;
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wire Demo_Dump_Done_Interrupt;
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wire RSSI_interrupt;
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wire [15:0] key_interrupt;
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wire [15:0] key_in;
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wire [15:0] key_out;
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/*Set IRQ*/
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assign IRQ = {12'b0,key_interrupt,RSSI_interrupt,Demo_Dump_Done_Interrupt,interrupt_IQ_done,interrupt_UART};
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keyboard_scan scan_unit(clk,col,row,key_in);
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key_filter filter_unit(.clk(clk),.rstn(RSTn),.key_in(key_in),.key_deb(key_out),.en());
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pulse_gen pulse_gen_unit(clk,RSTn,key_out,key_interrupt);
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/***************************/
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wire RXEV;
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assign RXEV = 1'b0;
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//------------------------------------------------------------------------------
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// AHB
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//------------------------------------------------------------------------------
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wire [31:0] HADDR;
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wire [ 2:0] HBURST;
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wire HMASTLOCK;
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wire [ 3:0] HPROT;
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wire [ 2:0] HSIZE;
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wire [ 1:0] HTRANS;
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wire [31:0] HWDATA;
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wire HWRITE;
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wire [31:0] HRDATA;
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wire HRESP;
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wire HMASTER;
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wire HREADY;
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//------------------------------------------------------------------------------
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// RESET AND DEBUG
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//------------------------------------------------------------------------------
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wire SYSRESETREQ;
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reg cpuresetn;
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always @(posedge clk or negedge RSTn)begin
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if (~RSTn) cpuresetn <= 1'b0;
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else if (SYSRESETREQ) cpuresetn <= 1'b0;
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else cpuresetn <= 1'b1;
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end
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wire CDBGPWRUPREQ;
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reg CDBGPWRUPACK;
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always @(posedge clk or negedge RSTn)begin
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if (~RSTn) CDBGPWRUPACK <= 1'b0;
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else CDBGPWRUPACK <= CDBGPWRUPREQ;
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end
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//------------------------------------------------------------------------------
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// Instantiate Cortex-M0 processor logic level
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//------------------------------------------------------------------------------
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cortexm0ds_logic u_logic (
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// System inputs
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.FCLK (clk), //FREE running clock
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.SCLK (clk), //system clock
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.HCLK (clk), //AHB clock
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.DCLK (clk), //Debug clock
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.PORESETn (RSTn), //Power on reset
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.HRESETn (cpuresetn), //AHB and System reset
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.DBGRESETn (RSTn), //Debug Reset
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.RSTBYPASS (1'b0), //Reset bypass
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.SE (1'b0), // dummy scan enable port for synthesis
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// Power management inputs
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.SLEEPHOLDREQn (1'b1), // Sleep extension request from PMU
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.WICENREQ (1'b0), // WIC enable request from PMU
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.CDBGPWRUPACK (CDBGPWRUPACK), // Debug Power Up ACK from PMU
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// Power management outputs
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.CDBGPWRUPREQ (CDBGPWRUPREQ),
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.SYSRESETREQ (SYSRESETREQ),
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// System bus
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.HADDR (HADDR[31:0]),
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.HTRANS (HTRANS[1:0]),
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.HSIZE (HSIZE[2:0]),
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.HBURST (HBURST[2:0]),
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.HPROT (HPROT[3:0]),
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.HMASTER (HMASTER),
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.HMASTLOCK (HMASTLOCK),
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.HWRITE (HWRITE),
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.HWDATA (HWDATA[31:0]),
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.HRDATA (HRDATA[31:0]),
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.HREADY (HREADY),
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.HRESP (HRESP),
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// Interrupts
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.IRQ (IRQ), //Interrupt
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.NMI (1'b0), //Watch dog interrupt
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.IRQLATENCY (8'h0),
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.ECOREVNUM (28'h0),
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// Systick
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.STCLKEN (1'b0),
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.STCALIB (26'h0),
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// Debug - JTAG or Serial wire
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// Inputs
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.nTRST (1'b1),
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.SWDITMS (SWDI),
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.SWCLKTCK (SWCLK),
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.TDI (1'b0),
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// Outputs
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.SWDO (SWDO),
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.SWDOEN (SWDOEN),
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.DBGRESTART (1'b0),
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// Event communication
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.RXEV (RXEV), // Generate event when a DMA operation completed.
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.EDBGRQ (1'b0) // multi-core synchronous halt request
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);
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//------------------------------------------------------------------------------
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// AHBlite Interconncet
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//------------------------------------------------------------------------------
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wire HSEL_P0;
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wire [31:0] HADDR_P0;
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wire [2:0] HBURST_P0;
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wire HMASTLOCK_P0;
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wire [3:0] HPROT_P0;
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wire [2:0] HSIZE_P0;
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wire [1:0] HTRANS_P0;
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wire [31:0] HWDATA_P0;
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wire HWRITE_P0;
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wire HREADY_P0;
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wire HREADYOUT_P0;
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wire [31:0] HRDATA_P0;
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wire HRESP_P0;
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wire HSEL_P1;
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wire [31:0] HADDR_P1;
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wire [2:0] HBURST_P1;
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wire HMASTLOCK_P1;
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wire [3:0] HPROT_P1;
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wire [2:0] HSIZE_P1;
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wire [1:0] HTRANS_P1;
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wire [31:0] HWDATA_P1;
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wire HWRITE_P1;
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wire HREADY_P1;
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wire HREADYOUT_P1;
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wire [31:0] HRDATA_P1;
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wire HRESP_P1;
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wire HSEL_P2;
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wire [31:0] HADDR_P2;
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wire [2:0] HBURST_P2;
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wire HMASTLOCK_P2;
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wire [3:0] HPROT_P2;
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wire [2:0] HSIZE_P2;
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wire [1:0] HTRANS_P2;
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wire [31:0] HWDATA_P2;
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wire HWRITE_P2;
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wire HREADY_P2;
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wire HREADYOUT_P2;
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wire [31:0] HRDATA_P2;
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wire HRESP_P2;
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wire HSEL_P3;
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wire [31:0] HADDR_P3;
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wire [2:0] HBURST_P3;
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wire HMASTLOCK_P3;
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wire [3:0] HPROT_P3;
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wire [2:0] HSIZE_P3;
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wire [1:0] HTRANS_P3;
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wire [31:0] HWDATA_P3;
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wire HWRITE_P3;
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wire HREADY_P3;
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wire HREADYOUT_P3;
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wire [31:0] HRDATA_P3;
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wire HRESP_P3;
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wire HSEL_P4;
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wire [31:0] HADDR_P4;
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wire [2:0] HBURST_P4;
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wire HMASTLOCK_P4;
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wire [3:0] HPROT_P4;
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wire [2:0] HSIZE_P4;
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wire [1:0] HTRANS_P4;
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wire [31:0] HWDATA_P4;
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wire HWRITE_P4;
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wire HREADY_P4;
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wire HREADYOUT_P4;
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wire [31:0] HRDATA_P4;
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wire HRESP_P4;
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wire HSEL_P5;
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wire [31:0] HADDR_P5;
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wire [2:0] HBURST_P5;
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wire HMASTLOCK_P5;
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wire [3:0] HPROT_P5;
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wire [2:0] HSIZE_P5;
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wire [1:0] HTRANS_P5;
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wire [31:0] HWDATA_P5;
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wire HWRITE_P5;
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wire HREADY_P5;
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wire HREADYOUT_P5;
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wire [31:0] HRDATA_P5;
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wire HRESP_P5;
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AHBlite_Interconnect Interconncet(
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.HCLK (clk),
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.HRESETn (cpuresetn),
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// CORE SIDE
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.HADDR (HADDR),
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.HTRANS (HTRANS),
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.HSIZE (HSIZE),
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.HBURST (HBURST),
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.HPROT (HPROT),
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.HMASTLOCK (HMASTLOCK),
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.HWRITE (HWRITE),
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.HWDATA (HWDATA),
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.HRDATA (HRDATA),
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.HREADY (HREADY),
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.HRESP (HRESP),
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// P0
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.HSEL_P0 (HSEL_P0),
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.HADDR_P0 (HADDR_P0),
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.HBURST_P0 (HBURST_P0),
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.HMASTLOCK_P0 (HMASTLOCK_P0),
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.HPROT_P0 (HPROT_P0),
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.HSIZE_P0 (HSIZE_P0),
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.HTRANS_P0 (HTRANS_P0),
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.HWDATA_P0 (HWDATA_P0),
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.HWRITE_P0 (HWRITE_P0),
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.HREADY_P0 (HREADY_P0),
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.HREADYOUT_P0 (HREADYOUT_P0),
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.HRDATA_P0 (HRDATA_P0),
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.HRESP_P0 (HRESP_P0),
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// P1
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.HSEL_P1 (HSEL_P1),
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.HADDR_P1 (HADDR_P1),
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.HBURST_P1 (HBURST_P1),
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.HMASTLOCK_P1 (HMASTLOCK_P1),
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.HPROT_P1 (HPROT_P1),
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.HSIZE_P1 (HSIZE_P1),
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.HTRANS_P1 (HTRANS_P1),
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.HWDATA_P1 (HWDATA_P1),
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.HWRITE_P1 (HWRITE_P1),
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.HREADY_P1 (HREADY_P1),
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.HREADYOUT_P1 (HREADYOUT_P1),
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.HRDATA_P1 (HRDATA_P1),
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.HRESP_P1 (HRESP_P1),
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// P2
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.HSEL_P2 (HSEL_P2),
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.HADDR_P2 (HADDR_P2),
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.HBURST_P2 (HBURST_P2),
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.HMASTLOCK_P2 (HMASTLOCK_P2),
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.HPROT_P2 (HPROT_P2),
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.HSIZE_P2 (HSIZE_P2),
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.HTRANS_P2 (HTRANS_P2),
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.HWDATA_P2 (HWDATA_P2),
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.HWRITE_P2 (HWRITE_P2),
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.HREADY_P2 (HREADY_P2),
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.HREADYOUT_P2 (HREADYOUT_P2),
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.HRDATA_P2 (HRDATA_P2),
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.HRESP_P2 (HRESP_P2),
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// P3
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.HSEL_P3 (HSEL_P3),
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.HADDR_P3 (HADDR_P3),
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.HBURST_P3 (HBURST_P3),
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.HMASTLOCK_P3 (HMASTLOCK_P3),
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.HPROT_P3 (HPROT_P3),
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.HSIZE_P3 (HSIZE_P3),
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.HTRANS_P3 (HTRANS_P3),
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.HWDATA_P3 (HWDATA_P3),
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.HWRITE_P3 (HWRITE_P3),
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.HREADY_P3 (HREADY_P3),
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.HREADYOUT_P3 (HREADYOUT_P3),
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.HRDATA_P3 (HRDATA_P3),
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.HRESP_P3 (HRESP_P3),
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// P4
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.HSEL_P4 (HSEL_P4),
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.HADDR_P4 (HADDR_P4),
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.HBURST_P4 (HBURST_P4),
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.HMASTLOCK_P4 (HMASTLOCK_P4),
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.HPROT_P4 (HPROT_P4),
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.HSIZE_P4 (HSIZE_P4),
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.HTRANS_P4 (HTRANS_P4),
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.HWDATA_P4 (HWDATA_P4),
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.HWRITE_P4 (HWRITE_P4),
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.HREADY_P4 (HREADY_P4),
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.HREADYOUT_P4 (HREADYOUT_P4),
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.HRDATA_P4 (HRDATA_P4),
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.HRESP_P4 (HRESP_P4),
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// P5
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.HSEL_P5 (HSEL_P5),
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.HADDR_P5 (HADDR_P5),
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.HBURST_P5 (HBURST_P5),
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.HMASTLOCK_P5 (HMASTLOCK_P5),
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.HPROT_P5 (HPROT_P5),
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.HSIZE_P5 (HSIZE_P5),
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.HTRANS_P5 (HTRANS_P5),
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.HWDATA_P5 (HWDATA_P5),
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.HWRITE_P5 (HWRITE_P5),
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.HREADY_P5 (HREADY_P5),
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.HREADYOUT_P5 (HREADYOUT_P5),
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.HRDATA_P5 (HRDATA_P5),
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.HRESP_P5 (HRESP_P5)
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);
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//------------------------------------------------------------------------------
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// AHB RAMCODE
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//------------------------------------------------------------------------------
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wire [31:0] RAMCODE_RDATA,RAMCODE_WDATA;
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wire [ADDR_WIDTH-1:0] RAMCODE_WADDR;
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wire [ADDR_WIDTH-1:0] RAMCODE_RADDR;
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wire [3:0] RAMCODE_WRITE;
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AHBlite_Block_RAM RAMCODE_Interface(
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/* Connect to Interconnect Port 0 */
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.HCLK (clk),
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.HRESETn (cpuresetn),
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.HSEL (HSEL_P0),
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.HADDR (HADDR_P0),
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.HPROT (HPROT_P0),
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.HSIZE (HSIZE_P0),
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.HTRANS (HTRANS_P0),
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.HWDATA (HWDATA_P0),
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.HWRITE (HWRITE_P0),
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.HRDATA (HRDATA_P0),
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.HREADY (HREADY_P0),
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.HREADYOUT (HREADYOUT_P0),
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.HRESP (HRESP_P0),
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.BRAM_WRADDR (RAMCODE_WADDR),
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.BRAM_RDADDR (RAMCODE_RADDR),
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.BRAM_RDATA (RAMCODE_RDATA),
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.BRAM_WDATA (RAMCODE_WDATA),
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.BRAM_WRITE (RAMCODE_WRITE)
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/**********************************/
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);
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//------------------------------------------------------------------------------
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// AHB WaterLight
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//------------------------------------------------------------------------------
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/*
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wire [7:0] WaterLight_mode;
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wire [31:0] WaterLight_speed;
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AHBlite_WaterLight WaterLight_Interface(
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.HCLK (clk),
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.HRESETn (cpuresetn),
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.HSEL (HSEL_P2),
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.HADDR (HADDR_P2),
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.HPROT (HPROT_P2),
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.HSIZE (HSIZE_P2),
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.HTRANS (HTRANS_P2),
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.HWDATA (HWDATA_P2),
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.HWRITE (HWRITE_P2),
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.HRDATA (HRDATA_P2),
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.HREADY (HREADY_P2),
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.HREADYOUT (HREADYOUT_P2),
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.HRESP (HRESP_P2),
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.WaterLight_mode (WaterLight_mode),
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.WaterLight_speed (WaterLight_speed)
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);
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*/
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//------------------------------------------------------------------------------
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// AHB RAMDATA
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//------------------------------------------------------------------------------
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wire [31:0] RAMDATA_RDATA;
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wire [31:0] RAMDATA_WDATA;
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wire [ADDR_WIDTH-1:0] RAMDATA_WADDR;
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wire [ADDR_WIDTH-1:0] RAMDATA_RADDR;
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wire [3:0] RAMDATA_WRITE;
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AHBlite_Block_RAM RAMDATA_Interface(
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/* Connect to Interconnect Port 1 */
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.HCLK (clk),
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.HRESETn (cpuresetn),
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.HSEL (HSEL_P1),
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.HADDR (HADDR_P1),
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.HPROT (HPROT_P1),
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.HSIZE (HSIZE_P1),
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.HTRANS (HTRANS_P1),
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.HWDATA (HWDATA_P1),
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.HWRITE (HWRITE_P1),
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.HRDATA (HRDATA_P1),
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.HREADY (HREADY_P1),
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.HREADYOUT (HREADYOUT_P1),
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.HRESP (HRESP_P1),
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.BRAM_WRADDR (RAMDATA_WADDR),
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.BRAM_RDADDR (RAMDATA_RADDR),
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.BRAM_WDATA (RAMDATA_WDATA),
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.BRAM_RDATA (RAMDATA_RDATA),
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.BRAM_WRITE (RAMDATA_WRITE)
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/**********************************/
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);
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//------------------------------------------------------------------------------
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// AHB FMDATA
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//------------------------------------------------------------------------------
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wire [31:0] FMDATA_RDATA;
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wire [31:0] FMDATA_WDATA;
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wire [FM_ADDR_WIDTH-1:0] FMDATA_WADDR;
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wire [FM_ADDR_WIDTH-1:0] FMDATA_RADDR;
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wire [3:0] FMDATA_WRITE;
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AHBlite_Block_RAM_FM_Data FMDATA_Interface(
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/* Connect to Interconnect Port 1 */
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.HCLK (clk),
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.HRESETn (cpuresetn),
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.HSEL (HSEL_P5),
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.HADDR (HADDR_P5),
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.HPROT (HPROT_P5),
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.HSIZE (HSIZE_P5),
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.HTRANS (HTRANS_P5),
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.HWDATA (HWDATA_P5),
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.HWRITE (HWRITE_P5),
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.HRDATA (HRDATA_P5),
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.HREADY (HREADY_P5),
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.HREADYOUT (HREADYOUT_P5),
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.HRESP (HRESP_P5),
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.FM_WRADDR (FMDATA_WADDR),
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.FM_RDADDR (FMDATA_RADDR),
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.FM_WDATA (FMDATA_WDATA),
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.FM_RDATA (FMDATA_RDATA),
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.FM_WRITE (FMDATA_WRITE)
|
|
/**********************************/
|
|
);
|
|
|
|
|
|
//------------------------------------------------------------------------------
|
|
// AHB UART
|
|
//------------------------------------------------------------------------------
|
|
|
|
wire state;
|
|
wire [7:0] UART_RX_data;
|
|
wire [7:0] UART_TX_data;
|
|
wire tx_en;
|
|
|
|
AHBlite_UART UART_Interface(
|
|
.HCLK (clk),
|
|
.HRESETn (cpuresetn),
|
|
.HSEL (HSEL_P3),
|
|
.HADDR (HADDR_P3),
|
|
.HPROT (HPROT_P3),
|
|
.HSIZE (HSIZE_P3),
|
|
.HTRANS (HTRANS_P3),
|
|
.HWDATA (HWDATA_P3),
|
|
.HWRITE (HWRITE_P3),
|
|
.HRDATA (HRDATA_P3),
|
|
.HREADY (HREADY_P3),
|
|
.HREADYOUT (HREADYOUT_P3),
|
|
.HRESP (HRESP_P3),
|
|
.UART_RX (UART_RX_data),
|
|
.state (state),
|
|
.tx_en (tx_en),
|
|
.UART_TX (UART_TX_data)
|
|
);
|
|
|
|
//------------------------------------------------------------------------------
|
|
// AHB SPI
|
|
//------------------------------------------------------------------------------
|
|
|
|
wire [23:0] SPI_TX_Data;
|
|
wire SPI_tx_en;
|
|
|
|
AHBlite_SPI SPI_Interface(
|
|
.HCLK (clk),
|
|
.HRESETn (cpuresetn),
|
|
.HSEL (HSEL_P4),
|
|
.HADDR (HADDR_P4),
|
|
.HPROT (HPROT_P4),
|
|
.HSIZE (HSIZE_P4),
|
|
.HTRANS (HTRANS_P4),
|
|
.HWDATA (HWDATA_P4),
|
|
.HWRITE (HWRITE_P4),
|
|
.HRDATA (HRDATA_P4),
|
|
.HREADY (HREADY_P4),
|
|
.HREADYOUT (HREADYOUT_P4),
|
|
.HRESP (HRESP_P4),
|
|
.tx_en (SPI_tx_en),
|
|
.SPI_TX (SPI_TX_Data)
|
|
);
|
|
|
|
//------------------------------------------------------------------------------
|
|
// RAM
|
|
//------------------------------------------------------------------------------
|
|
|
|
Block_RAM RAM_CODE(
|
|
.clka (clk),
|
|
.addra (RAMCODE_WADDR),
|
|
.addrb (RAMCODE_RADDR),
|
|
.dina (RAMCODE_WDATA),
|
|
.doutb (RAMCODE_RDATA),
|
|
.wea (RAMCODE_WRITE)
|
|
);
|
|
|
|
Block_RAM RAM_DATA(
|
|
.clka (clk),
|
|
.addra (RAMDATA_WADDR),
|
|
.addrb (RAMDATA_RADDR),
|
|
.dina (RAMDATA_WDATA),
|
|
.doutb (RAMDATA_RDATA),
|
|
.wea (RAMDATA_WRITE)
|
|
);
|
|
|
|
/*
|
|
Block_RAM_FM_Data FM_DATA(
|
|
.clka (clk),
|
|
.addra (RAMDATA_WADDR),
|
|
.addrb (RAMDATA_RADDR),
|
|
.dina (RAMDATA_WDATA),
|
|
.doutb (RAMDATA_RDATA),
|
|
.wea (RAMDATA_WRITE)
|
|
);
|
|
*/
|
|
|
|
wire [3:0] FM_HW_state;
|
|
|
|
FM_HW FM_HW(
|
|
.clk (clk),
|
|
.ADC_start (1'b1),
|
|
.RSTn (RSTn),
|
|
.LED_Out (LED),
|
|
.wraddr (FMDATA_WADDR),
|
|
.rdaddr (FMDATA_RADDR),
|
|
.wdata (FMDATA_WDATA),
|
|
.wea (FMDATA_WRITE),
|
|
.rdata (FMDATA_RDATA),
|
|
.FM_HW_state (FM_HW_state),
|
|
.IQ_Write_Done_interrupt (interrupt_IQ_done),
|
|
.audio_pwm (audio_pwm),
|
|
.Demo_Dump_Done_Interrupt (Demo_Dump_Done_Interrupt),
|
|
.RSSI_interrupt (RSSI_interrupt)
|
|
);
|
|
|
|
|
|
FM_Display FM_Display(
|
|
.clk (clk),
|
|
.RSTn (RSTn),
|
|
.wraddr (FMDATA_WADDR),
|
|
.wdata (FMDATA_WDATA),
|
|
.wea (FMDATA_WRITE),
|
|
.FM_HW_state (FM_HW_state),
|
|
.seg (seg),
|
|
.sel (sel)
|
|
);
|
|
|
|
|
|
//------------------------------------------------------------------------------
|
|
// SPI
|
|
//------------------------------------------------------------------------------
|
|
|
|
SPI_TX SPI_TX(
|
|
.clk(clk),
|
|
.CW_CLK_MSI(clk),
|
|
.RSTn(cpuresetn),
|
|
.data(SPI_TX_Data),
|
|
.SPI_tx_en(SPI_tx_en),
|
|
.MSI_SDATA(MSI_SDATA),
|
|
.MSI_SCLK(MSI_SCLK),
|
|
.MSI_CS(MSI_CS)
|
|
);
|
|
|
|
|
|
//------------------------------------------------------------------------------
|
|
// UART
|
|
//------------------------------------------------------------------------------
|
|
|
|
wire clk_uart;
|
|
wire bps_en;
|
|
wire bps_en_rx,bps_en_tx;
|
|
|
|
assign bps_en = bps_en_rx | bps_en_tx;
|
|
|
|
clkuart_pwm clkuart_pwm(
|
|
.clk(clk),
|
|
.RSTn(cpuresetn),
|
|
.clk_uart(clk_uart),
|
|
.bps_en(bps_en)
|
|
);
|
|
|
|
UART_RX UART_RX(
|
|
.clk(clk),
|
|
.clk_uart(clk_uart),
|
|
.RSTn(cpuresetn),
|
|
.RXD(RXD),
|
|
.data(UART_RX_data),
|
|
.interrupt(interrupt_UART),
|
|
.bps_en(bps_en_rx)
|
|
);
|
|
|
|
UART_TX UART_TX(
|
|
.clk(clk),
|
|
.clk_uart(clk_uart),
|
|
.RSTn(cpuresetn),
|
|
.data(UART_TX_data),
|
|
.tx_en(tx_en),
|
|
.TXD(TXD),
|
|
.state(state),
|
|
.bps_en(bps_en_tx)
|
|
);
|
|
|
|
|
|
wire CW_CLK_MSI; //synthesis keep;
|
|
wire CLK_Lock_MSI;
|
|
`ifndef SIM_PROFILE
|
|
RF_REF_24M MSI_REF_CLK(
|
|
.refclk(clk),
|
|
.reset(1'b0),
|
|
.stdby(1'b0),
|
|
.extlock(CLK_Lock_MSI),
|
|
.clk0_out(CW_CLK_MSI),
|
|
.clk3_out(MSI_REFCLK)
|
|
);
|
|
`endif
|
|
|
|
endmodule
|