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58 lines
1.3 KiB
Verilog
58 lines
1.3 KiB
Verilog
module AHBlite_SPI(
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input wire HCLK,
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input wire HRESETn,
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input wire HSEL,
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input wire [31:0] HADDR,
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input wire [1:0] HTRANS,
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input wire [2:0] HSIZE,
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input wire [3:0] HPROT,
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input wire HWRITE,
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input wire [31:0] HWDATA,
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input wire HREADY,
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output wire HREADYOUT,
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output reg [31:0] HRDATA,
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output wire HRESP,
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output wire tx_en,
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output wire [23:0] SPI_TX
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);
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assign HRESP = 1'b0;
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assign HREADYOUT = 1'b1;
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wire read_en;
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assign read_en=HSEL&HTRANS[1]&(~HWRITE)&HREADY;
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wire write_en;
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assign write_en=HSEL&HTRANS[1]&(HWRITE)&HREADY;
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reg [3:0] addr_reg;
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always@(posedge HCLK or negedge HRESETn) begin
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if(~HRESETn) addr_reg <= 4'h0;
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else if(read_en || write_en) addr_reg <= HADDR[3:0];
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end
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reg rd_en_reg;
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always@(posedge HCLK or negedge HRESETn) begin
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if(~HRESETn) rd_en_reg <= 1'b0;
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else if(read_en) rd_en_reg <= 1'b1;
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else rd_en_reg <= 1'b0;
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end
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reg wr_en_reg;
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always@(posedge HCLK or negedge HRESETn) begin
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if(~HRESETn) wr_en_reg <= 1'b0;
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else if(write_en) wr_en_reg <= 1'b1;
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else wr_en_reg <= 1'b0;
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end
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assign tx_en = wr_en_reg ? 1'b1 : 1'b0;
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assign SPI_TX = wr_en_reg ? HWDATA[23:0] : 24'b0;
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always@(*) begin
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HRDATA <= 32'b0;
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end
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endmodule
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