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https://github.com/JefferyLi0903/MMC.git
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126 lines
5.3 KiB
Verilog
126 lines
5.3 KiB
Verilog
module I2S_TX(
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input clk, // 50M clk I2S need a 1M with 20KHz audio data: 20K*(24+1)bit*2 (right+left audio channel) = 1MHz
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input RSTn,
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input [23:0] Ldata,
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input [23:0] Rdata,
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input clk_fm_demo_sampling,
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output I2S_SDATA, // data 50bit
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output wire I2S_BCLK, //clk out
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output reg I2S_LRCLK //L R channel enable
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);
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wire i2s_1m_clk;
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I2S_1M i2s_1m(
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.clk(clk),
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.RSTn(RSTn),
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.i2s_1m_clk(i2s_1m_clk)
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);
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wire [49:0] data_add_onebit_0;
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reg [49:0] data_add_onebit,data_add_onebit_1,data_add_onebit_2;
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assign data_add_onebit_0 = {Ldata[23],Ldata,Rdata[23],Rdata};
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//input data delay 3 1M clock(i2s_1m_clk)
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always@(posedge i2s_1m_clk or negedge RSTn) begin
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if(~RSTn)begin
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data_add_onebit_1 <= 50'h0;
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data_add_onebit_2 <= 50'h0;
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data_add_onebit <= 50'h0;
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end
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else begin
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data_add_onebit_1 <= data_add_onebit_0;
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data_add_onebit_2 <= data_add_onebit_1;
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data_add_onebit <= data_add_onebit_2;
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end
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end
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//1 audio channle use 24bit + 1bit , so left channel + right channle need 50bit so we use 6 bit counter
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reg [5:0] counter;
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reg N_1=1'b0;
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reg N=1'b0;
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//counter shall be aligned to boundary of clk_fm_demo_sampling
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always@(posedge i2s_1m_clk or negedge RSTn) begin
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if(~RSTn) counter <= 6'h0;
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else begin
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N_1<=N;
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N<=clk_fm_demo_sampling;
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if(N>N_1) begin
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counter <= 6'h0;
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end
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else begin
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counter <= counter + 1'b1;
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end
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end
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end
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reg data_temp;
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always@(posedge i2s_1m_clk or negedge RSTn) begin
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if(~RSTn) begin
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I2S_LRCLK <= 1'b1;
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data_temp<=1'b0;
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end
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else begin
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case(counter)
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6'd0: I2S_LRCLK <= 1'b0;
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6'd1: data_temp <= data_add_onebit[48];
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6'd2: data_temp <= data_add_onebit[47];
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6'd3: data_temp <= data_add_onebit[46];
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6'd4: data_temp <= data_add_onebit[45];
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6'd5: data_temp <= data_add_onebit[44];
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6'd6: data_temp <= data_add_onebit[43];
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6'd7: data_temp <= data_add_onebit[42];
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6'd8: data_temp <= data_add_onebit[41];
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6'd9: data_temp <= data_add_onebit[40];
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6'd10: data_temp <= data_add_onebit[39];
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6'd11: data_temp <= data_add_onebit[38];
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6'd12: data_temp <= data_add_onebit[37];
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6'd13: data_temp <= data_add_onebit[36];
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6'd14: data_temp <= data_add_onebit[35];
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6'd15: data_temp <= data_add_onebit[34];
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6'd16: data_temp <= data_add_onebit[33];
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6'd17: data_temp <= data_add_onebit[32];
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6'd18: data_temp <= data_add_onebit[31];
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6'd19: data_temp <= data_add_onebit[30];
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6'd20: data_temp <= data_add_onebit[29];
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6'd21: data_temp <= data_add_onebit[28];
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6'd22: data_temp <= data_add_onebit[27];
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6'd23: data_temp <= data_add_onebit[26];
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6'd24: data_temp <= data_add_onebit[25];
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6'd25: begin I2S_LRCLK <= 1'b1; data_temp <= data_add_onebit[24]; end
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6'd26: data_temp <= data_add_onebit[23];
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6'd27: data_temp <= data_add_onebit[22];
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6'd28: data_temp <= data_add_onebit[21];
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6'd29: data_temp <= data_add_onebit[20];
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6'd30: data_temp <= data_add_onebit[19];
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6'd31: data_temp <= data_add_onebit[18];
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6'd32: data_temp <= data_add_onebit[17];
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6'd33: data_temp <= data_add_onebit[16];
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6'd34: data_temp <= data_add_onebit[15];
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6'd35: data_temp <= data_add_onebit[14];
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6'd36: data_temp <= data_add_onebit[13];
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6'd37: data_temp <= data_add_onebit[12];
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6'd38: data_temp <= data_add_onebit[11];
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6'd39: data_temp <= data_add_onebit[10];
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6'd40: data_temp <= data_add_onebit[9];
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6'd41: data_temp <= data_add_onebit[8];
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6'd42: data_temp <= data_add_onebit[7];
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6'd43: data_temp <= data_add_onebit[6];
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6'd44: data_temp <= data_add_onebit[5];
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6'd45: data_temp <= data_add_onebit[4];
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6'd46: data_temp <= data_add_onebit[3];
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6'd47: data_temp <= data_add_onebit[2];
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6'd48: data_temp <= data_add_onebit[1];
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6'd49: data_temp <= data_add_onebit[0];
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//6'd50: I2S_clk_en<=1'b0;
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//default: begin I2S_clk_en <= 1'b0; end
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endcase
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end
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end
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assign I2S_SDATA = data_temp;
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//assign I2S_BCLK = I2S_clk_en?i2s_1m_clk:1'b0;
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assign I2S_BCLK = i2s_1m_clk;
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endmodule |