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56 lines
1.1 KiB
Verilog
56 lines
1.1 KiB
Verilog
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module lib_mult18M9 (
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a,
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b,
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x
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);
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parameter Na = 18; // Input bit width for "a"
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parameter Nb = 9; // Input bit width for "b"
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parameter Nx = Na + Nb; // Output bit width for "x"
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input [Na-1:0] a;
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input [Nb-1:0] b;
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output [Nx-1:0] x;
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/********************************************************************/
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/* Original Function */
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/********************************************************************/
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function [Nx-1:0] S_MUL;
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input [Na-1:0] a;
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input [Nb-1:0] b;
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reg [Na-1:0] ABSa;
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reg [Nb-1:0] ABSb;
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reg SIGN;
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reg [Nx-1:0] MUL;
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begin
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//absolute element for "a"
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if(a[Na-1])
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ABSa = ~a + 1; //negative entry
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else
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ABSa = a; //positive entry
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//absolute element for "b"
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if(b[Nb-1])
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ABSb = ~b + 1; //negative entry
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else
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ABSb = b; //positive entry
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//absolute multiplication
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MUL = ABSa * ABSb;
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//sign judgment
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SIGN = a[Na-1]^b[Nb-1];
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if(SIGN)
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S_MUL = ~MUL + 1; //negative entry
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else
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S_MUL = MUL; //positive entry
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end
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endfunction
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assign x = S_MUL(a,b);
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endmodule
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