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108 lines
2.3 KiB
Verilog
108 lines
2.3 KiB
Verilog
module AHBlite_SlaveMUX (
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input HCLK,
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input HRESETn,
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input HREADY,
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//port 0
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input P0_HSEL,
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input P0_HREADYOUT,
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input P0_HRESP,
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input [31:0] P0_HRDATA,
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//port 1
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input P1_HSEL,
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input P1_HREADYOUT,
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input P1_HRESP,
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input [31:0] P1_HRDATA,
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//port 2
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input P2_HSEL,
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input P2_HREADYOUT,
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input P2_HRESP,
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input [31:0] P2_HRDATA,
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//port 3
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input P3_HSEL,
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input P3_HREADYOUT,
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input P3_HRESP,
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input [31:0] P3_HRDATA,
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//port 4
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input P4_HSEL,
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input P4_HREADYOUT,
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input P4_HRESP,
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input [31:0] P4_HRDATA,
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//port 5
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input P5_HSEL,
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input P5_HREADYOUT,
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input P5_HRESP,
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input [31:0] P5_HRDATA,
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//output
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output wire HREADYOUT,
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output wire HRESP,
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output wire [31:0] HRDATA
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);
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//reg the hsel
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reg [5:0] hsel_reg;
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always@(posedge HCLK or negedge HRESETn) begin
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if(~HRESETn) hsel_reg <= 6'b000000;
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else if(HREADY) hsel_reg <= {P0_HSEL,P1_HSEL,P2_HSEL,P3_HSEL,P4_HSEL,P5_HSEL};
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end
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//hready mux
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reg hready_mux;
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always@(*) begin
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case(hsel_reg)
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6'b000001 : begin hready_mux = P5_HREADYOUT;end
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6'b000010 : begin hready_mux = P4_HREADYOUT;end
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6'b000100 : begin hready_mux = P3_HREADYOUT;end
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6'b001000 : begin hready_mux = P2_HREADYOUT;end
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6'b010000 : begin hready_mux = P1_HREADYOUT;end
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6'b100000 : begin hready_mux = P0_HREADYOUT;end
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default : begin hready_mux = 1'b1;end
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endcase
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end
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assign HREADYOUT = hready_mux;
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//hresp mux
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reg hresp_mux;
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always@(*) begin
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case(hsel_reg)
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6'b000001 : begin hresp_mux = P5_HRESP;end
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6'b000010 : begin hresp_mux = P4_HRESP;end
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6'b000100 : begin hresp_mux = P3_HRESP;end
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6'b001000 : begin hresp_mux = P2_HRESP;end
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6'b010000 : begin hresp_mux = P1_HRESP;end
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6'b100000 : begin hresp_mux = P0_HRESP;end
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default : begin hresp_mux = 1'b0;end
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endcase
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end
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assign HRESP = hresp_mux;
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//hrdata mux
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reg [31:0] hrdata_mux;
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always@(*) begin
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case(hsel_reg)
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6'b000001 : begin hrdata_mux = P5_HRDATA;end
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6'b000010 : begin hrdata_mux = P4_HRDATA;end
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6'b000100 : begin hrdata_mux = P3_HRDATA;end
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6'b001000 : begin hrdata_mux = P2_HRDATA;end
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6'b010000 : begin hrdata_mux = P1_HRDATA;end
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6'b100000 : begin hrdata_mux = P0_HRDATA;end
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default : begin hrdata_mux = 32'b0;end
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endcase
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end
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assign HRDATA = hrdata_mux;
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endmodule
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