mirror of
https://github.com/JefferyLi0903/MMC.git
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118 lines
2.7 KiB
Verilog
118 lines
2.7 KiB
Verilog
// Verilog netlist created by TD v5.0.43066
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// Fri May 27 17:21:45 2022
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`timescale 1ns / 1ps
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module RF_REF_24M // RF_REF_24M.v(23)
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(
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refclk,
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reset,
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stdby,
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clk0_out,
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clk3_out,
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extlock
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);
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input refclk; // RF_REF_24M.v(30)
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input reset; // RF_REF_24M.v(31)
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input stdby; // RF_REF_24M.v(32)
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output clk0_out; // RF_REF_24M.v(34)
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output clk3_out; // RF_REF_24M.v(35)
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output extlock; // RF_REF_24M.v(33)
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wire clk0_buf; // RF_REF_24M.v(37)
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EG_PHY_GCLK bufg_feedback (
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.clki(clk0_buf),
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.clko(clk0_out)); // RF_REF_24M.v(39)
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EG_PHY_CONFIG #(
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.DONE_PERSISTN("ENABLE"),
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.INIT_PERSISTN("ENABLE"),
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.JTAG_PERSISTN("DISABLE"),
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.PROGRAMN_PERSISTN("DISABLE"))
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config_inst ();
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EG_PHY_PLL #(
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.CLKC0_CPHASE(11),
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.CLKC0_DIV(12),
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.CLKC0_DIV2_ENABLE("DISABLE"),
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.CLKC0_ENABLE("ENABLE"),
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.CLKC0_FPHASE(0),
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.CLKC1_CPHASE(1),
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.CLKC1_DIV(1),
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.CLKC1_DIV2_ENABLE("DISABLE"),
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.CLKC1_ENABLE("DISABLE"),
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.CLKC1_FPHASE(0),
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.CLKC2_CPHASE(1),
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.CLKC2_DIV(1),
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.CLKC2_DIV2_ENABLE("DISABLE"),
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.CLKC2_ENABLE("DISABLE"),
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.CLKC2_FPHASE(0),
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.CLKC3_CPHASE(49),
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.CLKC3_DIV(50),
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.CLKC3_DIV2_ENABLE("DISABLE"),
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.CLKC3_ENABLE("ENABLE"),
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.CLKC3_FPHASE(0),
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.CLKC4_CPHASE(1),
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.CLKC4_DIV(1),
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.CLKC4_DIV2_ENABLE("DISABLE"),
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.CLKC4_ENABLE("DISABLE"),
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.CLKC4_FPHASE(0),
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.DERIVE_PLL_CLOCKS("DISABLE"),
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.DPHASE_SOURCE("DISABLE"),
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.DYNCFG("DISABLE"),
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.FBCLK_DIV(2),
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.FEEDBK_MODE("NORMAL"),
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.FEEDBK_PATH("CLKC0_EXT"),
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.FIN("50.000"),
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.FREQ_LOCK_ACCURACY(2),
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.GEN_BASIC_CLOCK("DISABLE"),
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.GMC_GAIN(4),
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.GMC_TEST(14),
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.ICP_CURRENT(13),
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.IF_ESCLKSTSW("DISABLE"),
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.INTFB_WAKE("DISABLE"),
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.KVCO(4),
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.LPF_CAPACITOR(1),
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.LPF_RESISTOR(4),
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.NORESET("DISABLE"),
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.ODIV_MUXC0("DIV"),
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.ODIV_MUXC1("DIV"),
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.ODIV_MUXC2("DIV"),
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.ODIV_MUXC3("DIV"),
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.ODIV_MUXC4("DIV"),
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.PLLC2RST_ENA("DISABLE"),
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.PLLC34RST_ENA("DISABLE"),
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.PLLMRST_ENA("DISABLE"),
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.PLLRST_ENA("ENABLE"),
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.PLL_LOCK_MODE(0),
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.PREDIV_MUXC0("VCO"),
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.PREDIV_MUXC1("VCO"),
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.PREDIV_MUXC2("VCO"),
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.PREDIV_MUXC3("VCO"),
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.PREDIV_MUXC4("VCO"),
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.REFCLK_DIV(1),
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.REFCLK_SEL("INTERNAL"),
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.STDBY_ENABLE("ENABLE"),
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.STDBY_VCO_ENA("DISABLE"),
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.SYNC_ENABLE("DISABLE"),
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.VCO_NORESET("DISABLE"))
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pll_inst (
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.daddr(6'b000000),
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.dclk(1'b0),
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.dcs(1'b0),
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.di(8'b00000000),
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.dwe(1'b0),
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.fbclk(clk0_out),
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.load_reg(1'b0),
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.psclk(1'b0),
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.psclksel(3'b000),
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.psdown(1'b0),
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.psstep(1'b0),
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.refclk(refclk),
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.reset(reset),
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.stdby(stdby),
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.clkc({open_n47,clk3_out,open_n48,open_n49,clk0_buf}),
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.extlock(extlock)); // RF_REF_24M.v(66)
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endmodule
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