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24 lines
700 B
Verilog
24 lines
700 B
Verilog
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module clk_fm_demo_sample_pwm #(
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parameter BPS_PARA = 10 ) //400Khz/BPS_PARA = audio samping rate. BPS_PARA=20: 20kHz
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(
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input FM_demod_en,
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input EOC,
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input RSTn,
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output reg clk_fm_demo_sampling
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);
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reg [5:0] cnt = 0;
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always @ (posedge EOC or negedge RSTn) begin
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if(~RSTn) cnt <= 6'b0;
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else if (~FM_demod_en) begin
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if((cnt >= BPS_PARA-1)||(FM_demod_en)) begin
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cnt <= 6'b0;
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clk_fm_demo_sampling <= 1'b1;
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end
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else begin cnt <= cnt + 1'b1;clk_fm_demo_sampling <= 1'b0; end
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end
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else clk_fm_demo_sampling <= 1'b0;
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end
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endmodule |