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41 lines
816 B
Verilog
41 lines
816 B
Verilog
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module Aduio_PWM
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(
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input clk_fm_demo_sampling,
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input clk,
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input RSTn,
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input demod_en,
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input wire [9:0] demodulated_signal_downsample,
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output wire audio_pwm
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);
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//pwm generation simulate the DAC using 10bit range
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reg [11:0] cnt = 0;
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reg audio_pwm_reg;
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reg N_1=1'b0;
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reg N=1'b0;
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always @ (posedge clk or negedge RSTn) begin
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if(~RSTn) cnt <= 10'b0;
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else begin
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N_1<=N;
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N<=clk_fm_demo_sampling;
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if(N>N_1)
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cnt <= 10'b0;
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else
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cnt <= cnt + 1'b1;
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end
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end
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always @ (posedge clk or negedge RSTn) begin
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if(~RSTn) audio_pwm_reg <= 1'b0;
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else if(cnt >= (demodulated_signal_downsample)) audio_pwm_reg <= 1'b1;
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else audio_pwm_reg <= 1'b0;
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end
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assign audio_pwm = (~demod_en)?audio_pwm_reg:1'b0;
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endmodule |