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74 lines
1.1 KiB
Verilog
74 lines
1.1 KiB
Verilog
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//it is just a normal FIFO
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module FIFO(
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input clock,
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input sclr,
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input rdreq, wrreq,
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output reg full, empty,
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input [7 : 0] data,
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output [7 : 0] q
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);
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reg [7 : 0] mem [15 : 0];
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reg [3 : 0] wp, rp;
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reg w_flag, r_flag;
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initial
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begin
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wp=0;
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w_flag=0;
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rp=0;
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r_flag=0;
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end
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always @(posedge clock) begin
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if (~sclr) begin
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wp <= 0;
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w_flag <= 0;
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end else if(!full && wrreq) begin
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wp<= (wp==16-1) ? 0 : wp+1;
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w_flag <= (wp==16-1) ? ~w_flag : w_flag;
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end
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end
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always @(posedge clock) begin
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if(wrreq && !full)begin
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mem[wp] <= data;
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end
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end
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always @(posedge clock) begin
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if (~sclr) begin
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rp<=0;
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r_flag <= 0;
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end else if(!empty && rdreq) begin
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rp<= (rp==16-1) ? 0 : rp+1;
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r_flag <= (rp==16-1) ? ~r_flag : r_flag;
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end
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end
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assign q = mem[rp];
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always @(*) begin
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if(wp==rp)begin
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if(r_flag==w_flag)begin
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full <= 0;
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empty <= 1;
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end else begin
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full <= 1;
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empty <= 0;
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end
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end else begin
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full <= 0;
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empty <= 0;
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end
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end
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endmodule |