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https://github.com/JefferyLi0903/MMC.git
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118 lines
3.9 KiB
Verilog
118 lines
3.9 KiB
Verilog
module SPI_TX (
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input clk ,
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input CW_CLK_MSI,
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input RSTn ,
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input [23:0] data ,
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input SPI_tx_en ,
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output MSI_SDATA , //! port 30, connected to pin N9
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output wire MSI_SCLK , //! port 29, connected to pin M9
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output reg MSI_CS //! port 31, connected to pin P9
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);
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//FIFO 24bit-24depth
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wire FIFOrd_en ;
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wire FIFOwr_en ;
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wire [24:0] FIFOdata ;
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wire FIFOempty ;
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wire FIFOfull ;
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wire [24:0] data_add_onebit;
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assign data_add_onebit = {data[23],data};
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FIFO_SPI FIFO_SPI (
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.clock(clk ),
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.sclr (RSTn ),
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.rdreq(FIFOrd_en ),
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.wrreq(FIFOwr_en ),
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.full (FIFOfull ),
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.empty(FIFOempty ),
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.data (data_add_onebit),
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.q (FIFOdata )
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);
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//FIFO write control
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assign FIFOwr_en = (~FIFOfull) & SPI_tx_en;
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//SPI TX
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reg count_en;
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//according to MSI001 datasheet, 1 SPI Word will transmit 24bit,
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//interword delay need 300ns. now we use 50M clk which the interword delay need 15000 clk.
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//so the counter will be 15024, we need 14bit to store the counter
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reg [13:0] counter;
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wire trans_finish;
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assign trans_finish = (counter == 14'd15024); //14'd15024
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wire trans_start;
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assign trans_start = (~FIFOempty) & (~count_en);
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always@(posedge clk or negedge RSTn) begin
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if(~RSTn) count_en <= 1'b0;
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else if(trans_start) count_en <= 1'b1;
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else if(trans_finish) begin count_en <= 1'b0; end
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end
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always@(posedge clk or negedge RSTn) begin
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if(~RSTn) counter <= 14'h0;
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else if(counter == 14'd15024) counter <= 14'h0; //14'd15025
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else if(count_en) counter <= counter + 1'b1;
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end
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reg data_temp ;
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reg MSI_clk_en;
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wire [24:0] read_fifo ;
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assign read_fifo = FIFOdata;
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always@(posedge clk or negedge RSTn) begin
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if(~RSTn) begin
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MSI_CS <= 1'b1;
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MSI_clk_en <= 1'b0;
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data_temp <= 25'h0;
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end
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else if(count_en) begin
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case(counter)
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14'd0 : begin MSI_CS <= 1'b0; data_temp <= read_fifo[24]; MSI_clk_en<=1'b0; end
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14'd1 : begin data_temp <= read_fifo[23]; MSI_clk_en<=1'b1;end
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14'd2 : data_temp <= read_fifo[22];
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14'd3 : data_temp <= read_fifo[21];
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14'd4 : data_temp <= read_fifo[20];
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14'd5 : data_temp <= read_fifo[19];
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14'd6 : data_temp <= read_fifo[18];
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14'd7 : data_temp <= read_fifo[17];
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14'd8 : data_temp <= read_fifo[16];
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14'd9 : data_temp <= read_fifo[15];
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14'd10 : data_temp <= read_fifo[14];
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14'd11 : data_temp <= read_fifo[13];
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14'd12 : data_temp <= read_fifo[12];
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14'd13 : data_temp <= read_fifo[11];
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14'd14 : data_temp <= read_fifo[10];
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14'd15 : data_temp <= read_fifo[9];
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14'd16 : data_temp <= read_fifo[8];
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14'd17 : data_temp <= read_fifo[7];
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14'd18 : data_temp <= read_fifo[6];
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14'd19 : data_temp <= read_fifo[5];
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14'd20 : data_temp <= read_fifo[4];
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14'd21 : data_temp <= read_fifo[3];
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14'd22 : data_temp <= read_fifo[2];
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14'd23 : data_temp <= read_fifo[1];
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14'd24 : data_temp <= read_fifo[0];
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14'd25 : MSI_clk_en<=1'b0;
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default : begin MSI_CS <= 1'b1; end
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endcase
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end
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end
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assign MSI_SDATA = data_temp;
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assign MSI_SCLK = MSI_clk_en?~clk:1'b0;
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//FIFO read control
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assign FIFOrd_en = (~FIFOempty) & trans_finish;
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endmodule |