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78 lines
2.2 KiB
Verilog
78 lines
2.2 KiB
Verilog
module AHBlite_Block_RAM #(
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parameter ADDR_WIDTH = 12)(
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input wire HCLK,
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input wire HRESETn,
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input wire HSEL,
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input wire [31:0] HADDR,
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input wire [1:0] HTRANS,
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input wire [2:0] HSIZE,
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input wire [3:0] HPROT,
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input wire HWRITE,
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input wire [31:0] HWDATA,
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input wire HREADY,
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output wire HREADYOUT,
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output wire [31:0] HRDATA,
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output wire [1:0] HRESP,
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output wire [ADDR_WIDTH-1:0] BRAM_RDADDR,
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output wire [ADDR_WIDTH-1:0] BRAM_WRADDR,
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input wire [31:0] BRAM_RDATA,
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output wire [31:0] BRAM_WDATA,
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output wire [3:0] BRAM_WRITE
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);
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assign HRESP = 2'b0;
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assign HRDATA = BRAM_RDATA;
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wire trans_en;
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assign trans_en = HSEL & HTRANS[1];
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wire write_en;
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assign write_en = trans_en & HWRITE;
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wire read_en;
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assign read_en = trans_en & (~HWRITE);
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reg [3:0] size_dec;
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always@(*) begin
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case({HADDR[1:0],HSIZE[1:0]})
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4'h0 : size_dec = 4'h1;
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4'h1 : size_dec = 4'h3;
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4'h2 : size_dec = 4'hf;
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4'h4 : size_dec = 4'h2;
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4'h8 : size_dec = 4'h4;
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4'h9 : size_dec = 4'hc;
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4'hc : size_dec = 4'h8;
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default : size_dec = 4'h0;
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endcase
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end
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reg [3:0] size_reg;
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always@(posedge HCLK or negedge HRESETn) begin
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if(~HRESETn) size_reg <= 0;
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else if(write_en & HREADY) size_reg <= size_dec;
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end
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reg [ADDR_WIDTH-1:0] addr_reg;
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always@(posedge HCLK or negedge HRESETn) begin
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if(~HRESETn) addr_reg <= 0;
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else if(trans_en & HREADY) addr_reg <= HADDR[(ADDR_WIDTH+1):2];
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end
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reg wr_en_reg;
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always@(posedge HCLK or negedge HRESETn) begin
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if(~HRESETn) wr_en_reg <= 1'b0;
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else if(HREADY) wr_en_reg <= write_en;
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else wr_en_reg <= 1'b0;
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end
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assign BRAM_RDADDR = HADDR[(ADDR_WIDTH+1):2];
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assign BRAM_WRADDR = addr_reg;
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assign HREADYOUT = 1'b1;
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assign BRAM_WRITE = wr_en_reg ? size_reg : 4'h0;
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assign BRAM_WDATA = HWDATA;
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endmodule
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