mirror of
https://github.com/JefferyLi0903/MMC.git
synced 2025-01-22 10:22:53 +08:00
252 lines
7.0 KiB
Verilog
252 lines
7.0 KiB
Verilog
module AHBlite_Interconnect(
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// CLK & RST
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input wire HCLK,
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input wire HRESETn,
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// CORE SIDE
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input wire [31:0] HADDR,
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input wire [2:0] HBURST,
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input wire HMASTLOCK,
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input wire [3:0] HPROT,
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input wire [2:0] HSIZE,
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input wire [1:0] HTRANS,
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input wire [31:0] HWDATA,
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input wire HWRITE,
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output wire HREADY,
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output wire [31:0] HRDATA,
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output wire HRESP,
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// Peripheral 0
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output wire HSEL_P0,
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output wire [31:0] HADDR_P0,
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output wire [2:0] HBURST_P0,
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output wire HMASTLOCK_P0,
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output wire [3:0] HPROT_P0,
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output wire [2:0] HSIZE_P0,
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output wire [1:0] HTRANS_P0,
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output wire [31:0] HWDATA_P0,
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output wire HWRITE_P0,
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output wire HREADY_P0,
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input wire HREADYOUT_P0,
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input wire [31:0] HRDATA_P0,
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input wire HRESP_P0,
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// Peripheral 1
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output wire HSEL_P1,
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output wire [31:0] HADDR_P1,
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output wire [2:0] HBURST_P1,
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output wire HMASTLOCK_P1,
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output wire [3:0] HPROT_P1,
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output wire [2:0] HSIZE_P1,
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output wire [1:0] HTRANS_P1,
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output wire [31:0] HWDATA_P1,
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output wire HWRITE_P1,
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output wire HREADY_P1,
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input wire HREADYOUT_P1,
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input wire [31:0] HRDATA_P1,
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input wire HRESP_P1,
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// Peripheral 2
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output wire HSEL_P2,
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output wire [31:0] HADDR_P2,
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output wire [2:0] HBURST_P2,
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output wire HMASTLOCK_P2,
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output wire [3:0] HPROT_P2,
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output wire [2:0] HSIZE_P2,
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output wire [1:0] HTRANS_P2,
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output wire [31:0] HWDATA_P2,
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output wire HWRITE_P2,
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output wire HREADY_P2,
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input wire HREADYOUT_P2,
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input wire [31:0] HRDATA_P2,
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input wire HRESP_P2,
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// Peripheral 3
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output wire HSEL_P3,
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output wire [31:0] HADDR_P3,
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output wire [2:0] HBURST_P3,
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output wire HMASTLOCK_P3,
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output wire [3:0] HPROT_P3,
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output wire [2:0] HSIZE_P3,
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output wire [1:0] HTRANS_P3,
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output wire [31:0] HWDATA_P3,
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output wire HWRITE_P3,
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output wire HREADY_P3,
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input wire HREADYOUT_P3,
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input wire [31:0] HRDATA_P3,
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input wire HRESP_P3,
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// Peripheral 4 for SPI data
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output wire HSEL_P4,
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output wire [31:0] HADDR_P4,
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output wire [2:0] HBURST_P4,
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output wire HMASTLOCK_P4,
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output wire [3:0] HPROT_P4,
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output wire [2:0] HSIZE_P4,
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output wire [1:0] HTRANS_P4,
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output wire [31:0] HWDATA_P4,
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output wire HWRITE_P4,
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output wire HREADY_P4,
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input wire HREADYOUT_P4,
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input wire [31:0] HRDATA_P4,
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input wire HRESP_P4,
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// Peripheral 5 for FM HW control&memory
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output wire HSEL_P5,
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output wire [31:0] HADDR_P5,
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output wire [2:0] HBURST_P5,
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output wire HMASTLOCK_P5,
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output wire [3:0] HPROT_P5,
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output wire [2:0] HSIZE_P5,
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output wire [1:0] HTRANS_P5,
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output wire [31:0] HWDATA_P5,
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output wire HWRITE_P5,
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output wire HREADY_P5,
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input wire HREADYOUT_P5,
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input wire [31:0] HRDATA_P5,
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input wire HRESP_P5
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);
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// Public signals--------------------------------
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//-----------------------------------------------
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// HADDR
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assign HADDR_P0 = HADDR;
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assign HADDR_P1 = HADDR;
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assign HADDR_P2 = HADDR;
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assign HADDR_P3 = HADDR;
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assign HADDR_P4 = HADDR;
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assign HADDR_P5 = HADDR;
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// HBURST
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assign HBURST_P0 = HBURST;
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assign HBURST_P1 = HBURST;
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assign HBURST_P2 = HBURST;
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assign HBURST_P3 = HBURST;
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assign HBURST_P4 = HBURST;
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assign HBURST_P5 = HBURST;
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// HMASTLOCK
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assign HMASTLOCK_P0 = HMASTLOCK;
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assign HMASTLOCK_P1 = HMASTLOCK;
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assign HMASTLOCK_P2 = HMASTLOCK;
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assign HMASTLOCK_P3 = HMASTLOCK;
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assign HMASTLOCK_P4 = HMASTLOCK;
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assign HMASTLOCK_P5 = HMASTLOCK;
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// HPROT
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assign HPROT_P0 = HPROT;
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assign HPROT_P1 = HPROT;
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assign HPROT_P2 = HPROT;
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assign HPROT_P3 = HPROT;
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assign HPROT_P4 = HPROT;
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assign HPROT_P5 = HPROT;
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// HSIZE
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assign HSIZE_P0 = HSIZE;
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assign HSIZE_P1 = HSIZE;
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assign HSIZE_P2 = HSIZE;
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assign HSIZE_P3 = HSIZE;
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assign HSIZE_P4 = HSIZE;
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assign HSIZE_P5 = HSIZE;
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// HTRANS
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assign HTRANS_P0 = HTRANS;
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assign HTRANS_P1 = HTRANS;
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assign HTRANS_P2 = HTRANS;
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assign HTRANS_P3 = HTRANS;
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assign HTRANS_P4 = HTRANS;
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assign HTRANS_P5 = HTRANS;
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// HWDATA
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assign HWDATA_P0 = HWDATA;
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assign HWDATA_P1 = HWDATA;
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assign HWDATA_P2 = HWDATA;
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assign HWDATA_P3 = HWDATA;
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assign HWDATA_P4 = HWDATA;
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assign HWDATA_P5 = HWDATA;
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// HWRITE
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assign HWRITE_P0 = HWRITE;
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assign HWRITE_P1 = HWRITE;
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assign HWRITE_P2 = HWRITE;
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assign HWRITE_P3 = HWRITE;
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assign HWRITE_P4 = HWRITE;
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assign HWRITE_P5 = HWRITE;
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// HREADY
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assign HREADY_P0 = HREADY;
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assign HREADY_P1 = HREADY;
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assign HREADY_P2 = HREADY;
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assign HREADY_P3 = HREADY;
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assign HREADY_P4 = HREADY;
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assign HREADY_P5 = HREADY;
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// Decoder---------------------------------------
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//-----------------------------------------------
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AHBlite_Decoder Decoder(
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.HADDR (HADDR),
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.P0_HSEL (HSEL_P0),
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.P1_HSEL (HSEL_P1),
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.P2_HSEL (HSEL_P2),
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.P3_HSEL (HSEL_P3),
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.P4_HSEL (HSEL_P4),
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.P5_HSEL (HSEL_P5)
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);
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// Slave MUX-------------------------------------
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//-----------------------------------------------
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AHBlite_SlaveMUX SlaveMUX(
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// CLOCK & RST
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.HCLK (HCLK),
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.HRESETn (HRESETn),
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.HREADY (HREADY),
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//P0
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.P0_HSEL (HSEL_P0),
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.P0_HREADYOUT (HREADYOUT_P0),
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.P0_HRESP (HRESP_P0),
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.P0_HRDATA (HRDATA_P0),
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//P1
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.P1_HSEL (HSEL_P1),
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.P1_HREADYOUT (HREADYOUT_P1),
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.P1_HRESP (HRESP_P1),
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.P1_HRDATA (HRDATA_P1),
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//P2
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.P2_HSEL (HSEL_P2),
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.P2_HREADYOUT (HREADYOUT_P2),
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.P2_HRESP (HRESP_P2),
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.P2_HRDATA (HRDATA_P2),
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//P3
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.P3_HSEL (HSEL_P3),
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.P3_HREADYOUT (HREADYOUT_P3),
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.P3_HRESP (HRESP_P3),
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.P3_HRDATA (HRDATA_P3),
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//P4
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.P4_HSEL (HSEL_P4),
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.P4_HREADYOUT (HREADYOUT_P4),
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.P4_HRESP (HRESP_P4),
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.P4_HRDATA (HRDATA_P4),
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//P5
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.P5_HSEL (HSEL_P5),
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.P5_HREADYOUT (HREADYOUT_P5),
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.P5_HRESP (HRESP_P5),
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.P5_HRDATA (HRDATA_P5),
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.HREADYOUT (HREADY),
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.HRESP (HRESP),
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.HRDATA (HRDATA)
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);
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endmodule |