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https://github.com/JefferyLi0903/MMC.git
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120 lines
3.2 KiB
Verilog
120 lines
3.2 KiB
Verilog
module keyboard_scan(clk,col,row,key);
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input clk;
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input [3:0] col;
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output reg [3:0] row = 4'b1110;
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output reg [15:0] key;
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reg [31:0] cnt = 0;
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reg scan_clk = 0;
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always@(posedge clk) begin
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if(cnt == 2499) begin
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cnt <= 0;
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scan_clk <= ~scan_clk;
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end
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else
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cnt <= cnt + 1;
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end
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always@(posedge scan_clk)
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row <= {row[2:0],row[3]};
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always@(negedge scan_clk)
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case(row)
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4'b1110 : key[3:0] <= col;
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4'b1101 : key[7:4] <= col;
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4'b1011 : key[11:8] <= col;
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4'b0111 : key[15:12] <= col;
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default : key <= 0;
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endcase
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endmodule
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module key_filter(clk,rstn,key_in,key_deb,en);
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input clk;
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input rstn;
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input [15:0] key_in;
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output [15:0] key_deb;
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output en;
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// Counting
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reg [19:0] cnt = 0;
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parameter CNTMAX = 999_999;
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always@(posedge clk or negedge rstn) begin
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if(~rstn)
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cnt <= 0;
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else if(cnt == CNTMAX)
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cnt <= 0;
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else
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cnt <= cnt + 1'b1;
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end
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// Sampling
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reg [15:0] key_reg0;
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reg [15:0] key_reg1;
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reg [15:0] key_reg2;
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always@(posedge clk or negedge rstn) begin
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if(~rstn) begin
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key_reg0 <= 16'hffff;
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key_reg1 <= 16'hffff;
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key_reg2 <= 16'hffff;
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end
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else if(cnt == CNTMAX) begin
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key_reg0 <= key_in;
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key_reg1 <= key_reg0;
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key_reg2 <= key_reg1;
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end
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end
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assign key_deb = (~key_reg0&~key_reg1& ~key_reg2)|(~key_reg0&~key_reg1&key_reg2);
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// State_machine
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parameter s0 = 1'b0 ;
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parameter s1 = 1'b1 ;
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reg [2:0] current_state ; //statement
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reg [2:0] next_state ; //statement
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reg [15:0] key_debb;// define the intermediate variable
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reg en;
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always@(posedge clk or negedge rstn) begin
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if(~rstn) begin
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current_state <= s0;
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next_state <= s0;
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end
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else begin
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current_state <= next_state;
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key_debb <= key_deb;
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case(current_state)
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s0:if(key_deb == key_debb) begin//s0
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next_state <= s0;
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en <= 0;
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end
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else begin
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next_state <= s1;
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en <= 1;
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end
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s1:if(key_deb == key_debb) begin//s1
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next_state <= s1;
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en <= 0;
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end
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else begin
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next_state <= s0;
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en <= 0;
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end
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default:next_state<=s0;
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endcase
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end
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end
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endmodule
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module pulse_gen
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(
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input clk,
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input RSTn,
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input [15:0] key_signal,
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output [15:0] pulse
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);
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reg [15:0] key_reg_1;
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reg [15:0] key_reg_2;
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always @(posedge clk or negedge RSTn) begin
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if (~RSTn) begin
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key_reg_1 <= 0;
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key_reg_2 <= 0;
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end
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else begin
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key_reg_1 <= key_signal;
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key_reg_2 <= key_reg_1;
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end
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end
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assign pulse = (key_signal) & (~key_reg_2);
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endmodule |