mirror of
https://github.com/JefferyLi0903/MMC.git
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106 lines
6.4 KiB
Plaintext
106 lines
6.4 KiB
Plaintext
============================================================
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Tang Dynasty, V5.0.43066
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Copyright: Shanghai Anlogic Infotech Co., Ltd.
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2011 - 2021
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Executable = D:/Anlogic/TD5.0.43066/bin/td.exe
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Built at = 20:38:48 Nov 30 2021
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Run by = JefferyLi
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Run Date = Sat Apr 2 14:51:56 2022
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Run on = LAPTOP-3NKS5JFR
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============================================================
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RUN-001 : GUI based run...
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RUN-1002 : start command "import_device eagle_s20.db -package BG256 -basic"
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ARC-1001 : Device Initialization.
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ARC-1001 : ------------------------------------------------------------------
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ARC-1001 : OPTION | IO | SETTING
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ARC-1001 : ------------------------------------------------------------------
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ARC-1001 : cso_b/cclk/mosi/miso/dout | T3/R11/T10/P10/S11 | gpio
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ARC-1001 : done | P13 | gpio
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ARC-1001 : program_b | T2 | dedicate
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ARC-1001 : tdi/tms/tck/tdo | C12/A15/C14/E14 | dedicate
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ARC-1001 : ------------------------------------------------------------------
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ARC-1004 : Device setting, marked 5 dedicate IOs in total.
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RUN-1002 : start command "read_verilog -file clkdivider.v"
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HDL-1007 : analyze verilog file clkdivider.v
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HDL-1007 : elaborate module clkdivider in clkdivider.v(23)
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HDL-1007 : elaborate module EG_LOGIC_BUFG in D:/Anlogic/TD5.0.43066/arch/eagle_macro.v(8)
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HDL-1007 : elaborate module EG_PHY_PLL(FIN="50.000",FBCLK_DIV=4,CLKC0_DIV=4,CLKC1_DIV=50,CLKC0_ENABLE="ENABLE",CLKC1_ENABLE="ENABLE",FEEDBK_PATH="CLKC0_EXT",CLKC0_CPHASE=3,CLKC1_CPHASE=49,GMC_GAIN=4,ICP_CURRENT=13,KVCO=4,LPF_CAPACITOR=1,LPF_RESISTOR=4,SYNC_ENABLE="DISABLE") in D:/Anlogic/TD5.0.43066/arch/eagle_macro.v(929)
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HDL-1200 : Current top model is clkdivider
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HDL-1100 : Inferred 0 RAMs.
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RUN-1002 : start command "optimize_rtl"
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RUN-1001 : Open license file D:/Anlogic/TD5.0.43066/license/Anlogic.lic
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RUN-1001 : Print Rtl Property
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RUN-1001 : ------------------------------------------------------
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RUN-1001 : Parameters | Settings | Default Values
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RUN-1001 : ------------------------------------------------------
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RUN-1001 : compress_add | ripple | ripple
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RUN-1001 : elf_sload | off | off
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RUN-1001 : fix_undriven | 0 | 0
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RUN-1001 : flatten | off | off
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RUN-1001 : gate_sharing | on | on
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RUN-1001 : hdl_warning_level | normal | normal
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RUN-1001 : impl_internal_tribuf | on | on
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RUN-1001 : impl_set_reset | on | on
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RUN-1001 : infer_gsr | off | off
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RUN-1001 : keep_hierarchy | auto | auto
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RUN-1001 : max_fanout | 9999 | 9999
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RUN-1001 : max_oh2bin_len | 10 | 10
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RUN-1001 : merge_equal | on | on
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RUN-1001 : merge_equiv | on | on
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RUN-1001 : merge_mux | off | off
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RUN-1001 : min_ce_fanout | 16 | 16
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RUN-1001 : min_ripple_len | auto | auto
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RUN-1001 : oh2bin_ratio | 0.08 | 0.08
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RUN-1001 : opt_adder_fanout | on | on
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RUN-1001 : opt_arith | on | on
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RUN-1001 : opt_big_gate | off | off
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RUN-1001 : opt_const | on | on
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RUN-1001 : opt_const_mult | on | on
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RUN-1001 : opt_lessthan | on | on
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RUN-1001 : opt_mux | off | off
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RUN-1001 : opt_ram | high | high
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RUN-1001 : rtl_sim_model | off | off
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RUN-1001 : seq_syn | on | on
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RUN-1001 : ------------------------------------------------------
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SYN-1012 : SanityCheck: Model "clkdivider"
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SYN-1011 : Flatten model clkdivider
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SYN-1014 : Optimize round 1
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SYN-1032 : 8/1 useful/useless nets, 3/0 useful/useless insts
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SYN-1015 : Optimize round 1, 1 better
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SYN-1014 : Optimize round 2
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SYN-1032 : 8/1 useful/useless nets, 3/1 useful/useless insts
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SYN-1015 : Optimize round 2, 0 better
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SYN-1032 : 8/1 useful/useless nets, 3/1 useful/useless insts
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RUN-1002 : start command "map_macro -nopad"
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RUN-1001 : Print Gate Property
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RUN-1001 : ----------------------------------------------------------
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RUN-1001 : Parameters | Settings | Default Values
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RUN-1001 : ----------------------------------------------------------
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RUN-1001 : auto_partition | fine | fine
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RUN-1001 : cascade_dsp | off | off
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RUN-1001 : cascade_eram | on | on
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RUN-1001 : gate_sim_model | off | off
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RUN-1001 : map_sim_model | off | off
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RUN-1001 : opt_area | medium | medium
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RUN-1001 : opt_timing | auto | auto
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RUN-1001 : pack_effort | medium | medium
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RUN-1001 : pack_lslice_ripple | on | on
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RUN-1001 : pack_lslice_ripple_ratio | 0.5 | 0.5
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RUN-1001 : pack_seq_in_io | auto | auto
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RUN-1001 : ph1_mux_ratio | 1.0 | 1.0
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RUN-1001 : report | standard | standard
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RUN-1001 : ----------------------------------------------------------
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SYN-2501 : Processed 0 LOGIC_BUF instances.
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SYN-2501 : 1 BUFG to GCLK
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SYN-2571 : Optimize after map_dsp, round 1
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SYN-1032 : 8/1 useful/useless nets, 4/1 useful/useless insts
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SYN-2571 : Optimize after map_dsp, round 1, 0 better
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SYN-2501 : Optimize round 1
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SYN-1032 : 8/1 useful/useless nets, 4/1 useful/useless insts
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SYN-2501 : Optimize round 1, 0 better
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SYN-1032 : 8/1 useful/useless nets, 4/1 useful/useless insts
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RUN-1002 : start command "write_verilog clkdivider_sim.v"
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HDL-1201 : write out verilog file clkdivider_sim.v
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GUI-2000 : Create ip file(s) successfully :{EG4S20BG256(D:/Documents/MMC/project/al_ip/clkdivider.v)}
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