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增加了interface及其封装

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lf 2020-07-22 22:29:09 +08:00
parent 43f57fe88c
commit 0cc18145b6
4 changed files with 99 additions and 14 deletions
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37
rtl/if/sm3_if.sv Normal file
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@ -0,0 +1,37 @@
`timescale 1ns / 1ps
// `include "../inc/sm3_cfg"
`include "sm3_cfg.v"
//////////////////////////////////////////////////////////////////////////////////
// Author: ljgibbs / lf_gibbs@163.com
// Create Date: 2020/07/22
// Design Name: sm3
// Module Name: sm3_if
// Description:
// SM3 总线定义
// 分为 pad/expnd/cmprss/monitor 类型
// Dependencies:
// inc/sm3_cfg.v
// Revision:
// Revision 0.01 - File Created
//////////////////////////////////////////////////////////////////////////////////
interface sm3_if;
logic clk;
logic rst_n;
logic [`INPT_DW1:0] msg_inpt_d_i;
logic [`INPT_BYTE_DW1:0] msg_inpt_vld_byte_i;
logic msg_inpt_vld_i;
logic msg_inpt_lst_i;
logic pad_otpt_ena_i;
logic msg_inpt_rdy_o;
logic pad_otpt_d_o;
logic pad_otpt_lst_o;
logic pad_otpt_vld_o;
modport PAD (
input clk,rst_n,msg_inpt_d_i,msg_inpt_vld_byte_i,msg_inpt_vld_i,msg_inpt_lst_i,pad_otpt_ena_i,
output msg_inpt_rdy_o,pad_otpt_d_o,pad_otpt_lst_o,pad_otpt_vld_o
);
endinterface //sm3_if

3
rtl/sm3_pad_core.v
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@ -1,5 +1,6 @@
`timescale 1ns / 1ps
`include "./inc/sm3_cfg"
// `include "./inc/sm3_cfg.v"
`include "sm3_cfg.v"
//////////////////////////////////////////////////////////////////////////////////
// Author: ljgibbs / lf_gibbs@163.com
// Create Date: 2020/07/19

38
rtl/wrppr/sm3_pad_core_wrapper.sv Normal file
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@ -0,0 +1,38 @@
`timescale 1ns / 1ps
`include "sm3_cfg.v"
//////////////////////////////////////////////////////////////////////////////////
// Author: ljgibbs / lf_gibbs@163.com
// Create Date: 2020/07/22
// Design Name: sm3
// Module Name: sm3_pad_core_wrapper
// Description:
// sm3_pad_core 封装
// 封装 sm3_if 总线接口，类型为 PAD
// Dependencies:
// inc/sm3_cfg.v
// Revision:
// Revision 0.01 - File Created
//////////////////////////////////////////////////////////////////////////////////
module sm3_pad_core_wrapper (
sm3_if.PAD sm3if
);
sm3_pad_core U_sm3_pad_core(
.clk (sm3if.clk ),
.rst_n (sm3if.rst_n ),
.msg_inpt_d_i (sm3if.msg_inpt_d_i ),
.msg_inpt_vld_byte_i (sm3if.msg_inpt_vld_byte_i ),
.msg_inpt_vld_i (sm3if.msg_inpt_vld_i ),
.msg_inpt_lst_i (sm3if.msg_inpt_lst_i ),
.pad_otpt_ena_i (sm3if.pad_otpt_ena_i ),
.msg_inpt_rdy_o (sm3if.msg_inpt_rdy_o ),
.pad_otpt_d_o (sm3if.pad_otpt_d_o ),
.pad_otpt_lst_o (sm3if.pad_otpt_lst_o ),
.pad_otpt_vld_o (sm3if.pad_otpt_vld_o )
);
endmodule

35
tb/tb_sm3_pad_top.sv
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@ -1,5 +1,6 @@
`timescale 1ns / 1ps
`include "./inc/sm3_cfg"
// `include "../rtl/inc/sm3_cfg"
`include "sm3_cfg.v"
//////////////////////////////////////////////////////////////////////////////////
// Author: ljgibbs / lf_gibbs@163.com
// Create Date: 2020/07/21
@ -16,21 +17,24 @@
module tb_sm3_pad_top (
);
//reg
reg clk;
reg rst_n;
//logic
logic clk;
logic rst_n;
reg [`INPT_DW1:0] msg_inpt_d_i;
reg [`INPT_BYTE_DW1:0] msg_inpt_vld_byte_i;
reg msg_inpt_vld_i;
reg msg_inpt_lst_i;
logic [`INPT_DW1:0] msg_inpt_d_i;
logic [`INPT_BYTE_DW1:0] msg_inpt_vld_byte_i;
logic msg_inpt_vld_i;
logic msg_inpt_lst_i;
reg pad_otpt_ena_i;
logic pad_otpt_ena_i;
wire msg_inpt_rdy_o;
wire pad_otpt_d_o;
wire pad_otpt_lst_o;
wire pad_otpt_vld_o;
logic msg_inpt_rdy_o;
logic pad_otpt_d_o;
logic pad_otpt_lst_o;
logic pad_otpt_vld_o;
//interface
sm3_if sm3if();
//uut
sm3_pad_core U_sm3_pad_core(
@ -51,6 +55,11 @@ sm3_pad_core U_sm3_pad_core(
.pad_otpt_vld_o (pad_otpt_vld_o )
);
//uut with bus wrapper
sm3_pad_core_wrapper U_sm3_pad_core_wrapper(
sm3if
);
initial begin
clk =0;
rst_n =0;