diff --git a/rtl/if/sm3_if.sv b/rtl/if/sm3_if.sv
new file mode 100644
index 0000000..6dda988
--- /dev/null
+++ b/rtl/if/sm3_if.sv
@@ -0,0 +1,37 @@
+`timescale 1ns / 1ps
+// `include "../inc/sm3_cfg"
+`include "sm3_cfg.v"
+//////////////////////////////////////////////////////////////////////////////////
+// Author:        ljgibbs / lf_gibbs@163.com
+// Create Date: 2020/07/22 
+// Design Name: sm3
+// Module Name: sm3_if
+// Description:
+//      SM3 总线定义
+//          分为 pad/expnd/cmprss/monitor 类型
+// Dependencies: 
+//      inc/sm3_cfg.v
+// Revision:
+// Revision 0.01 - File Created
+//////////////////////////////////////////////////////////////////////////////////
+interface sm3_if;
+    logic                       clk;
+    logic                       rst_n;
+
+    logic [`INPT_DW1:0]         msg_inpt_d_i;
+    logic [`INPT_BYTE_DW1:0]    msg_inpt_vld_byte_i;
+    logic                       msg_inpt_vld_i;
+    logic                       msg_inpt_lst_i;
+
+    logic                       pad_otpt_ena_i;
+
+    logic                       msg_inpt_rdy_o;
+    logic                       pad_otpt_d_o;
+    logic                       pad_otpt_lst_o;
+    logic                       pad_otpt_vld_o;
+
+    modport PAD (
+        input clk,rst_n,msg_inpt_d_i,msg_inpt_vld_byte_i,msg_inpt_vld_i,msg_inpt_lst_i,pad_otpt_ena_i,
+        output msg_inpt_rdy_o,pad_otpt_d_o,pad_otpt_lst_o,pad_otpt_vld_o 
+    );
+endinterface //sm3_if
\ No newline at end of file
diff --git a/rtl/sm3_pad_core.v b/rtl/sm3_pad_core.v
index d2e9eda..589dd78 100644
--- a/rtl/sm3_pad_core.v
+++ b/rtl/sm3_pad_core.v
@@ -1,5 +1,6 @@
 `timescale 1ns / 1ps
-`include "./inc/sm3_cfg"
+// `include "./inc/sm3_cfg.v"
+`include "sm3_cfg.v"
 //////////////////////////////////////////////////////////////////////////////////
 // Author:        ljgibbs / lf_gibbs@163.com
 // Create Date: 2020/07/19 
diff --git a/rtl/wrppr/sm3_pad_core_wrapper.sv b/rtl/wrppr/sm3_pad_core_wrapper.sv
new file mode 100644
index 0000000..b71e1ae
--- /dev/null
+++ b/rtl/wrppr/sm3_pad_core_wrapper.sv
@@ -0,0 +1,38 @@
+`timescale 1ns / 1ps
+`include "sm3_cfg.v"
+//////////////////////////////////////////////////////////////////////////////////
+// Author:        ljgibbs / lf_gibbs@163.com
+// Create Date: 2020/07/22 
+// Design Name: sm3
+// Module Name: sm3_pad_core_wrapper
+// Description:
+//      sm3_pad_core 封装
+//          封装 sm3_if 总线接口，类型为 PAD
+// Dependencies: 
+//      inc/sm3_cfg.v
+// Revision:
+// Revision 0.01 - File Created
+//////////////////////////////////////////////////////////////////////////////////
+module sm3_pad_core_wrapper (
+    sm3_if.PAD sm3if
+);
+
+sm3_pad_core U_sm3_pad_core(
+    .clk                    (sm3if.clk                    ),
+    .rst_n                  (sm3if.rst_n                  ),
+
+    .msg_inpt_d_i           (sm3if.msg_inpt_d_i           ),
+    .msg_inpt_vld_byte_i    (sm3if.msg_inpt_vld_byte_i    ),
+    .msg_inpt_vld_i         (sm3if.msg_inpt_vld_i         ),
+    .msg_inpt_lst_i         (sm3if.msg_inpt_lst_i         ),
+
+    .pad_otpt_ena_i         (sm3if.pad_otpt_ena_i         ),
+
+    .msg_inpt_rdy_o         (sm3if.msg_inpt_rdy_o         ),
+
+    .pad_otpt_d_o           (sm3if.pad_otpt_d_o           ),
+    .pad_otpt_lst_o         (sm3if.pad_otpt_lst_o         ),
+    .pad_otpt_vld_o         (sm3if.pad_otpt_vld_o         )
+);   
+    
+endmodule
\ No newline at end of file
diff --git a/tb/tb_sm3_pad_top.sv b/tb/tb_sm3_pad_top.sv
index 40f23dd..13ffd3e 100644
--- a/tb/tb_sm3_pad_top.sv
+++ b/tb/tb_sm3_pad_top.sv
@@ -1,5 +1,6 @@
 `timescale 1ns / 1ps
-`include "./inc/sm3_cfg"
+// `include "../rtl/inc/sm3_cfg"
+`include "sm3_cfg.v"
 //////////////////////////////////////////////////////////////////////////////////
 // Author:        ljgibbs / lf_gibbs@163.com
 // Create Date: 2020/07/21 
@@ -16,21 +17,24 @@
 module tb_sm3_pad_top (                 
 );
 
-//reg
-reg                     clk;
-reg                     rst_n;
+//logic
+logic                       clk;
+logic                       rst_n;
 
-reg [`INPT_DW1:0]       msg_inpt_d_i;
-reg [`INPT_BYTE_DW1:0]  msg_inpt_vld_byte_i;
-reg                     msg_inpt_vld_i;
-reg                     msg_inpt_lst_i;
+logic [`INPT_DW1:0]         msg_inpt_d_i;
+logic [`INPT_BYTE_DW1:0]    msg_inpt_vld_byte_i;
+logic                       msg_inpt_vld_i;
+logic                       msg_inpt_lst_i;
 
-reg                     pad_otpt_ena_i;
+logic                       pad_otpt_ena_i;
 
-wire                    msg_inpt_rdy_o;
-wire                    pad_otpt_d_o;
-wire                    pad_otpt_lst_o;
-wire                    pad_otpt_vld_o;
+logic                       msg_inpt_rdy_o;
+logic                       pad_otpt_d_o;
+logic                       pad_otpt_lst_o;
+logic                       pad_otpt_vld_o;
+
+//interface
+sm3_if sm3if();
 
 //uut
 sm3_pad_core U_sm3_pad_core(
@@ -51,6 +55,11 @@ sm3_pad_core U_sm3_pad_core(
     .pad_otpt_vld_o         (pad_otpt_vld_o         )
 );
 
+//uut with bus wrapper
+sm3_pad_core_wrapper U_sm3_pad_core_wrapper(
+    sm3if
+);
+
 initial begin
     clk                     =0;
     rst_n                   =0;