From 48370215397b52e892e217debdf930ba71dc5a17 Mon Sep 17 00:00:00 2001 From: lf <15201710458@163.com> Date: Tue, 28 Jul 2020 22:19:22 +0800 Subject: [PATCH] =?UTF-8?q?=E5=AE=8C=E5=96=84=E8=BF=AD=E4=BB=A3=E5=8E=8B?= =?UTF-8?q?=E7=BC=A9=E6=A8=A1=E5=9D=97=E7=9A=84=E4=BB=A3=E7=A0=81?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- rtl/inc/sm3_cfg.v | 7 +- rtl/sm3_cmprss_ceil_comb.v | 127 ++++++++++++++++++++++++++++++++++++ rtl/sm3_cmprss_core.v | 2 + rtl/util/adder_32b.v | 31 +++++++++ rtl/util/csa_adder_3i_32b.v | 43 ++++++++++++ rtl/util/sm3_adder.v | 56 ++++++++++++++++ 6 files changed, 265 insertions(+), 1 deletion(-) create mode 100644 rtl/sm3_cmprss_ceil_comb.v create mode 100644 rtl/util/adder_32b.v create mode 100644 rtl/util/csa_adder_3i_32b.v create mode 100644 rtl/util/sm3_adder.v diff --git a/rtl/inc/sm3_cfg.v b/rtl/inc/sm3_cfg.v index 5107209..588d4e2 100644 --- a/rtl/inc/sm3_cfg.v +++ b/rtl/inc/sm3_cfg.v @@ -57,4 +57,9 @@ `define OTPT_DW1 (OTPT_DW - 1) //定义 SM3 字扩展模式----------------------- -`define SM3_EXPND_PRE_LOAD_REG \ No newline at end of file +`define SM3_EXPND_PRE_LOAD_REG + +//定义 SM3 迭代压缩中的加法方式----------------------- +//直接使用加法符，使工具推断 +`define SM3_CMPRSS_DIRECT_ADD +`define SM3_CMPRSS_CSA_ADD \ No newline at end of file diff --git a/rtl/sm3_cmprss_ceil_comb.v b/rtl/sm3_cmprss_ceil_comb.v new file mode 100644 index 0000000..ff2b9d3 --- /dev/null +++ b/rtl/sm3_cmprss_ceil_comb.v @@ -0,0 +1,127 @@ +`timescale 1ns / 1ps +`include "sm3_cfg.v" +////////////////////////////////////////////////////////////////////////////////// +// Author: ljgibbs / lf_gibbs@163.com +// Create Date: 2020/07/28 +// Design Name: sm3 +// Module Name: sm3_cmprss_ceil_comb +// Description: +// SM3 单轮迭代压缩模块 由组合逻辑构成 +// +// Dependencies: +// inc/sm3_cfg.v +// Revision: +// Revision 0.01 - File Created +////////////////////////////////////////////////////////////////////////////////// +module sm3_cmprss_ceil_comb( + input cmprss_round_sm_16_i, + input [31:0] tj_i, + + input [31:0] reg_a_i, + input [31:0] reg_b_i, + input [31:0] reg_c_i, + input [31:0] reg_d_i, + input [31:0] reg_e_i, + input [31:0] reg_f_i, + input [31:0] reg_g_i, + input [31:0] reg_h_i, + + input [31:0] wj_i, + input [31:0] wjj_i, + + output [31:0] reg_a_o, + output [31:0] reg_b_o, + output [31:0] reg_c_o, + output [31:0] reg_d_o, + output [31:0] reg_e_o, + output [31:0] reg_f_o, + output [31:0] reg_g_o, + output [31:0] reg_h_o + ); + + +//wire +wire [31:0] tmp_for_ss1_0 ; +wire [31:0] tmp_for_ss1_2 ; +wire [31:0] ss1 ; +wire [31:0] ss2 ; +wire [31:0] tmp_for_tt1_0 ; +wire [31:0] tmp_for_tt1_1 ; +wire [31:0] tt1 ; +wire [31:0] tmp_for_tt2_0 ; +wire [31:0] tmp_for_tt2_1 ; +wire [31:0] tt2 ; +wire [31:0] tt2_after_p0 ; + +wire [31:0] TJ = tj_i; + +//加法器0 +`ifdef SM3_CMPRSS_DIRECT_ADD + assign tmp_for_ss1_0 = {reg_a_i[31-12:0], reg_a_i[31:31-12+1]} + reg_e_i; + assign tmp_for_ss1_2 = tmp_for_ss1_0 + TJ; +`else + sm3_adder U_ss1( + .A({reg_a_i[31-12:0], reg_a_i[31:31-12+1]}), + .B(reg_e_i), + .C(TJ), + .R(tmp_for_ss1_2) + ); +`endif + +assign ss1 = {tmp_for_ss1_2[31 - 7 : 0], tmp_for_ss1_2[31 : 31 - 7 + 1]}; +assign ss2 = ss1 ^ {reg_a_i[31 - 12 : 0], reg_a_i[31 : 31 - 12 + 1]}; + +//加法器1 +assign tmp_for_tt1_0 = cmprss_round_sm_16_i? reg_a_i ^ reg_b_i ^ reg_c_i : (reg_a_i & reg_b_i | reg_a_i & reg_c_i | reg_b_i & reg_c_i); +`ifdef SM3_CMPRSS_DIRECT_ADD + assign tmp_for_tt1_1 = reg_d_i + ss2 + wjj_i; + assign tt1 = tmp_for_tt1_0 + tmp_for_tt1_1; +`else + //tmp_for_tt1_1 = reg_d_i + tmp_for_tt1_0 + wjj_i + sm3_adder U_tmp_for_tt1_1( + .A(reg_d_i), + .B(tmp_for_tt1_0), + .C(wjj_i), + .R(tmp_for_tt1_1) + ); + //tt1 = ss2 + tmp_for_tt1_1 + adder_32b U_tt1( + .A(ss2), + .B(tmp_for_tt1_1), + .R(tt1) + ); +`endif + +//加法器2 +assign tmp_for_tt2_0 = cmprss_round_sm_16_i? reg_e_i ^ reg_f_i ^ reg_g_i : (reg_e_i & reg_f_i | ~reg_e_i & reg_g_i); +`ifdef SM3_CMPRSS_DIRECT_ADD + assign tmp_for_tt2_1 = reg_h_i + ss1 + wj_i; + assign tt2 = tmp_for_tt2_0 + tmp_for_tt2_1; +`else + //tmp_for_tt2_1 = reg_h_i + tmp_for_tt2_0 + wj_i + sm3_adder U_tmp_for_tt2_1( + .A(reg_h_i), + .B(tmp_for_tt2_0), + .C(wj_i), + .R(tmp_for_tt2_1) + ); + //tt2 = ss1 + tmp_for_tt2_1 + adder_32b U_tt2( + .A(ss1), + .B(tmp_for_tt2_1), + .R(tt2) + ); +`endif + +assign tt2_after_p0 = tt2 ^ {tt2[31-9:0], tt2[31:31-9+1]} ^ {tt2[31-17:0], tt2[31:31-17+1]}; + +assign reg_a_o = tt1; +assign reg_b_o = reg_a_i; +assign reg_c_o = {reg_b_i[31 - 9 : 0], reg_b_i[31 : 31 - 9 + 1]}; +assign reg_d_o = reg_c_i; +assign reg_e_o = tt2_after_p0; +assign reg_f_o = reg_e_i; +assign reg_g_o = {reg_f_i[31 - 19 : 0], reg_f_i[31 : 31 - 19 + 1]}; +assign reg_h_o = reg_g_i; + +endmodule diff --git a/rtl/sm3_cmprss_core.v b/rtl/sm3_cmprss_core.v index eb8380e..d1cdb6b 100644 --- a/rtl/sm3_cmprss_core.v +++ b/rtl/sm3_cmprss_core.v @@ -1,3 +1,5 @@ +`timescale 1ns / 1ps +`include "sm3_cfg.v" ////////////////////////////////////////////////////////////////////////////////// // Author: ljgibbs / lf_gibbs@163.com // Create Date: 2020/07/27 diff --git a/rtl/util/adder_32b.v b/rtl/util/adder_32b.v new file mode 100644 index 0000000..df4d9ff --- /dev/null +++ b/rtl/util/adder_32b.v @@ -0,0 +1,31 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: SHU +// Engineer: lf +// +// Create Date: 2020/04/26 16:24:02 +// Design Name: +// Module Name: adder_32b +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// 32 位 加法器 性能分析用 +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module adder_32b( + input [31:0] A, + input [31:0] B, + output [31:0] R + ); + wire [32:0] R_tmp; + assign R_tmp = A + B; + assign R = R_tmp[31:0]; +endmodule diff --git a/rtl/util/csa_adder_3i_32b.v b/rtl/util/csa_adder_3i_32b.v new file mode 100644 index 0000000..d269b4f --- /dev/null +++ b/rtl/util/csa_adder_3i_32b.v @@ -0,0 +1,43 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: SHU +// Engineer: lf +// +// Create Date: 2020/04/26 16:24:02 +// Design Name: +// Module Name: csa_adder_3i_32b +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// 32 位 3 输入 CSA 加法器，不考虑进位 +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module csa_adder_3i_32b( + input [31:0] A, + input [31:0] B, + input [31:0] C, + output [31:0] R + ); + + wire [31:0] S; + wire [31:0] Ca; + wire [33:0] R_tmp; + + //3-2 CSA + assign S = A ^ B ^ C; + assign Ca = (A & B) | (A & C) | (B & C); + + //加法器 + assign R_tmp = {Ca,{1'b0}} + S; + + //输出端口,取低位，不考虑进位 + assign R = R_tmp[31:0]; +endmodule diff --git a/rtl/util/sm3_adder.v b/rtl/util/sm3_adder.v new file mode 100644 index 0000000..69f4777 --- /dev/null +++ b/rtl/util/sm3_adder.v @@ -0,0 +1,56 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: SHU +// Engineer: lf +// +// Create Date: 2020/04/26 16:24:02 +// Design Name: +// Module Name: sm3_adder +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// SM3 32 位 3 输入 加法器， +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module sm3_adder( + input [31:0] A, + input [31:0] B, + input [31:0] C, + output [31:0] R + ); + + `define USE_CSA + + `ifdef USE_CSA + //使用CSA加法器 + csa_adder_3i_32b U_csa_adder_3i_32b( + .A(A), + .B(B), + .C(C), + .R(R) + ); + `else + //使用两级加法器 + wire [31:0] tmp; + adder_32b U_adder_0( + .A(A), + .B(B), + .R(tmp) + ); + adder_32b U_adder_1( + .A(tmp), + .B(C), + .R(R) + ); + + `endif + +endmodule